Nexperia-PBSS4230PANP-115
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PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
14 December 2012
Product data sheet
1. General
description
NPN/PNP low V
CEsat
Breakthrough In Small Signal (BISS) transistor in a leadless
medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package.
NPN/NPN complement: PBSS4230PAN. PNP/PNP complement: PBSS5230PA
P
.
2. Features
and benefits
Very low collector-emitter saturation voltage V
CEsat
High collector current capability I
C
and I
CM
High collector current gain h
FE
at high I
C
Reduced Printed-Circuit Board (PCB) requirements
High efficiency due to less heat generation
AEC-Q101 qualified
•
•
•
•
•
•
3. Applications
Load switch
•
•
•
•
•
Battery-driven devices
Power management
Charging circuits
Power switches (e.g. motors, fans)
4. Quick
reference data
Table 1.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor; for the PNP transistor with negative polarity
V
CEO
collector-emitter
voltage
open base
–
–
30
V
I
C
collector current
–
–
–
–
2
3
A
A
I
CM
peak collector current
single pulse; t
p
≤ 1 ms
TR1 (NPN)
R
CEsat
collector-emitter
I
C
= 1 A; I
B
= 100 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
–
–
145
mΩ
saturation resistance
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Symbol
TR2 (PNP)
R
CEsat
Parameter
Conditions
Min
Typ
Max
Unit
collector-emitter
I
C
= -1 A; I
B
= -100 mA; pulsed;
–
–
195
mΩ
saturation resistance
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
5. Pinning
information
Table 2.
Pin
Pinning information
Symbol Description
Simplified outline
Graphic symbol
C1 B2
1
2
3
4
5
6
7
8
E1
B1
C2
E2
B2
C1
C1
C2
emitter TR1
base TR1
E2
6
5
4
TR2
7
8
collector TR2
emitter TR2
base TR2
TR1
E1
B1 C2
sym139
1
2
3
Transparent top view
collector TR1
collector TR1
collector TR2
DFN2020-6 (SOT1118)
6. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
SOT1118
PBSS4230PANP
DFN2020-6
plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body 2 x 2 x 0.65 mm
7. Marking
Table 4.
Marking codes
Type number
Marking code
PBSS4230PANP
2J
8. Limiting
values
Table 5.
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Limiting values
Min
Max
Unit
Per transistor; for the PNP transistor with negative polarity
V
CBO
collector-base voltage
collector-emitter voltage
open emitter
–
30
30
V
V
V
CEO
open base
–
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
2 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Symbol
V
EBO
I
C
Parameter
Conditions
Min
Max
7
Unit
V
emitter-base voltage
collector current
peak collector current
base current
open collector
–
–
–
–
–
–
–
–
–
–
–
–
–
2
A
I
CM
single pulse; t
p
≤ 1 ms
3
A
I
B
0.3
1
A
I
BM
peak base current
total power dissipation
single pulse; t
p
≤ 1 ms
T
amb
≤ 25 °C
A
P
tot
370
570
530
700
450
760
700
mW
mW
mW
mW
mW
mW
mW
1450 mW
Per device
P
tot
total power dissipation
T
amb
≤ 25 °C
–
510
780
730
960
620
mW
mW
mW
mW
mW
–
–
–
–
–
1040 mW
960 mW
2000 mW
–
–
T
j
junction temperature
ambient temperature
storage temperature
–
150
150
150
°C
°C
°C
T
amb
T
stg
-55
-65
[1] Device
mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device
mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm
2
.
[3] Device
mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm
2
.
[4]
[5] Device
mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device
mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm
2
.
[7] Device
mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm
2
.
[8]
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
3 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad165
1.5
(1)
P
tot
(W)
1.0
(2)
(3) (4)
(5)
(6)
(7)
(8)
0.5
0
-75
-25
25
75
125
175
(°C)
T
amb
(1) 4-layer PCB 70 µm, mounting pad for collector 1 cm
2
(2) FR4 PCB 70 µm, mounting pad for collector 1 cm
2
(3) 4-layer PCB 70 µm, standard footprint
(4) 4-layer PCB 35 µm, mounting pad for collector 1 cm
2
(5) FR4 PCB 35 µm, mounting pad for collector 1 cm
2
(6) 4-layer PCB 35 µm, standard footprint
(7) FR4 PCB 70 µm, standard footprint
(8) FR4 PCB 35 µm, standard footprint
Fig. 1.
Per transistor: power derating curves
9. Thermal
characteristics
Table 6.
Symbol
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
R
th(j-a)
thermal resistance
from junction to
ambient
in free air
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
338
219
236
179
278
164
179
86
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
R
th(j-sp)
thermal resistance
from junction to solder
point
30
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
4 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Symbol
Per device
R
th(j-a)
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance
from junction to
ambient
in free air
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
245
160
171
130
202
120
130
63
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
[1] Device
mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
[2] Device
mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm
2
.
[3] Device
mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm
2
.
[4]
[5] Device
mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
[6] Device
mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm
2
.
[7] Device
mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm
2
.
[8]
006aad166
3
10
Z
duty cycle = 1
th(j-a)
(K/W)
0.75
0.5
2
0.33
10
0.2
0.1
0.05
10
0.02
0.01
0
1
10
-5
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 35 µm, standard footprint
Fig. 2.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
5 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad167
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
10
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 35 µm, mounting pad for collector 1 cm
2
Fig. 3.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad168
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
0.5
10
0.33
0.2
0.1
0.05
10
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 35 µm, standard footprint
Fig. 4.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
6 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad169
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
2
10
0.5
0.33
0.2
0.1
0.05
10
0.02
0
0.01
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 35 µm, mounting pad for collector 1 cm
2
Fig. 5.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aac610
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
0.5
0.33
2
10
0.2
0.1
0.05
10
0.02
0.01
0
1
10
– 5
– 4
– 3
10
– 2
– 1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 70 µm, standard footprint
Fig. 6.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
7 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aac611
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
2
0.75
0.5
10
0.33
0.2
0.1
10
0.05
0.02
0.01
0
1
10
– 5
– 4
– 3
10
– 2
– 1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB 70 µm, mounting pad for collector 1 cm
2
Fig. 7.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aad170
3
10
Z
th(j-a)
(K/W)
duty cycle = 1
0.75
0.5
2
10
0.33
0.2
0.1
0.05
10
0.02
0
0.01
-4
1
-5
10
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 70 µm, standard footprint
Fig. 8.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
8 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad171
2
10
duty cycle = 1
0.75
0.5
0.2
Z
th(j-a)
(K/W)
0.33
10
0.1
0.05
0.02
0.01
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
4-layer PCB 70 µm, mounting pad for collector 1 cm
2
Fig. 9.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
10. Characteristics
Table 7.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
TR1 (NPN)
I
CBO
collector-base cut-off
V
CB
= 24 V; I
E
= 0 A; T
amb
= 25 °C
V
CB
= 24 V; I
E
= 0 A; T
j
= 150 °C
V
EB
= 5 V; I
C
= 0 A; T
amb
= 25 °C
–
–
–
–
–
–
100
50
nA
µA
nA
current
I
EBO
emitter-base cut-off
current
100
h
FE
DC current gain
V
CE
= 2 V; I
C
= 100 mA; pulsed;
250
230
200
150
380
350
310
230
–
–
–
–
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
CE
= 2 V; I
C
= 500 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
CE
= 2 V; I
C
= 1 A; pulsed; t
p
≤ 300 µs;
δ ≤ 0.02 ; T
amb
= 25 °C
V
CE
= 2 V; I
C
= 2 A; pulsed; t
p
≤ 300 µs;
δ ≤ 0.02 ; T
amb
= 25 °C
V
CEsat
collector-emitter
I
C
= 500 mA; I
B
= 50 mA; T
amb
= 25 °C
–
–
60
80
mV
mV
saturation voltage
I
C
= 1 A; I
B
= 50 mA; pulsed;
120
160
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= 2 A; I
B
= 100 mA; pulsed;
–
–
230
300
290
mV
mV
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= 2 A; I
B
= 200 mA; pulsed;
220
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
9 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
CEsat
collector-emitter
I
C
= 1 A; I
B
= 100 mA; pulsed;
–
–
145
mΩ
saturation resistance
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
BEsat
base-emitter saturation
I
C
= 500 mA; I
B
= 50 mA; T
amb
= 25 °C
–
–
–
–
1
1
V
V
voltage
I
C
= 1 A; I
B
= 50 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= 2 A; I
B
= 100 mA; pulsed;
–
–
–
–
–
–
1.1
1.2
0.9
V
V
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= 2 A; I
B
= 200 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
BEon
base-emitter turn-on
voltage
V
CE
= 2 V; I
C
= 0.5 A; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
t
d
t
r
delay time
V
CC
= 12.5 V; I
C
= 1 A; I
Bon
= 50 mA;
I
Boff
= -50 mA; T
amb
= 25 °C
–
10
–
–
–
–
–
–
–
ns
rise time
–
50
ns
t
on
t
s
turn-on time
storage time
fall time
–
60
ns
–
310
60
ns
t
f
–
ns
t
off
f
T
turn-off time
transition frequency
–
370
120
ns
V
CE
= 10 V; I
C
= 50 mA; f = 100 MHz;
T
amb
= 25 °C
60
MHz
C
c
collector capacitance
V
CB
= 10 V; I
E
= 0 A; i
e
= 0 A;
f = 1 MHz; T
amb
= 25 °C
–
13.5
18
pF
TR2 (PNP)
I
CBO
collector-base cut-off
current
V
CB
= -24 V; I
E
= 0 A
–
–
–
–
–
–
-100
-50
nA
µA
nA
V
CB
= -24 V; I
E
= 0 A; T
j
= 150 °C
V
EB
= -5 V; I
C
= 0 A
I
EBO
emitter-base cut-off
current
-100
h
FE
DC current gain
V
CE
= -2 V; I
C
= -100 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
260
210
160
100
–
370
290
230
145
-75
–
V
CE
= -2 V; I
C
= -500 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
–
V
CE
= -2 V; I
C
= -1 A; pulsed;
–
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
CE
= -2 V; I
C
= -2 A; pulsed;
–
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
CEsat
collector-emitter
I
C
= -500 mA; I
B
= -50 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
-110
-220
mV
mV
saturation voltage
I
C
= -1 A; I
B
= -50 mA; pulsed;
–
-155
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
©
PBSS4230PANP
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
10 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I
C
= -2 A; I
B
= -100 mA; pulsed;
–
-295
-420
mV
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= -2 A; I
B
= -200 mA; pulsed;
–
–
–
–
–
–
–
-275
-390
195
-1
mV
mΩ
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
R
CEsat
collector-emitter
I
C
= -1 A; I
B
= -100 mA; pulsed;
–
–
–
–
–
–
saturation resistance
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
BEsat
base-emitter saturation
I
C
= -500 mA; I
B
= -50 mA; pulsed;
voltage
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= -1 A; I
B
= -50 mA; pulsed;
-1
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= -2 A; I
B
= -100 mA; pulsed;
-1.1
-1.2
-0.9
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
I
C
= -2 A; I
B
= -200 mA; pulsed;
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
V
BEon
base-emitter turn-on
voltage
V
CE
= -2 V; I
C
= -0.5 A; pulsed;
V
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
t
d
t
r
delay time
V
CC
= -12.5 V; I
C
= -1 A; I
Bon
= -0.05 A;
I
Boff
= 0.05 A; T
amb
= 25 °C
–
10
–
–
–
–
–
–
–
ns
rise time
–
50
ns
t
on
t
s
turn-on time
storage time
fall time
–
60
ns
–
200
45
ns
t
f
–
ns
t
off
f
T
turn-off time
transition frequency
–
245
95
ns
V
CE
= -10 V; I
C
= -50 mA; f = 100 MHz;
T
amb
= 25 °C
50
MHz
C
c
collector capacitance
V
CB
= -10 V; I
E
= 0 A; i
e
= 0 A;
f = 1 MHz; T
amb
= 25 °C
–
22
29
pF
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
11 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad188
006aad189
600
3
I
= 15 mA
13.5 12
10.5
B
(1)
(2)
h
I
C
(A)
FE
9
400
2
1
0
7.5
6
4.5
(3)
200
3
1.5
0
10
-1
2
3
4
1
10
10
10
10
(mA)
0
1
2
3
4
5
I
V
(V)
CE
C
V
CE
= 2 V
T
amb
= 25 °C
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 11.
TR1 (NPN): Collector current as a function of
collector-emitter voltage; typical values
Fig. 10.
TR1 (NPN): DC current gain as a function of
collector current; typical values
006aad190
006aad191
1.2
1.2
V
BEsat
(V)
V
BE
(V)
1.0
0.8
0.6
0.4
0.2
(1)
0.8
(1)
(2)
(3)
(2)
(3)
0.4
0
10
-1
2
3
4
-1
2
3
4
1
10
10
10
10
(mA)
10
1
10
10
10
10
I (mA)
C
I
C
V
CE
= 2 V
I
C
/I
B
= 20
(1) T
amb
= −55 °C
(2) T
amb
= 25 °C
(3) T
amb
= 100 °C
(1) T
amb
= −55 °C
(2) T
amb
= 25 °C
(3) T
amb
= 100 °C
Fig. 12.
TR1 (NPN): Base-emitter voltage as a function
of collector current; typical values
Fig. 13.
TR1 (NPN): Base-emitter saturation voltage as a
function of collector current; typical values
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
12 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad192
006aad193
1
1
V
V
CEsat
(V)
CEsat
(V)
-1
-1
(1)
10
10
10
10
10
10
(2)
(1)
(2)
(3)
-2
-3
-2
-3
(3)
-1
2
3
4
-1
2
3
4
10
1
10
10
10
10
(mA)
10
1
10
10
10
10
I (mA)
C
I
C
I
C
/I
B
= 20
T
amb
= 25 °C
(1) I
C
/I
B
= 100
(2) I
C
/I
B
= 50
(3) I
C
/I
B
= 10
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 14.
TR1 (NPN): Collector-emitter saturation voltage
Fig. 15.
TR1 (NPN): Collector-emitter saturation voltage
as a function of collector current; typical values
as a function of collector current; typical values
006aad194
006aad195
3
3
10
10
R
CEsat
(Ω)
R
CEsat
(Ω)
2
2
10
10
(1)
10
10
(1)
(2)
(3)
1
1
(2)
-1
-1
10
10
10
10
(3)
-2
-2
-1
2
3
4
-1
2
3
4
10
1
10
10
10
10
(mA)
10
1
10
10
10
10
I (mA)
C
I
C
I
C
/I
B
= 20
T
amb
= 25 °C
(1) I
C
/I
B
= 100
(2) I
C
/I
B
= 50
(3) I
C
/I
B
= 10
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 16.
TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
Fig. 17.
TR1 (NPN): Collector-emitter saturation
resistance as a function of collector current;
typical values
©
PBSS4230PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
13 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad196
006aad197
600
-3
I
B
= -30 mA
-27 -24 -21
(1)
(2)
h
I
C
(A)
FE
-18
-15
400
-2
-1
0
-12
-9
-6
-3
200
(3)
0
-10
-1
2
3
4
-1
-10
-10
-10
-10
(mA)
0
-1
-2
-3
-4
-5
I
C
V
(V)
CE
V
CE
= −2 V
T
amb
= 25 °C
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 19.
TR2 (PNP): Collector current as a function of
collector-emitter voltage; typical values
Fig. 18.
TR2 (PNP): DC current gain as a function of
collector current; typical values
006aad198
006aad199
-1.2
-1.2
V
BEsat
(V)
V
BE
(V)
-1.0
-0.8
-0.6
-0.4
-0.2
-0.8
(1)
(2)
(3)
(1)
(2)
(3)
-0.4
0
-10
-1
2
3
4
-1
2
3
4
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
V
CE
= −2 V
I
C
/I
B
= 20
(1) T
amb
= −55 °C
(2) T
amb
= 25 °C
(3) T
amb
= 100 °C
(1) T
amb
= −55 °C
(2) T
amb
= 25 °C
(3) T
amb
= 100 °C
Fig. 20.
TR2 (PNP): Base-emitter voltage as a function
of collector current; typical values
Fig. 21.
TR2 (PNP): Base-emitter saturation voltage as a
function of collector current; typical values
©
PBSS4230PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
14 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
006aad200
006aad201
-1
-10
V
CEsat
(V)
V
CEsat
(V)
-1
-1
-10
-10
-10
(1)
-1
-2
-3
(2)
-10
-10
-10
(1)
(2)
-2
-3
(3)
(3)
-1
2
3
4
-1
2
3
4
-10
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
I
C
/I
B
= 20
T
amb
= 25 °C
(1) I
C
/I
B
= 100
(2) I
C
/I
B
= 50
(3) I
C
/I
B
= 10
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 22.
TR2 (PNP): Collector-emitter saturation voltage
Fig. 23.
TR2 (PNP): Collector-emitter saturation voltage
as a function of collector current; typical values
as a function of collector current; typical values
006aad202
006aad203
3
3
10
10
R
CEsat
(Ω)
R
CEsat
(Ω)
(1)
(2)
2
10
2
10
10
(3)
10
1
(1)
(2)
1
-1
10
10
(3)
-1
-2
10
-1
2
3
4
-1
2
3
4
-10
-1
-10
-10
-10
-10
(mA)
-10
-1
-10
-10
-10
-10
I (mA)
C
I
C
I
C
/I
B
= 20
T
amb
= 25 °C
(1) I
C
/I
B
= 100
(2) I
C
/I
B
= 50
(3) I
C
/I
B
= 10
(1) T
amb
= 100 °C
(2) T
amb
= 25 °C
(3) T
amb
= −55 °C
Fig. 24.
TR2 (PNP): Collector-emitter saturation
Fig. 25.
TR2 (PNP): Collector-emitter saturation
resistance as a function of collector current;
typical values
resistance as a function of collector current;
typical values
©
PBSS4230PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
15 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
11. Test
information
Fig. 26.
TR1 (NPN): BISS transistor switching time definition
Fig. 27.
TR1 (NPN): Test circuit for switching times
©
PBSS4230PANP
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Product data sheet
14 December 2012
16 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
Fig. 28.
TR2 (PNP): BISS transistor switching time definition
Fig. 29.
TR2 (PNP): Test circuit for switching times
11.1 Quality
information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard
Q101 – Stress test qualification for discrete semiconductors
, and is
suitable for use in automotive applications.
©
PBSS4230PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
17 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
12. Package outline
2.1
1.9
0.65
max
1.1
0.9
0.04
max
0.77
0.57
(2×)
3
4
6
0.65
(4×)
2.1
1.9
0.54
0.44
(2×)
0.35
0.25
(6×)
1
0.3
0.2
Dimensions in mm
10-05-31
Fig. 30.
Package outline DFN2020-6 (SOT1118)
13. Soldering
2.1
0.65
0.65
0.49
0.49
0.3 0.4
(6×) (6×)
solder lands
0.875
0.875
solder paste
1.05 1.15
2.25
(2×) (2×)
solder resist
occupied area
Dimensions in mm
0.35
(6×)
0.72
(2×)
0.45
(6×)
0.82
(2×)
sot1118_fr
Fig. 31.
Reflow soldering footprint for DFN2020-6 (SOT1118)
14. Revision history
Table 8.
Revision history
Data sheet ID
Release date
Data sheet status
Change notice
Supersedes
PBSS4230PANP v.1
20121214
Product data sheet
–
–
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PBSS4230PANP
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Product data sheet
14 December 2012
18 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including – without limitation –
lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
15. Legal information
15.1 Data
sheet status
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
Terms and conditions of commercial sale
of Nexperia.
Document
Product
Definition
Objective
[short] data
sheet
Development This
document contains data from
the objective specification for product
development.
Right to make changes
— Nexperia reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Preliminary
[short] data
sheet
Qualification This
document contains data from the
preliminary specification.
Suitability for use in automotive applications
— This Nexperia
product has been qualified for use in automotive
Product
[short] data
sheet
Production
This document contains the product
specification.
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
[1] Please
consult the most recently issued document before initiating or
completing a design.
[2] The
term ‘short data sheet’ is explained in section “Definitions”.
[3] The
product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
15.2 Definitions
Applications
— Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Preview
— The document is a preview version only. The document is still
subject to formal approval, which may result in modifications or additions.
Nexperia does not give any representations or warranties as to
the accuracy or completeness of information included herein and shall have
no liability for the consequences of use of such information.
Customers are responsible for the design and operation of their
applications and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the Nexperia product is suitable and fit for the
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Short data sheet
— A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications
short data sheet, the full data sheet shall prevail.
and the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Product specification
— The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
15.3 Disclaimers
Terms and conditions of commercial sale
— Nexperia
Limited warranty and liability
— Information in this document is believed
to be accurate and reliable. However, Nexperia does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
products are sold subject to the general terms and conditions of commercial
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
©
PBSS4230PANP
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Nexperia B.V. 2017. All rights reserved
Product data sheet
14 December 2012
19 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
No offer to sell or license
— Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control
— This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations
— A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
PBSS4230PANP
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Product data sheet
14 December 2012
20 / 21
Nexperia
PBSS4230PANP
30
V
, 2 A
N
PN/PNP low VCEsat (BISS) transistor
16. Contents
1
2
3
4
5
6
7
8
9
10
11
11.1
Quality information …………………………………..
12
13
14
15
15.1
15.2
15.3
15.4
©
Nexperia B.V. 2017. All rights reserved
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
14 December 2012
©
PBSS4230PANP
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Product data sheet
14 December 2012
21 / 21
