Nexperia-PDTA113ZU-115
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Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia
. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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– © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
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Should be replaced with:
–
© Nexperia B.V. (year). All rights reserved
.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
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Kind regards,
Team Nexperia
PDTA113Z series
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Rev. 04 — 2 September 2009
Product data sheet
1. Product
profile
1.1 General
description
PNP resistor-equipped transistors.
Table 1.
Product overview
Type number
Package
NXP
NPN complement
JEITA
SC-75
SC-59
SC-101
SC-43A
–
PD
T
A
113ZE
PD
T
A
113ZK
PD
T
A
113ZM
PD
T
A
113ZS
[1]
PD
T
A
113ZT
PD
T
A
113ZU
SOT416
SOT346
SOT883
SOT54 (TO-92)
SOT23
PDTC113ZE
PDTC113ZK
PDTC113ZM
PDTC113ZS
PDTC113ZT
PDTC113ZU
SOT323
SC-70
[1] Also
available in SOT54A and SOT54 variant packages (see
Section 2
).
1.2 Features
I
Built-in bias resistors
I
Reduces component count
I
Simplifies circuit design
I
Reduces pick and place costs
1.3 Applications
I
General purpose switching and
I
Circuit drivers
amplification
I
Inverter and interface circuits
1.4 Quick
reference data
Table 2.
Symbol
V
CEO
I
O
Quick reference data
Parameter
Conditions
Min
Typ
Max
−
50
−
100
1.3
Unit
V
collector-emitter voltage
output current (DC)
bias resistor 1 (input)
bias resistor ratio
open base
–
–
–
–
mA
k
Ω
R1
0.7
8
1
10
R2/R1
12
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
2. Pinning
information
Table 3.
Pinning
Pin
Description
Simplified outline
Symbol
SOT54
1
2
3
input (base)
2
3
output (collector)
GND (emitter)
R1
1
1
1
1
2
3
R2
001aab347
006aaa148
SOT54A
1
2
3
input (base)
2
3
output (collector)
GND (emitter)
R1
1
2
R2
3
001aab348
006aaa148
SOT54 variant
1
2
3
input (base)
2
3
output (collector)
GND (emitter)
R1
1
2
3
R2
001aab447
006aaa148
SOT23, SOT323, SOT346, SOT416
1
2
3
input (base)
3
3
GND (emitter)
output (collector)
R1
1
R2
1
2
2
006aaa144
sym003
SOT883
1
2
3
input (base)
1
2
3
2
GND (emitter)
output (collector)
3
R1
1
Transparent
top view
R2
sym003
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
2 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
3. Ordering
information
Table 4.
Ordering information
Type number
Package
Name
Description
Version
SOT416
SOT346
PD
T
A
113ZE
PD
T
A
113ZK
PD
T
A
113ZM
SC-75
SC-59
plastic surface mounted package; 3 leads
plastic surface mounted package; 3 leads
SC-101 leadless
ultra small plastic package; 3 solder lands;
SOT883
body 1.0
×
0.6
×
0.5 mm
PD
T
A
113ZS
[1]
SC-43A plastic-single-ended
leaded (through hole) package;
SOT54
3 leads
PD
T
A
113ZT
PD
T
A
113ZU
–
plastic surface mounted package; 3 leads
plastic surface mounted package; 3 leads
SOT23
SC-70
SOT323
[1] Also
available in SOT54A and SOT54 variant packages (see
Section 2
and
Section 9
)
4. Marking
Table 5.
Marking codes
Type number
PD
T
A
113ZE
PD
T
A
113ZK
PD
T
A
113ZM
PD
T
A
113ZS
PD
T
A
113ZT
PD
T
A
113ZU
Marking code
[1]
15
27
G3
T
A
113Z
*AM
*16
[1] *
= -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
3 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
5. Limiting
values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
V
I
Parameter
Conditions
open emitter
open base
Min
Max
−
50
−
50
−
5
Unit
V
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage
–
–
–
V
open collector
V
positive
–
–
–
–
+5
V
negative
−
10
−
100
−
100
V
I
O
output current (DC)
peak collector current
total power dissipation
SOT416
mA
mA
I
CM
P
tot
T
amb
≤
25
°
C
[1]
[1]
–
150
250
250
500
250
200
+150
150
+150
mW
mW
mW
mW
mW
mW
°
C
SOT346
–
[2][3]
[1]
SOT883
–
SOT54
–
[1]
SOT23
–
[1]
SOT323
–
T
stg
T
j
storage temperature
junction temperature
ambient temperature
−
65
–
°
C
T
amb
−
65
°
C
[1] Refer
to standard mounting conditions.
[2] Reflow
soldering is the only recommended soldering method.
[3] Refer
to SOT883 standard mounting conditions; FR4 printed-circuit board with 60
µ
m copper strip line.
6. Thermal
characteristics
Table 7.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max Unit
R
th(j-a)
thermal resistance from
junction to ambient
in free air
[1]
[1]
SOT416
SOT346
SOT883
SOT54
–
–
–
–
–
–
–
–
–
–
–
–
833
500
500
250
500
625
K/W
K/W
K/W
K/W
K/W
K/W
[2][3]
[1]
[1]
SOT23
[1]
SOT323
[1] Refer
to standard mounting conditions.
[2] Reflow
soldering is the only recommended soldering method.
[3] Refer
to SOT883 standard mounting conditions; FR4 printed-circuit board with 60
µ
m copper strip line.
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
4 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
7. Characteristics
Table 8.
Characteristics
T
amb
= 25
°
C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
I
CBO
collector-base cut-off
V
CB
=
−
50 V; I
E
= 0 A
–
–
−
100
nA
current
I
CEO
collector-emitter
cut-off current
V
CE
=
−
30 V; I
B
= 0 A
–
–
–
–
−
1
µ
A
µ
A
V
CE
=
−
30 V; I
B
= 0 A;
T
j
=
150
°
C
−
50
I
EBO
emitter-base cut-off
current
V
EB
=
−
5 V; I
C
= 0 A
–
–
−
800
µ
A
h
FE
DC current gain
V
CE
=
−
5 V; I
C
=
−
5 mA
35
–
–
–
–
V
CEsat
collector-emitter
I
C
=
−
10 mA; I
B
=
−
0.5 mA
−
150
mV
saturation voltage
V
I(off)
V
I(on)
R1
off-state input voltage
V
CE
=
−
5 V; I
C
=
−
100
µ
A
on-state input voltage
V
CE
=
−
300 mV; I
C
=
−
20 mA
bias resistor 1 (input)
–
−
0.65
−
0.3
–
V
−
2.5
0.7
8
−
0.95
V
1
1.3
12
2
k
Ω
R2/R1
C
c
bias resistor ratio
10
–
collector capacitance
V
CB
=
−
10 V; I
E
= i
e
= 0 A;
–
pF
f = 1 MHz
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
5 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
006aaa107
006aaa108
3
10
−
1
h
FE
(2) (1)
V
CEsat
(V)
2
10
(3)
−
1
−
10
(1)
(2)
(3)
10
−
2
1
−
10
−
10
−
1
2
2
−
1
−
10
−
10
−
1
−
10
−
10
I
(mA)
I (mA)
C
C
V
CE
=
−
5 V
I
C
/I
B
= 20
(1) T
amb
= 100
°
C
(2) T
amb
= 25
°
C
(3) T
amb
=
−
40
°
C
(1) T
amb
= 100
°
C
(2) T
amb
= 25
°
C
(3) T
amb
=
−
40
°
C
Fig 1.
DC current gain as a function of collector
current; typical values
Fig 2.
Collector-emitter saturation voltage as a
function of collector current; typical values
006aaa109
006aaa110
−
10
−
10
V
V
I(off)
I(on)
(V)
(V)
(1)
(1)
(2)
−
1
−
1
(2)
(3)
(3)
−
1
−
1
−
10
−
10
−
1
2
−
1
−
10
−
1
−
10
−
10
−
10
−
1
−
10
I
(mA)
I (mA)
C
C
V
CE
=
−
0.3 V
V
CE
=
−
5 V
(1) T
amb
=
−
40
°
C
(2) T
amb
= 25
°
C
(3) T
amb
= 100
°
C
(1) T
amb
=
−
40
°
C
(2) T
amb
= 25
°
C
(3) T
amb
= 100
°
C
Fig 3.
On-state input voltage as a function of
collector current; typical values
Fig 4.
Off-state input voltage as a function of
collector current; typical values
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
6 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
8. Package
outline
Plastic surface-mounted package; 3 leads
SOT416
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
1
2
c
e
1
b
p
w
M
B
L
p
e
detail X
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
A
UNIT
b
c
D
E
e
e
H
L
p
Q
v
w
p
1
E
max
0.30
0.15
0.25
0.10
1.8
1.4
0.9
0.7
1.75
1.45
0.45
0.15
0.23
0.13
0.95
0.60
mm
0.1
1
0.5
0.2
0.2
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-04
06-03-16
SOT416
SC-75
Fig 5.
Package outline SOT416 (SC-75)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
7 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic surface-mounted package; 3 leads
SOT346
E
A
D
B
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
L
p
e
1
b
p
w
M
B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
A
p
1
p
1
E
1.3
1.0
0.1
0.013
0.50
0.35
0.26
0.10
3.1
2.7
1.7
1.3
3.0
2.5
0.6
0.2
0.33
0.23
mm
1.9
0.95
0.2
0.2
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
JEITA
SC-59A
04-11-11
06-03-16
SOT346
TO-236
Fig 6.
Package outline SOT346 (SC-59/TO-236)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
8 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm
SOT883
L
L
1
2
b
3
b
e
1
1
e
1
A
A
1
E
D
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
1
UNIT
A
b
b
D
E
e
e
L
L
1
1
1
max.
0.50
0.46
0.20 0.55 0.62 1.02
0.12 0.47 0.55 0.95
0.30 0.30
0.22 0.22
mm
0.03
0.35 0.65
Note
1. Including plating thickness
REFERENCES
JEDEC
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEITA
03-02-05
03-04-03
SOT883
SC-101
Fig 7.
Package outline SOT883 (SC-101)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
9 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
1
UNIT
A
b
b
c
D
d
E
e
e
L
1
1
max.
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
14.5
12.7
mm
2.54
1.27
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-06-28
04-11-16
SOT54
TO-92
SC-43A
Fig 8.
Package outline SOT54 (SC-43A/TO-92)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
10 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic single-ended leaded (through hole) package; 3 leads (wide pitch)
SOT54A
c
E
A
L
d
L
b
2
1
e
1
e
D
2
3
b
1
L
1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
1
UNIT
A
b
b
c
D
d
E
e
e
L
L
2
1
1
max.
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
14.5
12.7
3
2
mm
5.08
2.54
3
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
97-05-13
04-06-28
SOT54A
Fig 9.
Package outline SOT54A
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
11 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
SOT54 variant
c
e
1
L
2
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
L
2
1
UNIT
A
b
b
c
D
d
E
e
e
L
1
1
max
max
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
14.5
12.7
mm
2.54
1.27
2.5
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
04-06-28
05-01-10
SOT54 variant
Fig 10.
Package outline SOT54 variant
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
12 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic surface-mounted package; 3 leads
SOT23
D
B
E
A
X
H
v
M
A
E
3
Q
A
A
1
c
1
2
e
1
b
p
w
M
B
L
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
UNIT
b
c
D
E
e
e
H
L
Q
v
w
A
p
p
1
E
max.
1.1
0.9
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
2.5
2.1
0.45
0.15
0.55
0.45
mm
0.1
1.9
0.95
0.2
0.1
REFERENCES
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
JEDEC
JEITA
04-11-04
06-03-16
SOT23
TO-236AB
Fig 11.
Package outline SOT23 (TO-236AB)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
13 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
Plastic surface-mounted package; 3 leads
SOT323
D
B
E
A
X
H
y
v
M
A
E
3
Q
A
A
1
c
1
2
L
p
e
1
b
p
w
M
B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
max
A
UNIT
b
c
D
E
e
e
H
E
L
Q
v
w
p
p
1
1.1
0.8
0.4
0.3
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.23
0.13
mm
0.1
1.3
0.65
0.2
0.2
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
04-11-04
06-03-16
SOT323
SC-70
Fig 12.
Package outline SOT323 (SC-70)
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
14 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
9. Packing
information
Table 9.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type number
Package
Description
Packing quantity
3000
5000
10000
-135
-135
-315
–
PD
T
A
113ZE
PD
T
A
113ZK
PD
T
A
113ZM
PD
T
A
113ZS
SOT416
SOT346
SOT883
SOT54
4 mm pitch, 8 mm tape and reel
4 mm pitch, 8 mm tape and reel
2 mm pitch, 8 mm tape and reel
bulk, straight leads
-115
–
-115
–
–
–
–
-412
SOT54A
SOT54A
SOT54 variant
SOT23
tape and reel, wide pitch
–
–
-116
-126
–
tape ammopack, wide patch
bulk, delta pinning
–
–
–
-112
PD
T
A
113ZT
PD
T
A
113ZU
4 mm pitch, 8 mm tape and reel
4 mm pitch, 8 mm tape and reel
-215
-115
–
–
-235
-135
SOT323
[1] For
further information and the availability of packing methods, see
Section 12
.
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
15 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
10. Revision history
Table 10.
Revision history
Document ID
Release date
20090902
Data sheet status
Change notice
Supersedes
PD
T
A
113Z_SER_4
Modifications:
Product data sheet
–
PD
T
A
113Z_SER_3
•
This data sheet was changed to reflect the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•
Figure 5 “Package outline SOT416 (SC-75)”
: updated
•
Figure 6 “Package outline SOT346 (SC-59/TO-236)”
: updated
•
Figure 11 “Package outline SOT23 (TO-236AB)”
. updated
•
Figure 12 “Package outline SOT323 (SC-70)”
: updated
PD
T
A
113Z_SER_3
PD
T
A
113ZT_2
20050407
20040518
20040325
Product data sheet
Objective data sheet
Objective data sheet
–
–
–
PD
T
A
113ZT_2
PD
T
A
113ZT_1
–
PD
T
A
113ZT_1
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
16 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
11. Legal information
11.1 Data
sheet status
Document status
[1][2]
Product status
[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
11.2 Definitions
Draft —
The document is a draft version onl
y
.
T
he content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications —
Applications that are described herein for any of these
products are for illustrative purposes onl
y
.
N
XP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values —
Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliabilit
y
.
Short data sheet —
A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale —
NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
11.3 Disclaimers
General —
Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license —
Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes —
NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control —
This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data —
The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Suitability for use —
NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, militar
y
,
a
ircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injur
y
,
d
eath or severe property or environmental
11.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
12. Contact information
PD
T
A
113Z_SER_4
© NXP B.
V
.
2
009. All rights reserved.
Product data sheet
Rev. 04 — 2 September 2009
17 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 k
Ω
, R2 = 10 k
Ω
13. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . .
1
General description. . . . . . . . . . . . . . . . . . . . . .
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Applications .
. . . . . . . . . . . . . . . . . . . . . . . . . .
1
Quick reference data. . . . . . . . . . . . . . . . . . . . .
1
1.1
1.2
1.3
1.4
2
Pinning informatio
n
. . . . . . . . . . . . . . . . . . . . . .
2
Ordering informatio
n
. . . . . . . . . . . . . . . . . . . . .
3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .
4
Thermal characteristics. . . . . . . . . . . . . . . . . . .
4
Characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . .
5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .
7
Packing information. . . . . . . . . . . . . . . . . . . . .
15
Revision histor
y
. . . . . . . . . . . . . . . . . . . . . . . .
1
6
3
4
5
6
7
8
9
10
11
Legal information. . . . . . . . . . . . . . . . . . . . . . .
17
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
17
Definition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
7
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
T
r
ademark
s
. . . . . . . . . . . . . . . . . . . . . . . . . . .
1
7
11.1
11.2
11.3
11.4
12
13
Contact informatio
n
. . . . . . . . . . . . . . . . . . . . .
17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.
V
.
2
009.
All rights reserved.
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 September 2009
Document identifier: PDTA113Z_SER_4
