Nexperia-PHB32N06LT-118
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PHB32N06LT
N-channel TrenchMOS logic level FET
Rev. 02 — 30 November 2009
Product data sheet
1. Product
profile
1.1 General
description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features
and benefits
Suitable for logic level gate drive
sources
1.3 Applications
General purpose switching
Switched-mode power supplies
1.4 Quick
reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage
T
j
≥
25 °C; T
j
≤
175 °C
Min
Typ
Max Unit
V
DS
I
D
–
–
–
–
60
34
V
A
drain current
T
mb
= 25 °C; V
GS
= 5 V;
see
Figure 1
and
3
P
tot
total power
dissipation
T
mb
= 25 °C;
see
Figure 2
–
–
–
97
–
W
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 5 V; I
D
= 20 A;
V
DS
= 44 V; T
j
= 25 °C;
see
Figure 11
8.5
nC
Static characteristics
R
DSon
drain-source
on-state resistance
V
GS
= 4.5 V; I
D
= 20 A;
T
j
= 25 °C
–
–
31.5 43
30 40
m
Ω
m
Ω
V
GS
= 5 V; I
D
= 20 A;
T
j
= 25 °C;
see
Figure 9
and
10
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
2. Pinning
information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
[1]
2
drain
source
3
G
mb
mounting base; connected to
drain
mbb076
S
2
1
3
SOT404 (D2PAK)
[1] It
is not possible to make a connection to pin 2.
3. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PHB32N06LT
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
SOT404
4. Limiting
values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 k
Ω
–
60
V
V
DGR
V
GS
–
60
V
-15
–
15
V
I
D
V
GS
= 5 V; T
mb
= 100 °C; see
Figure 1
24
A
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1
and
3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
–
34
A
I
DM
P
tot
T
stg
T
j
peak drain current
–
136
97
A
total power dissipation
T
mb
= 25 °C; see
Figure 2
storage temperature
–
W
°C
°C
V
-55
-55
-20
175
175
20
junction temperature
V
GSM
peak gate-source
voltage
pulsed; t
p
≤
50 µs
Source-drain diode
I
S
source current
peak source current
T
mb
= 25 °C
–
–
34
A
A
I
SM
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
136
Avalanche ruggedness
E
DS(AL)S
non-repetitive
V
GS
= 5 V; T
j(init)
= 25 °C; I
D
= 20 A; V
sup
≤
25 V;
–
100
mJ
drain-source avalanche
unclamped; t
p
= 0.11 ms; R
GS
= 50
Ω
energy
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
2 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
03aa24
03aa16
120
120
I
P
der
der
(%)
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
T
mb
(
°
C)
T
mb
(
°
C)
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03ah48
3
10
I
D
(A)
t
p
= 10
μ
s
100
μ
s
2
R
DSon
= V
/I
DS D
10
10
DC
1 ms
10 ms
1
2
1
10
10
V
DS
(V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
3 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
5. Characteristics
Table 5.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source
breakdown voltage
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
55
60
–
–
–
–
–
V
V
V
–
V
GS(th)
gate-source threshold
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
2.3
voltage
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 8
1
1.5
–
2
–
V
V
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
see
Figure 8
0.5
I
DSS
drain leakage current
gate leakage current
V
DS
= 60 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 60 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 20 A; T
j
= 25 °C
–
–
–
–
–
–
0.05
10
µA
µA
nA
–
500
100
100
43
I
GSS
2
2
nA
R
DSon
drain-source on-state
resistance
31.5
–
m
Ω
m
Ω
V
GS
= 5 V; I
D
= 20 A; T
j
= 175 °C;
see
Figure 9
and
10
84
V
GS
= 10 V; I
D
= 20 A; T
j
= 25 °C
–
–
26
30
37
40
m
Ω
m
Ω
V
GS
= 5 V; I
D
= 20 A; T
j
= 25 °C;
see
Figure 9
and
10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
I
D
= 20 A; V
DS
= 44 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 11
–
–
–
–
–
–
17
–
nC
nC
nC
pF
pF
pF
3
–
8.5
920
160
100
–
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
1280
200
155
C
oss
C
rss
reverse transfer
capacitance
t
d(on)
t
r
t
d(off)
t
f
turn-on delay time
rise time
V
DS
= 30 V; R
L
= 1.2
Ω
; V
GS
= 5 V;
R
G(ext)
= 10
Ω
; T
j
= 25 °C
–
–
–
–
14
–
–
–
–
ns
ns
ns
ns
120
45
turn-off delay time
fall time
55
Source-drain diode
V
SD
source-drain voltage
I
S
= 25 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 7
–
1
1.2
V
t
rr
reverse recovery time
recovered charge
I
S
= 20 A; dI
S
/dt = -100 A/µs; V
GS
= -10 V;
V
DS
= 30 V; T
j
= 25 °C
–
–
36
70
–
–
ns
Q
r
nC
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
4 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
03ah49
03ah51
40
40
T =
25
°
C
j
V
DS
> I
×
R
D
DSon
I
I
D
(A)
D
10 V
5 V
4 V
3.5 V
(A)
30
30
3 V
20
10
0
20
10
0
V
= 2.5 V
GS
175
°
C
T =
25
°
C
j
0
0.5
1.0
1.5
2.0
0
1
2
3
4
V
(V)
V
GS
(V)
DS
Fig 4.
Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 5.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
03aa36
03ah52
10
-1
40
I
D
(A)
10
-2
10
-3
V
GS
= 0 V
I
S
(A)
30
min
typ
max
20
10
0
10
-4
10
-5
10
-6
175
°
C
T =
25
°
C
j
0
1
2
3
0
0.3
0.6
0.9
1.2
V
GS
(V)
V
(V)
SD
Fig 7.
Source current as a function of source-drain
voltage; typical values
Fig 6.
Sub-threshold drain current as a function of
gate-source voltage
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
5 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
03aa33
03ah50
2.5
V
GS(th)
(V)
0.05
T =
25
°
C
j
V
GS
= 3.5 V
R
DSon
(
Ω
)
2
1.5
1
max
0.04
0.03
0.02
4 V
5 V
typ
min
10 V
0.5
0
-60
0
60
120
180
0
10
20
30
40
T ( C)
°
j
I (A)
D
Fig 9.
Drain-source on-state resistance as a function
of drain current; typical values
Fig 8.
Gate-source threshold voltage as a function of
junction temperature
03af18
03ah54
10
2
I
= 20 A
D
V
(V)
GS
a
T =
25
°
C
j
8
6
4
2
0
1.5
V
DD
= 14 V
V
= 44 V
DD
1
0.5
0
-60
0
60
120
180
0
10
20
30
40
T
j
(
°
C)
Q
G
(nC)
Fig 10.
Normalized drain-source on-state resistance
factor as a function of junction temperature
Fig 11.
Gate-source voltage as a function of turn-on
gate charge; typical values
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
6 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
03ah53
4
3
2
10
C
(pF)
10
C
iss
C
C
oss
10
rss
10
10
−
1
2
1
10
10
V
DS
(V)
Fig 12.
Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
6. Thermal
characteristics
Table 6.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from
see
Figure 13
–
–
1.55
K/W
junction to mounting
base
R
th(j-a)
thermal resistance from
mounted on printed-circuit board;
–
50
–
K/W
junction to ambient
minimum footprint
03ah47
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
−
1
−
2
−
3
10
10
10
0.05
0.02
t
p
P
δ
=
T
single pulse
t
t
p
T
−
5
−
4
−
3
−
2
−
1
10
10
10
10
10
1
t
(s)
p
Fig 13.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
7 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
7. Package
outline
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A
A
E
1
mounting
base
D
1
D
H
D
2
L
p
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
D
E
A
A
b
UNIT
c
D
e
L
H
Q
1
1
p
D
max.
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
1.60
1.20
10.30
9.70
2.90 15.80 2.60
2.10 14.80 2.20
mm
11
2.54
REFERENCES
JEDEC JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
05-02-11
06-03-16
SOT404
Fig 14.
Package outline SOT404 (D2PAK)
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
8 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
8. Revision
history
Table 7.
Revision history
Document ID
PHB32N06LT_2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20091130
Product data sheet
–
PHP_PHB_32N06LT-01
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
PHP_PHB_32N06LT-01
(9397 750 09024)
20011106
Product data
–
–
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
9 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
9. Legal
information
9.1 Data
sheet status
Document status
[1][2]
Product status
[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
Applications
— Applications that are described herein for any of these
9.2 Definitions
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet
— A short data sheet is an extract from a full data sheet with
the same product type number(s) and title. A short data sheet is intended for
quick reference only and should not be relied upon to contain detailed and full
information. For detailed and full information see the relevant full data sheet,
which is available on request via the local Nexperia sales office.
In case of any inconsistency or conflict with the short data sheet, the full data
sheet shall prevail.
Terms and conditions of sale
— Nexperia products are sold
subject to the general terms and conditions of commercial sale, as published
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by Nexperia. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3 Disclaimers
General
— Information in this document is believed to be accurate and
reliable. However, Nexperia does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license
— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes
— Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control
— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use
— Nexperia products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia accepts no liability for inclusion and/or use of
Nexperia products in such equipment or applications and
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
therefore such inclusion and/or use is at the customer’s own risk.
10. Contact information
PHB32N06LT_2
Product data sheet
Rev. 02 — 30 November 2009
10 of 11
©
Nexperia B.V. 2017. All rights reserved
PHB32N06LT
Nexperia
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description
. . . . . . . . . . . . . . . . . . . . . .1
Features and benefit
s
. . . . . . . . . . . . . . . . . . . . .1
Applications .
. . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data
. . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning informatio
n
. . . . . . . . . . . . . . . . . . . . . . .2
Ordering informatio
n
. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . . .4
Thermal characteristics
. . . . . . . . . . . . . . . . . . .7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .8
Revision histor
y
. . . . . . . . . . . . . . . . . . . . . . . . . .9
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .10
Definition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .10
9.1
9.2
9.3
9.4
10
Contact informatio
n
. . . . . . . . . . . . . . . . . . . . . .10
©
Nexperia B.V. 2017. All rights reserved
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
30 November 2009
