Nexperia-PMZ130UNE315
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Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia
. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
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Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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– © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
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Should be replaced with:
–
© Nexperia B.V. (year). All rights reserved
.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
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Team Nexperia
PSMN003-30P
N-channel TrenchMOS intermediate level FET
Rev. 02 — 25 February 2010
Product data sheet
1. Product
profile
1.1 General
description
SiliconMAX intermediate level N-channel enhancement mode Field-Effect Transistor
(FET) in a plastic package using TrenchMOS technology. This product is designed and
qualified for use in computing, communications, consumer and industrial applications
only.
1.2 Features
and benefits
Low conduction losses due to low
Suitable for high frequency
applications due to fast switching
characteristics
on-state resistance
1.3 Applications
High frequency computer motherboard
OR-ing applications
DC-to-DC convertors
1.4 Quick
reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
drain-source voltage
T
j
≥
25 °C; T
j
≤
175 °C
Min
Typ
Max Unit
V
DS
I
D
–
–
–
–
30
75
V
A
drain current
T
mb
= 25 °C; V
GS
= 10 V;
P
tot
total power
dissipation
–
–
–
230
–
W
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 10 V; I
D
= 75 A;
V
DS
= 15 V; T
j
= 25 °C;
45
nC
Static characteristics
R
DSon
drain-source
on-state resistance
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
–
–
3.3
2.4
4
m
Ω
m
Ω
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
2.8
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
2. Pinning
information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
2
drain
source
3
G
mb
mounting base; connected to
drain
mbb076
S
1
2 3
SOT78 (TO-220AB)
3. Ordering
information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN003-30P
TO-220AB
plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead
SOT78
TO-220AB
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
2 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
4. Limiting
values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
Parameter
Conditions
Min
Max
30
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 k
Ω
–
V
DGR
V
GS
–
30
V
-20
–
20
V
I
D
75
A
–
75
A
I
DM
P
tot
T
stg
T
j
peak drain current
–
400
230
175
175
25
A
storage temperature
–
W
°C
°C
V
-55
-55
-25
junction temperature
V
GSM
peak gate-source
voltage
pulsed; t
p
≤
50 µs;
δ
= 25 %; T
j
≤
150 °C
Source-drain diode
I
S
source current
peak source current
T
mb
= 25 °C
–
–
75
A
A
I
SM
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
400
Avalanche ruggedness
E
DS(AL)S
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 75 A; V
sup
= 15 V;
–
–
500
75
mJ
A
drain-source avalanche
unclamped; t
p
= 0.1 ms; R
GS
= 50
Ω
energy
I
AS
non-repetitive
V
sup
= 15 V; V
GS
= 10 V; T
j(init)
= 25 °C;
avalanche current
R
GS
= 50
Ω
; unclamped
03aa16
03af36
120
120
I
der
(%)
100
P
(%)
der
80
80
60
40
20
0
40
0
0
50
100
150
200
0
30
60
90
120
150
T
180
(
°
C)
T
mb
(
°
C)
mb
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
PSMN003-30P_2
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© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
3 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
03af49
3
10
R
DSon
= V
/I
DS
D
t
= 10
μ
s
p
I
D
(A)
100 µs
1 ms
2
10
10 ms
100 ms
DC
t
p
P
δ
=
10
T
t
t
p
T
1
2
1
10
10
V
DS
(V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
4 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
5. Thermal
characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
base
–
–
0.65
K/W
R
th(j-a)
thermal resistance from junction to ambient
vertical in still air
–
60
–
K/W
03af48
1
δ
= 0.5
Z
th(j-mb)
(K/W)
0.2
−
1
10
10
10
0.1
0.05
0.02
t
p
P
−
2
−
3
δ
=
T
single pulse
t
t
p
T
1
−
6
−
5
−
4
−
3
−
2
−
1
10
10
10
10
10
10
10
t
(s)
p
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
5 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V
(BR)DSS
drain-source
breakdown voltage
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
27
30
1
–
–
V
–
–
V
V
GS(th)
2
3
V
voltage
0.4
–
–
–
V
–
3.4
500
1
V
I
DSS
drain leakage current
gate leakage current
V
DS
= 30 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
–
–
µA
µA
nA
nA
m
Ω
–
0.02
10
10
4.32
I
GSS
–
100
100
5
–
R
DSon
drain-source on-state
resistance
–
–
–
3.3
2.4
4
m
Ω
m
Ω
2.8
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
I
D
= 75 A; V
DS
= 15 V; V
GS
= 10 V; T
j
= 25 °C;
–
–
–
–
–
–
170
44
–
–
–
–
–
–
nC
nC
nC
pF
pF
pF
45
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz; T
j
= 25 °C;
9200
1930
1300
C
oss
C
rss
reverse transfer
capacitance
t
d(on)
t
r
t
d(off)
t
f
turn-on delay time
rise time
V
DS
= 15 V; R
L
= 1.25
Ω
; V
GS
= 10 V;
R
G(ext)
= 6
Ω
; T
j
= 25 °C
–
–
–
–
33
–
–
–
–
ns
ns
ns
ns
66
turn-off delay time
fall time
210
115
Source-drain diode
V
SD
source-drain voltage
–
0.85
1.2
V
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
6 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
03af50
03af52
400
100
I
D
I
D
V
= 10 V
7 V
5.2 V
V
> I
x R
D DSon
T =
25
°
C
(A)
GS
DS
j
5 V
(A)
350
300
250
200
150
100
50
15 V
20 V
4.8 V
80
4.6 V
4.4 V
175
°
C
60
40
T =
25
°
C
j
4.2 V
4 V
3.8 V
20
0
3.6 V
3.4 V
0
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
V
(V)
GS
V
(V)
DS
Fig 6.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 5.
Output characteristics: drain current as a
function of drain-source voltage; typical values
03af66
03af65
1
4
I
D
V
GS(th)
(V)
(A)
10
-1
3
10
-2
max
typ
max
min
10
-3
10
-4
10
-5
10
-6
2
typ
1
min
0
-60
0
1
2
3
4
20
100
180
V
GS
(V)
T
j
(
°
C)
Fig 7.
Sub-threshold drain current as a function of
gate-source voltage
Fig 8.
Gate-source threshold voltage as a function of
junction temperature
PSMN003-30P_2
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© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
7 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
03af18
03af51
2
0.006
R
3.8 V
4 V
4.2 V
4.4 V
4.6 V
4.8 V
DSon
(
Ω
)
a
0.005
0.004
0.003
0.002
0.001
0
1.5
5 V
5.2 V
1
0.5
0
6 V
10 V
15 V
V
= 20 V
GS
T =
25
°
C
j
-60
0
60
120
180
0
100
200
300
400
500
T
j
(
°
C)
I
(A)
D
Fig 9.
Drain-source on-state resistance as a function
of drain current; typical values
Fig 10.
Normalized drain-source on-state resistance
factor as a function of junction temperature
03af56
03af55
5
12
10
V
GS
I
= 75 A
D
C
(V)
10
8
(pF)
V
= 15 V
DD
4
10
C
iss
T =
25
°
C
j
6
C
oss
3
4
10
C
rss
2
2
10
0
0
50
100
150
200
−
1
2
10
1
10
10
V
(V)
Q
(nC)
DS
G
Fig 11.
Gate-source voltage as a function of gate
charge; typical values
Fig 12.
Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
8 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
03af54
100
I
S
V
= 0 V
GS
(A)
80
175
°
C
60
40
20
0
T =
25
°
C
j
0.0
0.5
1.0
V
1.5
(V)
SD
Fig 13.
Source current as a function of source-drain voltage; typical values
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
9 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
7. Package
outline
Plastic single-ended package; heatsink mounted; 1 mounting hole;
3-lead TO-220AB
SOT78
E
p
A
A
1
q
mounting
D
1
base
D
(1)
(1)
L
1
L
2
Q
(2)
b
1
L
(3
×
)
(2)
b
2
(2
×
)
1
2
3
b(3
×
)
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
L
2
(2)
(2)
(1)
1
UNIT
mm
A
A
b
b
b
c
D
D
1
E
e
L
L
p
q
Q
1
1
2
max.
4.7
4.1
1.40
1.25
0.9
0.6
1.6
1.0
1.3
1.0
0.7
0.4
16.0
15.2
6.6
5.9
10.3
9.7
15.0 3.30
12.8 2.79
3.8
3.5
3.0
2.7
2.6
2.2
2.54
3.0
Notes
1. Lead shoulder designs may vary.
2. Dimension includes excess dambar.
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
08-04-23
08-06-13
SOT78
SC-46
3-lead TO-220AB
Fig 14.
Package outline SOT78 (TO-220AB)
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
10 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
8. Revision
history
Table 7.
Revision history
Document ID
PSMN003-30P_2
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20100225
Product data sheet
–
PSMN003-30P_1
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
PSMN003-30P_1
20011023
Product data
–
–
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
11 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
9. Legal
information
9.1 Data
sheet status
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
Suitability for use
— NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft
— The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications
— Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet
— A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification
— The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Quick reference data
— The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
9.3 Disclaimers
Limiting values
— Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability
— Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including – without limitation – lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale
— NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
T
e
rms and conditions of commercial sale
of NXP Semiconductors.
No offer to sell or license
— Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes
— NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
12 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
Export control
— This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use of
the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products
— Unless the data sheet of an NXP
Semiconductors product expressly states that the product is automotive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS
— is a trademark of NXP B.V.
10. Contact information
PSMN003-30P_2
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2010. All rights reserved.
Product data sheet
Rev. 02 — 25 February 2010
13 of 14
PSMN003-30P
NXP Semiconductors
N-channel TrenchMOS intermediate level FET
11. Contents
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Date of release: 25 February 2010
Document identifier: PSMN003-30P_2
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