Nexperia-PUMD13-115
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Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia
. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
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In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
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(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
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– © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
–
© Nexperia B.V. (year). All rights reserved
.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
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Team Nexperia
PEMD13; PUMD13
NPN/PNP resistor-equipped transistors;
R1 = 4.7 k
, R2 = 47 k
Rev. 3 — 7 December 2011
Product data sheet
1. Product
profile
1.1 General
description
NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted
Device (SMD) plastic packages.
Table 1.
Product overview
Type number
Package
NXP
PNP/PNP
complement
NPN/NPN
complement
Package
configuration
JEITA
PEMD13
SOT666
–
PEMB13
PUMB13
PEMH13
PUMH13
ultra small and flat
lead
PUMD13
SOT363
SC-88
very small
1.2 Features
and benefits
100 mA output current capability
Built-in bias resistors
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified
Simplifies circuit design
1.3 Applications
Low current peripheral driver
Control of IC inputs
Replaces general-purpose transistors in digital applications
1.4 Quick
reference data
Table 2.
Symbol
Quick reference data
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor; for the PNP transistor (TR2) with negative polarity
V
CEO
I
O
collector-emitter voltage
output current
open base
–
–
50
V
–
–
100
6.1
12
mA
k
R1
bias resistor 1 (input)
bias resistor ratio
3.3
8
4.7
10
R2/R1
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
2. Pinning
information
Table 3.
Pinning
Pin
1
Description
Simplified outline
Graphic symbol
GND (emitter) TR1
input (base) TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
output (collector) TR1
6
5
4
6
5
4
2
3
R1
R2
4
TR2
5
TR1
1
2
3
6
R2
R1
001aab555
1
2
3
006aaa143
3. Ordering
information
Table 4.
Ordering information
Type number
Package
Name
Description
Version
SOT666
SOT363
PEMD13
PUMD13
–
plastic surface-mounted package; 6 leads
plastic surface-mounted package; 6 leads
SC-88
4. Marking
Table 5.
Marking codes
Type number
PEMD13
Marking code
[1]
Z1
PUMD13
3*1
[1] *
= placeholder for manufacturing site code
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
2 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
5. Limiting
values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions Min
Per transistor; for the PNP transistor (TR2) with negative polarity
Max
Unit
V
CBO
V
CEO
V
EBO
V
I
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage TR1
positive
open emitter
open base
–
–
–
50
50
5
V
V
V
open collector
–
–
+30
V
V
negative
5
input voltage TR2
positive
–
–
–
–
+5
V
negative
30
100
100
V
I
O
output current
mA
mA
I
CM
peak collector current
single pulse;
t
p
1 ms
P
tot
total power dissipation
PEMD13 (SOT666)
PUMD13 (SOT363)
T
amb
25
C
[1][2]
[1]
–
–
200
200
mW
mW
Per device
P
tot
total power dissipation
PEMD13 (SOT666)
PUMD13 (SOT363)
junction temperature
ambient temperature
storage temperature
T
amb
25
C
[1][2]
[1]
–
300
mW
mW
C
–
300
T
j
–
150
T
amb
T
stg
65
65
+150
+150
C
C
[1] Device
mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow
soldering is the only recommended soldering method.
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
3 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
006aac749
400
P
tot
(mW)
300
200
100
0
-75
-25
25
75
125
175
(°C)
T
amb
FR4 PCB, standard footprint
Fig 1.
Per device: Power derating curve for SOT363 (SC-88) and SOT666
6. Thermal
characteristics
Table 7.
Symbol
Per transistor
Thermal characteristics
Parameter
Conditions
Min
Typ
Max Unit
R
th(j-a)
thermal resistance from
in free air
junction to ambient
PEMD13 (SOT666)
PUMD13 (SOT363)
[1][2]
[1]
–
–
–
–
625
625
K/W
K/W
Per device
R
th(j-a)
thermal resistance from
junction to ambient
in free air
[1][2]
[1]
PEMD13 (SOT666)
PUMD13 (SOT363)
–
–
–
–
417
417
K/W
K/W
[1] Device
mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow
soldering is the only recommended soldering method.
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
4 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
006aac751
3
10
duty cycle = 1
Z
th(j-a)
0.75
0.33
(K/W)
0.5
0.2
2
10
0.1
0.02
0
0.05
0.01
10
1
10
-5
-4
-3
-2
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, standard footprint
Fig 2.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for
PEMD13 (SOT666); typical values
006aac750
3
10
duty cycle = 1
Z
th(j-a)
0.75
0.33
(K/W)
0.5
0.2
2
10
0.1
0.05
0.01
0.02
0
10
1
10
-5
-4
-3
-2
-1
2
3
10
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, standard footprint
Fig 3.
Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration for
PUMD13 (SOT363); typical values
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
5 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
7. Characteristics
Table 8.
Characteristics
T
amb
= 25
C unless otherwise specified.
Symbol Parameter
Conditions
Per transistor; for the PNP transistor (TR2) with negative polarity
Min
Typ
Max
Unit
I
CBO
collector-base cut-off
current
V
CB
= 50 V; I
E
= 0 A
–
–
100
nA
I
CEO
collector-emitter cut-off
V
CE
= 30 V; I
B
= 0 A
–
–
–
–
1
5
A
A
current
V
CE
= 30 V; I
B
= 0 A;
T
j
= 150
C
I
EBO
emitter-base cut-off
current
V
EB
= 5 V; I
C
= 0 A
–
–
170
A
h
FE
DC current gain
V
CE
= 5 V; I
C
= 10 mA
I
C
= 5 mA; I
B
= 0.25 mA
100
–
–
–
–
V
CEsat
collector-emitter
100
mV
saturation voltage
V
I(off)
V
I(on)
R1
off-state input voltage
on-state input voltage
bias resistor 1 (input)
bias resistor ratio
V
CE
= 5 V; I
C
= 100
A
–
0.6
0.9
4.7
10
0.5
–
V
V
CE
= 0.3 V; I
C
= 5 mA
1.3
3.3
8
V
6.1
12
k
R2/R1
C
c
collector capacitance
V
CB
= 10 V; I
E
= i
e
= 0 A;
f = 1 MHz
TR1 (NPN)
TR2 (PNP)
–
–
–
–
2.5
3
pF
pF
[1]
f
T
transition frequency
V
CE
= 5 V; I
C
= 10 mA;
f = 100 MHz
TR1 (NPN)
TR2 (PNP)
–
–
230
180
–
–
MHz
MHz
[1] Characteristics
of built-in transistor
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
6 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
006aac819
006aac820
3
10
1
h
FE
(1)
V
CEsat
(2)
(V)
(3)
2
10
-1
(1)
10
(2)
(3)
10
-2
1
10
10
-1
2
-1
2
1
10
10
10
1
10
10
I
C
(mA)
I (mA)
C
V
CE
= 5 V
amb
= 100
C
I
C
/I
B
= 20
(1) T
amb
= 100
C
(1)
T
(2) T
amb
= 25
C
(3) T
amb
=
40
C
(2) T
amb
= 25
C
(3) T
amb
=
40
C
Fig 4.
TR1 (NPN): DC current gain as a function of
collector current; typical values
Fig 5.
TR1 (NPN): Collector-emitter saturation
voltage as a function of collector current;
typical values
006aac821
006aac822
10
10
V
V
I(off)
I(on)
(V)
(V)
(1)
1
1
(1)
(2)
(2)
(3)
(3)
-1
-1
10
10
-1
2
-1
10
1
10
10
10
1
10
I
C
(mA)
I (mA)
C
V
CE
= 0.3 V
V
CE
= 5 V
(1) T
amb
=
40
C
(2) T
amb
= 25
C
(1) T
amb
=
40
C
(2) T
amb
= 25
C
(3)
T
amb
= 100
C
(3) T
amb
= 100
C
Fig 6.
TR1 (NPN): On-state input voltage as a
function of collector current; typical values
Fig 7.
TR1 (NPN): Off-state input voltage as a
function of collector current; typical values
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
7 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
006aac823
006aac757
3
3
10
C
c
(pF)
f
T
(MHz)
2
1
0
2
10
10
10
-1
2
0
10
20
30
40
V
50
(V)
1
10
10
I (mA)
C
CB
f = 1 MHz; T
amb
= 25
C
V
CE
= 5 V; T
amb
= 25
C
Fig 8.
TR1 (NPN): Collector capacitance as a function
of collector-base voltage; typical values
Fig 9.
TR1 (NPN): Transition frequency as a function
of collector current; typical values of built-in
transistor
006aac824
006aac825
3
10
-1
h
FE
(1)
V
CEsat
(V)
(2)
(3)
2
10
-1
-10
(1)
10
(2)
(3)
-2
1
-10
-10
-1
2
-1
2
-1
-10
-10
-10
-1
-10
-10
I
C
(mA)
I (mA)
C
V
CE
=
5 V
I
C
/I
B
= 20
(1) T
amb
= 100
C
(2) T
amb
= 25
C
(1) T
amb
= 100
C
(2) T
amb
= 25
C
(3)
T
amb
=
40
C
(3) T
amb
=
40
C
Fig 10.
TR2 (PNP): DC current gain as a function of
collector current; typical values
Fig 11.
TR2 (PNP): Collector-emitter saturation
voltage as a function of collector current;
typical values
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
8 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
006aac826
006aac827
-10
-10
V
V
I(off)
I(on)
(V)
(V)
(1)
(1)
-1
-1
(2)
(2)
(3)
(3)
-1
-1
-10
-10
-1
2
-1
-10
-1
-10
-10
-10
-1
-10
I
C
(mA)
I (mA)
C
V
CE
=
0.3 V
amb
=
40
C
V
CE
=
5 V
amb
=
40
C
(1)
T
(1) T
(2) T
amb
= 25
C
(3) T
amb
= 100
C
(2) T
amb
= 25
C
(3) T
amb
= 100
C
Fig 12.
TR2 (PNP): On-state input voltage as a
Fig 13.
TR2 (PNP): Off-state input voltage as a
function of collector current; typical values
function of collector current; typical values
006aac828
006aac763
3
8
6
4
2
0
10
C
c
(pF)
f
T
(MHz)
2
10
10
-10
-1
2
0
-10
-20
-30
-40
-50
(V)
-1
-10
-10
V
I (mA)
C
CB
f = 1 MHz; T
amb
= 25
C
V
CE
=
5 V; T
amb
= 25
C
Fig 14.
TR2 (PNP): Collector capacitance as a function
of collector-base voltage; typical values
Fig 15.
TR2 (PNP): Transition frequency as a function
of collector current; typical values of built-in
transistor
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
9 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
8. Test
information
8.1 Quality
information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard
Q101 – Stress test qualification for discrete semiconductors
, and is
suitable for use in automotive applications.
9. Package
outline
2.2
1.8
1.1
0.8
1.7
1.5
0.6
0.5
0.45
0.15
6
5
4
6
5
4
0.3
0.1
2.2 1.35
2.0 1.15
1.7 1.3
1.5 1.1
pin 1
index
pin 1 index
1
2
3
1
2
3
0.25
0.10
0.3
0.2
0.18
0.08
0.27
0.17
0.65
0.5
1.3
1
Dimensions in mm
04-11-08
Dimensions in mm
06-03-16
Fig 16.
Package outline PEMD13 (SOT666)
Fig 17.
Package outline PUMD13 (SOT363)
10. Packing information
Table 9.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type
number
Package Description
Packing quantity
3000 4000 8000 10000
PEMD13 SOT666
2 mm pitch, 8 mm tape and reel
4 mm pitch, 8 mm tape and reel
–
–
-315
–
–
-115
–
–
–
–
[2]
[3]
PUMD13 SOT363 4
mm pitch, 8 mm tape and reel; T1
4 mm pitch, 8 mm tape and reel; T2
-115
-125
–
–
-135
-165
[1] For
further information and the availability of packing methods, see
Section 14
.
[2] T1:
normal taping
[3] T2:
reverse taping
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
10 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
11. Soldering
2.75
2.45
2.1
1.6
solder lands
0.4
(6
×
)
0.3
(2
×
)
0.25
(2
×
)
placement area
0.538
0.55
1.075
1.7
2
(2
×
)
solder paste
occupied area
0.325 0.375
(4
×
) (4
×
)
Dimensions in mm
1.7
0.45
0.6
(4
×
)
(2
×
)
0.5
0.65
(4
×
)
(2
×
)
sot666_fr
Reflow soldering is the only recommended soldering method.
Fig 18.
Reflow soldering footprint PEMD13 (SOT666)
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
11 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
2.65
solder lands
0.4 (2
×
)
1.5
2.35
0.6
(4
×
)
0.5
(4
×
)
solder resist
solder paste
0.5
(4
×
)
0.6
(2
×
)
occupied area
0.6
(4
×
)
Dimensions in mm
1.8
sot363_fr
Fig 19.
Reflow soldering footprint PUMD13 (SOT363)
1.5
solder lands
solder resist
occupied area
2.5
0.3
4.5
1.5
Dimensions in mm
preferred transport
direction during soldering
1.3
1.3
2.45
5.3
sot363_fw
Fig 20.
Wave soldering footprint PUMD13 (SOT363)
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
12 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
12. Revision history
Table 10.
Revision history
Document ID
Release date
20111207
Data sheet status
Change notice
Supersedes
PEMD13_PUMD13 v.3
Modifications:
Product data sheet
–
PEMD13_PUMD13 v.2
•
The format of this document has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
•
Section 1 “Product profile”
: updated
•
Section 4 “Marking”
: updated
•
Figure 1
to
15
: added
•
Section 5 “Limiting values”
: updated
•
Section 6 “Thermal characteristics”
: updated
•
T
a
ble 8 “Characteristics”
: V
i(on)
redefined to V
I(on)
on-state input voltage, V
i(off)
redefined to
V
I(off)
off-state input voltage, I
CEO
updated, f
T
added
•
Section 8 “
T
e
st information”
: added
•
Section 9 “Package outline”
: superseded by minimized package outline drawings
•
Section 10 “Packing information”
: added
•
Section 11 “Soldering”
: added
•
Section 13 “Legal information”
: updated
PEMD13_PUMD13 v.2
20031008
Product data sheet
–
PEMD13 v.1
PUMD13 v.1
PEMD13 v.1
PUMD13 v.1
20010911
20010227
Preliminary specification
Product specification
–
–
–
–
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
13 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
13. Legal information
13.1 Data
sheet status
Document status
[1][2]
Product status
[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet
Qualification
Product [short] data sheet
Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
Suitability for use —
NXP Semiconductors products are not designed,
13.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft —
The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet —
A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications —
Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification —
The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
13.3 Disclaimers
Limited warranty and liability —
Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values —
Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including – without limitation – lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale —
NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the
T
e
rms and conditions of commercial sale
of NXP Semiconductors.
Right to make changes —
NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license —
Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
14 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
Export control —
This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Quick reference data —
The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
14. Contact information
PEMD13_PUMD13
All information provided in this document is subject to legal disclaimers.
© NXP B.
V
. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 December 2011
15 of 16
PEMD13; PUMD13
NXP Semiconductors
NPN/PNP resistor-equipped transistors; R1 = 4.7 k
, R2 = 47 k
15. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . .
1
General description
. . . . . . . . . . . . . . . . . . . . .
1
Features and benefit
s
. . . . . . . . . . . . . . . . . . . .
1
Applications .
. . . . . . . . . . . . . . . . . . . . . . . . . .
1
Quick reference data
. . . . . . . . . . . . . . . . . . . .
1
1.1
1.2
1.3
1.4
2
Pinning informatio
n
. . . . . . . . . . . . . . . . . . . . . .
2
Ordering informatio
n
. . . . . . . . . . . . . . . . . . . . .
2
Markin
g
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .
3
Thermal characteristics
. . . . . . . . . . . . . . . . . .
4
Characteristic
s
. . . . . . . . . . . . . . . . . . . . . . . . . .
6
Test informatio
n
. . . . . . . . . . . . . . . . . . . . . . . .
1
0
Quality information . . . . . . . . . . . . . . . . . . . . .
10
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
10
Packing information
. . . . . . . . . . . . . . . . . . . .
10
Soldering .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Revision histor
y
. . . . . . . . . . . . . . . . . . . . . . . .
1
3
3
4
5
6
7
8
8.1
9
10
11
12
13
Legal information. . . . . . . . . . . . . . . . . . . . . . .
14
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
14
Definition
s
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4
Disclaimer
s
. . . . . . . . . . . . . . . . . . . . . . . . . . .
1
4
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
15
13.1
13.2
13.3
13.4
14
15
Contact informatio
n
. . . . . . . . . . . . . . . . . . . . .
15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V.
2011.
All rights reserved.
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 December 2011
Document identifier: PEMD13_PUMD13
