NXP-Semicon-A2I20D020NR1
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Document Number: A2I20D020N
Rev. 1, 05/2017
NXP Semiconductors
T
e
chnical Data
RF LDMOS Wideband Integrated
Power Amplifiers
A2I20D020NR1
A2I20D020GNR1
The A2I20D020N wideband integrated circuit is designed with on
–
–
chip
matching that makes it usable from 1400 to 2200 MHz. This multi
–
–
stage
structure is rated for 20 to 32 V operation and covers all typical cellular base
station modulation formats.
1400–2200 MHz, 2.5 W AVG., 28 V
AIRFAST RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIERS
1800–2200 MHz
Typical Single
–
–
Carrier W
–
–
CDMA Characterization Performance:
DD
= 28 Vdc,
I
DQ1(A+B)
= 32 mA, I
DQ2(A+B)
= 110 mA, P
out
= 2.5 W Avg.,
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCD
F
.
(1)
V
G
PAE
(%)
ACPR
(dBc)
ps
Frequency
1800 MHz
1900 MHz
2000 MHz
2100 MHz
2200 MHz
(dB)
31.0
31.0
31.1
31.4
32.0
TO
–
-270WB
–
-17
PLASTIC
A2I20D020NR1
19.7
21.7
22.1
21.1
19.6
–44.3
–45.0
–45.2
–45.2
–44.8
1. All
data measured in fixture with device soldered to heatsink.
TO
–
-270WBG
–
-17
PLASTIC
A2I20D020GNR1
Features
Extremely wide RF bandwidth
RF decoupled drain pins reduce overall board space
On
–
–
chip matching (50 ohm input, DC blocked)
Integrated quiescent current temperature compensation with
enable/disable function
(2)
2. Refer
to AN1977,
Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
and to AN1987,
Quiescent Current Control
for the RF Integrated Circuit Device Family
. Go to
http://www.nxp.com/R
F
. Select Documentation/Application Notes
–
–
A
N1977 or AN1987.
2016–2017 NXP B.
V
.
V
DS1A
VBW
A
17
16
(2)
V
1
2
VBW
DS1A
GS2A
A
V
V
RF
RF /V
out1 DS2A
inA
3
4
GS1A
RF
RF /V
out1 DS2A
inA
N.C.
5
GND
GND
N.C.
6
V
V
GS1A
GS2A
Quiescent Current
Temperature Compensation
GND
15
14
7
(1)
(1)
8
RF
9
inB
V
V
RF /V
out2 DS2B
GS1B
GS2B
Quiescent Current
Temperature Compensation
10
11
12
V
GS1B
GS2B
V
13
(2)
V
VBW
DS1B
B
RF
(
T
o
p View)
inB
RF /V
out2 DS2B
Note: Exposed
backside of the package is
the source terminal for the transistor.
VBW
V
B
DS1B
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
2. Device
can operate with V
current
DD
1. Refer to AN1977,
Quiescent Current Thermal Tracking Circuit in the RF Integrated
Circuit Family
, and to AN1987,
Quiescent Current Control for the RF Integrated Circuit
Device Family
. Go to
http://www.nxp.com/RF
and search for AN1977 or AN1987.
supplied through pin 13 and pin 17.
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Vdc
Vdc
Vdc
C
Drain
–
–
Source Voltage
Gate
–
–
Source Voltage
Operating Voltage
V
–0.5, +65
–0.5, +10
32, +0
DSS
V
GS
DD
V
Storage
T
e
mperature Range
Case Operating
T
e
mperature Range
T
stg
–65 to +150
–40 to +150
–40 to +225
T
C
C
(3,4)
Operating Junction
T
e
mperature Range
T
J
C
Table 2. Thermal Characteristics
Characteristic
(4,5)
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
C/W
JC
Case
T
e
mperature 74
C, 2.5 W, 2000 MHz
Stage 1, 28 Vdc, I
Stage 2, 28 Vdc, I
= 30 mA
= 110 mA
7.8
2.9
DQ1(A+B)
DQ2(A+B)
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22
–
–
A
1
14)
Machine Model (per EIA/JESD22
–
–
A
1
15)
Charge Device Model (per JESD22
–
–
C101)
1A
A
II
Table 4. Moisture Sensitivity Level
Test Methodology
Rating
Package Peak Temperature
Unit
Per JESD22
–
–
A
1
13, IPC/JEDEC J
–
–
STD
–
–
020
3
260
C
3. Continuous
use at maximum temperature will affect MTT
F
.
5. Refer
to AN1955,
Thermal Measurement Methodology of RF Power Amplifiers.
Go to
http://www.nxp.com/RF
and search for AN1955.
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
2
Table 5. Electrical Characteristics
(T =
25
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(1)
Stage 1
–
– Off Characteristics
Zero Gate Voltage Drain Leakage Current
I
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
(V =
65 Vdc, V
= 0 Vdc)
DS
GS
Zero Gate Voltage Drain Leakage Current
(V =
32 Vdc, V
= 0 Vdc)
DS
GS
Gate
–
–
Source Leakage Current
(V =
1.0 Vdc, V
= 0 Vdc)
I
1
GS
DS
Stage 1
–
– On Characteristics
(1)
Gate Threshold Voltage
V
V
0.8
—
1.2
1.9
8.2
1.6
—
Vdc
Vdc
Vdc
GS(th)
GS(Q)
GG(Q)
(V =
10 Vdc, I
= 2
Adc)
DS
D
Gate Quiescent Voltage
(V =
28 Vdc, I
= 32 mAdc)
DQ1(A+B)
DS
Fixture Gate Quiescent Voltage
V
7.5
9.0
(V =
28 Vdc, I
DD
= 32 mAdc, Measured in Functional
T
e
st)
DQ1(A+B)
(1)
Stage 2
–
– Off Characteristics
Zero Gate Voltage Drain Leakage Current
(V =
65 Vdc, V
= 0 Vdc)
I
—
—
—
—
—
—
10
1
Adc
Adc
Adc
DSS
DSS
GSS
DS
GS
Zero Gate Voltage Drain Leakage Current
(V =
32 Vdc, V
= 0 Vdc)
I
DS
GS
Gate
–
–
Source Leakage Current
(V =
1.0 Vdc, V
= 0 Vdc)
I
1
GS
DS
Stage 2
–
– On Characteristics
(1)
Gate Threshold Voltage
V
V
0.8
—
1.2
1.8
4.8
0.3
1.6
—
Vdc
Vdc
Vdc
Vdc
GS(th)
GS(Q)
GG(Q)
DS(on)
(V =
10 Vdc, I
= 11
Adc)
DS
D
Gate Quiescent Voltage
(V =
28 Vdc, I
= 110 mAdc)
DQ2(A+B)
DS
Fixture Gate Quiescent Voltage
(V =
28 Vdc, I
= 110 mAdc, Measured in Functional
T
e
st)
V
4.1
0.1
5.6
1.5
DD
DQ2(A+B)
(1)
Drain
–
–
Source On
–
–
V
oltage
(V =
10 Vdc, I
= 200
mAdc)
V
GS
D
1. Each
side of device measured separately.
(continued)
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
3
Table 5. Electrical Characteristics
(T =
25
C unless otherwise noted)
(continued)
A
Characteristic
Symbol
Min
Typ
= 32 mA, I
= 110 mA,
DQ2(A+B)
Max
Unit
(1,2)
Functional Tests
(In NXP Production
T
e
st Fixture, 50 ohm system) V
= 28 Vdc, I
DD
DQ1(A+B)
P
= 2.5 W Avg., f = 1900 MHz, Single
–
–
Carrier W
–
–
CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on
out
CCD
F
.
A
CPR measured in 3.84 MHz Channel Bandwidth @
5 MHz Offset.
Power Gain
G
30.2
20.3
—
31.0
21.2
35.0
—
dB
%
ps
Power Added Efficiency
PAE
ACPR
P3dB
Adjacent Channel Power Ratio
–44.0
22.2
–43.0
—
dBc
W
P
@ 3 dB Compression Point, CW
19.5
out
Load Mismatch
(In NXP Production
T
e
st Fixture, 50 ohm system) I
= 32 mA, I
= 110 mA, f = 2200 MHz
No Device Degradation
DQ1(A+B)
DQ2(A+B)
VSWR 10:1 at 32 Vdc, 46.8 W CW Output Power
(3 dB Input Overdrive from 40.7 W CW Rated Power)
(3)
Typical Performance
(In NXP Characterization
T
e
st Fixture, 50 ohm system) V
= 28 Vdc, I
= 32 mA, I
= 110 mA,
DD
DQ1(A+B)
DQ2(A+B)
1800–2200 MHz Bandwidth
P
P
@ 1 dB Compression Point, CW
P1dB
P3dB
—
16
24
—
—
—
W
W
out
out
(4)
@ 3 dB Compression Point
—
—
AM/PM
(Maximum value measured at the P3dB compression point across
–7.6
the 1800–2200 MHz frequency range.)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
VBW
—
170
—
MHz
%
res
(5)
Quiescent Current Accuracy over
T
e
mperature
I
QT
with 4.7 k
Gate Feed Resistors (
–
–
30 to 85
C) Stage 1
with 4.7 k
Gate Feed Resistors (
–
–
30 to 85
C) Stage 2
—
—
2.7
1.9
—
—
Gain Flatness in 400 MHz Bandwidth @ P
= 2.5 W Avg.
G
—
—
1.0
—
—
dB
out
F
Gain Variation over
T
e
mperature
G
0.023
dB/
C
(–30
C to +85
C)
Output Power Variation over
T
e
mperature
P1dB
—
0.015
—
dB/
C
(–30
C to +85
C)
Table 6. Ordering Information
Device
A2I20D020NR1
A2I20D020GNR1
Tape and Reel Information
Package
TO
–
–
270WB
–
–
17
R1 Suffix = 500 Units, 44 mm
T
a
pe Width, 13
–
–
Reel
TO
–
–
270WBG
–
–
17
1. Part
internally input and output matched.
2. Measurements
made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull
wing (GN) parts.
3. All
data measured in fixture with device soldered to heatsink.
4. P3dB
= P
+ 7.0 dB where P
is the average output power measured using an unclipped W
–
–
CDMA single
–
–
carrier input signal
avg
avg
where output PAR is compressed to 7.0 dB @ 0.01% probability on CCD
F
.
5. Refer
to AN1977,
Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
, and to AN1987,
Quiescent Current Control
for the RF Integrated Circuit Device Family.
Go to
http://www.nxp.com/RF
and search for AN1977 or AN1987.
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
4
V
DD1A
V
GG2A
V
DD2A
V
GG1A
R1
A2I20D020N
Rev. 4
R2
C7
C17
C15
C13
C9
C11
C5
Z1
C6
R5
C3
C4
C1
Z2
Q1
R6
C2
C14
C16
C18
C12
C10
C8
R3
R4
V
GG1B
V
DD2B
V
GG2B
D77506
V
DD1B
Note: All
data measured in fixture with device soldered to heatsink. Production fixture does not include device
soldered to heatsink.
Figure 3. A2I20D020NR1 Test Circuit Component Layout
Table 7. A2I20D020NR1 Test Circuit Component Designations and Values
Part
Description
3.9 pF Chip Capacitors
Part Number
Manufacturer
ATC
C1, C2
C3, C4
ATC600F3R9BT250XT
0.5 pF Chip Capacitors
4.7
F Chip Capacitors
10
F Chip Capacitors
ATC600F0R5BT250XT
GRM31CR71H475KA12L
GRM31CR61H106KA12L
ATC
C5, C6, C7, C8
Murata
Murata
C9, C10, C11, C12, C13,
C14, C15, C16, C17, C18
Q1
RF LDMOS Power Amplifier
A2I20D020N
NXP
R1, R2, R3, R4
R5, R6
Z1, Z2
4.7 k
, 1/4 W Chip Resistors
CRCW12064K70FKEA
060120A15Z50-2
X3C19P1-03S
D77506
Vishay
Anaren
Anaren
MTL
50
, 10 W Chip Resistors
1700–2300 MHz, 90
, 3 dB Hybrid Couplers
PCB
Rogers RO4350B, 0.020
,
= 3.66
r
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
5
TYPICAL CHARACTERISTICS — 1800–2200 MHz
33.0
32.8
32.6
32.4
32.2
32.0
31.8
31.6
31.4
26
V
= 28 Vdc, P
= 2.5 W (Avg.)
out
DD
24
I
= 32 mA, I
= 110 mA
DQ1(A+B)
DQ2(A+B)
22
D
20
18
Single
–
–
Carrier W
–
–
CDMA
3.84 MHz Channel Bandwidth
G
ps
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–42
–43
–44
PARC
ACPR
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
–45
–46
–47
31.2
31.0
1775 1825 1875
1925 1975
2025 2075 2125 2175
2225
f, FREQUENCY (MHz)
Figure 4. Single
–
-Carrier Output Peak
–
-to
–
-Average Ratio Compression
(PARC) Broadband Performance @ P
out
= 2.5 Watts Avg.
–
10
V
= 28 Vdc, P
= 8 W (PEP), I
= 32 mA
DD
out
DQ1(A+B)
I
= 110 mA, Two
–
–
T
one Measurements
DQ2(A+B)
(f1 + f2)/2 = Center Frequency of 2000 MHz
–20
–
30
–
40
–50
–
60
IM3
–
–
U
IM3
–
–
L
IM5
–
–
L
IM5
–
–
U
IM7
–
–
U
IM7
–
–
L
1
10
TWO
–
–
TONE SPACING (MHz)
100
300
Figure 5. Intermodulation Distortion Products
versus Two
–
-Tone Spacing
–5
32.0
31.5
31.0
30.5
30.0
29.5
29.0
0
–1
–2
–3
–4
45
V
= 28 Vdc, I
= 32 mA, I
= 110 mA
DD
DQ1(A+B)
DQ2(A+B)
f = 2000 MHz, Single
–
–
Carrier W
–
–
CDMA
–15
40
35
30
25
–2 dB = 3.3 W
D
–25
–35
–45
–55
–65
–1 dB = 2.1 W
ACPR
G
ps
–3 dB = 4.5 W
PARC
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
20
15
–5
–6
1
3
5
7
9
11
P
, OUTPUT POWER (WATTS)
out
Figure 6. Output Peak
–
-to
–
-Average Ratio
Compression (PARC) versus Output Power
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
6
TYPICAL CHARACTERISTICS — 1800–2200 MHz
5
33
32
31
30
29
28
27
40
35
V
= 28 Vdc, I
= 32 mA, I
= 110 mA
DQ2(A+B)
DD
DQ1(A+B)
D
–5
2200 MHz
2000 MHz
1800 MHz
G
ps
–15
–25
–35
–45
–55
30
25
Single
–
–
Carrier W
–
–
CDMA
3.84 MHz Channel Bandwidth
2200 MHz
1800 MHz
ACPR
20
15
10
1800 MHz
2000 MHz
2000 MHz
2200 MHz
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
1
10 12
P
, OUTPUT POWER (WATTS) AVG.
out
Figure 7. Single
–
-Carrier W
–
-CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
40
35
Gain
30
25
20
V
P
= 28 Vdc
= 0 dBm
DD
in
15
10
I
I
= 32 mA
= 110 mA
DQ1(A+B)
DQ2(A+B)
400
800
1200 1600
2000 2400 2800 3200
3600
f, FREQUENCY (MHz)
Figure 8. Broadband Frequency Response
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
7
Table 8. Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, I
= 16 mA, I
= 57 mA, Pulsed CW, 10
sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Output Power
P1dB
(1)
Z
AM/PM
(
)
f
Z
Z
in
(
)
load
(
)
D
source
(
)
(%)
54.5
52.5
51.6
Gain (dB)
31.6
(dBm)
40.6
(W)
11
(MHz)
1805
1840
1880
92.7 + j84.9
70.5 + j83.3
53.3 + j79.4
72.9 – j80.3
21.8 – j4.48
19.0 – j6.17
17.9 – j5.52
–3
–3
–3
62.6 – j79.4
50.7 – j74.5
31.4
40.6
11
31.3
40.6
12
Max Output Power
P3dB
(2)
Z
(
)
AM/PM
(
)
f
Z
Z
(
)
load
D
source
(
)
in
(%)
53.7
52.8
51.8
Gain (dB)
(dBm)
(W)
(MHz)
1805
1840
1880
92.7 + j84.9
71.2 – j79.5
20.1 – j7.48
18.5 – j6.91
17.5 – j6.54
29.3
41.5
14
–6
–6
–5
70.5 + j83.3
53.3 + j79.4
61.5 – j78.8
50.1 – j73.8
29.3
29.2
41.5
41.5
14
14
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured
impedance presented to the input of the device at the package reference plane.
= Impedance
as measured from gate contact to ground.
= Measured
impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Table 9. Load Pull Performance — Maximum Efficiency Tuning
V
= 28 Vdc, I
= 16 mA, I
= 57 mA, Pulsed CW, 10
sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
(
)
f
Z
Z
in
(
)
load
(
)
D
source
(
)
(%)
61.7
59.9
57.5
Gain (dB)
(dBm)
(W)
(MHz)
1805
1840
1880
92.7 + j84.9
70.5 + j83.3
53.3 + j79.4
73.1 – j84.4
41.8 + j7.22
32.6 + j4.15
26.6 + j12.0
32.9
39.0
8
–5
–4
–5
62.4 – j82.2
50.5 – j77.9
32.6
33.0
39.4
38.8
9
8
Max Drain Efficiency
P3dB
(2)
Z
(
)
AM/PM
(
)
f
Z
Z
(
)
load
D
source
(
)
in
(%)
61.1
59.8
58.1
Gain (dB)
(dBm)
(W)
(MHz)
1805
1840
1880
92.7 + j84.9
72.6 – j82.9
41.0 + j3.98
30.9 + j5.87
30.1 + j10.2
30.8
40.0
10
–8
–7
–6
70.5 + j83.3
53.3 + j79.4
62.5 – j81.6
50.2 – j76.9
30.6
30.9
40.3
39.7
11
9
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured
impedance presented to the input of the device at the package reference plane.
= Impedance
as measured from gate contact to ground.
= Measured
impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
8
P1dB
–
– TYPICAL LOAD PULL CONTOURS — 1840 MHz
20
20
15
10
5
56
36.5
15
54
10
39.5
40
39
37
5
0
E
E
38.5
58
56
37.5
0
38
–5
–5
–10
P
P
40.5
52
–10
54
50
44
–15
–20
–15
–20
46
50
48
52
10
20
10
20
30
40
50
60
30
40
50
60
REAL (
)
REAL (
)
Figure 9. P1dB Load Pull Output Power Contours (dBm)
Figure 10. P1dB Load Pull Efficiency Contours (%)
20
15
20
–14
–4
–12
–10
15
10
5
–8
10
5
–6
–4
33
E
E
0
0
32.5
–5
–5
P
P
32
–10
–10
–15
–20
31.5
31
30
–15
–20
30.5
–2
–2
29.5
10
20
10
20
30
40
REAL (
)
50
60
30
40
50
60
REAL (
)
Figure 12. P1dB Load Pull AM/PM Contours (
)
Figure 11. P1dB Load Pull Gain Contours (dB)
NOTE:
P
E
= Maximum
Output Power
= Maximum
Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
9
P3dB
–
– TYPICAL LOAD PULL CONTOURS — 1840 MHz
20
20
15
10
5
54
38
15
10
38.5
E
E
5
0
39
0
58
56
54
39.5
–5
–5
–10
P
P
40
–10
44
41
–15
–20
–15
–20
40.5
50
46
48
20
52
10
20
10
30
40
50
60
30
40
50
60
REAL (
)
REAL (
)
Figure 13. P3dB Load Pull Output Power Contours (dBm)
Figure 14. P3dB Load Pull Efficiency Contours (%)
20
20
31
–18
–16
15
15
10
30.5
–14
–12
10
5
30
–10
–8
E
E
5
0
29.5
0
29
–5
–6
–5
P
P
28.5
–4
–10
–10
–15
–20
28
–15
27.5
–2
–20
10
20
10
20
30
40
REAL (
)
50
60
30
40
50
60
REAL (
)
Figure 16. P3dB Load Pull AM/PM Contours (
)
Figure 15. P3dB Load Pull Gain Contours (dB)
NOTE:
P
E
= Maximum
Output Power
= Maximum
Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
10
Table 10. Load Pull Performance — Maximum Power Tuning
V
= 28 Vdc, I
= 16 mA, I
= 57 mA, Pulsed CW, 10
sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Output Power
P1dB
(1)
Z
AM/PM
(
)
f
Z
Z
in
(
)
load
(
)
D
source
(
)
(%)
50.7
52.9
55.3
Gain (dB)
32.6
(dBm)
40.6
(W)
12
(MHz)
2110
2140
2170
26.5 + j66.6
28.6 + j67.5
27.7 + j71.6
26.8 – j66.8
17.2 + j0.65
18.0 + j1.74
16.6 + j2.92
–4
–5
–5
26.6 – j69.1
28.6 – j71.2
33.3
40.7
12
33.9
40.8
12
Max Output Power
P3dB
(2)
Z
(
)
AM/PM
(
)
f
Z
Z
(
)
load
D
source
(
)
in
(%)
52.3
53.6
54.5
Gain (dB)
(dBm)
(W)
(MHz)
2110
2140
2170
26.5 + j66.6
26.3 – j66.3
17.2 + j0.31
17.4 + j1.43
18.6 + j0.54
30.6
41.5
14
–7
–8
–9
28.6 + j67.5
27.7 + j71.6
26.1 – j68.6
28.0 – j70.2
31.3
31.5
41.6
41.7
14
15
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Z
Z
Z
= Measured
impedance presented to the input of the device at the package reference plane.
= Impedance
as measured from gate contact to ground.
= Measured
impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Table 11. Load Pull Performance — Maximum Efficiency Tuning
V
= 28 Vdc, I
= 16 mA, I
= 57 mA, Pulsed CW, 10
sec(on), 10% Duty Cycle
DD
DQ1
DQ2
Max Drain Efficiency
P1dB
(1)
Z
AM/PM
(
)
f
Z
Z
in
(
)
load
(
)
D
source
(
)
(%)
58.3
60.9
64.3
Gain (dB)
(dBm)
(W)
(MHz)
2110
2140
2170
26.5 + j66.6
28.6 + j67.5
27.7 + j71.6
26.0 – j67.4
15.9 + j12.4
16.2 + j12.9
13.7 + j12.4
34.1
39.4
9
–5
–6
–8
26.1 – j69.4
28.1 – j71.5
34.6
35.1
39.7
39.6
9
9
Max Drain Efficiency
P3dB
(2)
Z
(
)
AM/PM
(
)
f
Z
Z
(
)
load
D
source
(
)
in
(%)
60.0
61.8
63.5
Gain (dB)
(dBm)
(W)
(MHz)
2110
2140
2170
26.5 + j66.6
25.7 – j67.3
16.2 + j12.1
14.7 + j12.9
14.2 + j13.7
32.0
40.5
11
–7
–9
28.6 + j67.5
27.7 + j71.6
25.6 – j69.4
27.4 – j71.4
32.7
33.2
40.4
40.2
11
10
–11
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Z
Z
Z
= Measured
impedance presented to the input of the device at the package reference plane.
= Impedance
as measured from gate contact to ground.
= Measured
impedance presented to the output of the device at the package reference plane.
source
in
load
Note: Measurement made on a per side basis.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Z
Z
in
Z
load
source
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
11
P1dB
–
– TYPICAL LOAD PULL CONTOURS — 2140 MHz
20
15
10
20
44
39
15
60
58
39.5
E
E
46
40
10
48
40.5
56
P
5
0
5
0
54
50
52
P
40
–5
–5
39.5
39
–10
–10
10
20
10
20
30
40
50
30
REAL (
)
40
50
REAL (
)
Figure 17. P1dB Load Pull Output Power Contours (dBm)
Figure 18. P1dB Load Pull Efficiency Contours (%)
20
20
35
–2
34.5
15
15
10
5
–8
–6
E
E
–4
34
10
–4
33.5
5
33
P
P
0
0
32.5
–5
–5
31.5
32
–10
–10
10
20
30
40
50
10
20
30
40
50
REAL (
)
REAL (
)
Figure 20. P1dB Load Pull AM/PM Contours (
)
Figure 19. P1dB Load Pull Gain Contours (dB)
NOTE:
P
E
= Maximum
Output Power
= Maximum
Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
12
P3dB
–
– TYPICAL LOAD PULL CONTOURS — 2140 MHz
20
15
10
20
39.5
39
40
15
E
E
60
40.5
10
41
58
5
0
5
0
56
P
41.5
54
50
48
P
52
46
–5
–5
–10
–10
10
20
10
20
30
REAL (
)
40
50
30
REAL (
)
40
50
Figure 21. P3dB Load Pull Output Power Contours (dBm)
Figure 22. P3dB Load Pull Efficiency Contours (%)
20
20
33
15
15
32.5
E
–12
–10
E
–2
32
10
10
5
31.5
–4
5
31
–8
P
P
0
0
30.5
–6
–8
–5
–5
30
29.5
–10
–10
10
20
10
20
30
40
50
30
REAL (
)
40
50
REAL (
)
Figure 24. P3dB Load Pull AM/PM Contours (
)
Figure 23. P3dB Load Pull Gain Contours (dB)
NOTE:
P
E
= Maximum
Output Power
= Maximum
Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
13
PACKAGE DIMENSIONS
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
14
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
15
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
16
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
17
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
18
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
19
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1907: Solder Reflow Attach Method for High Power RF Devices in Over
–
–
Molded Plastic Packages
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
Electromigration MTTF Calculator
RF High Power Model
.s2p File
Development Tools
Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to
http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
1
May 2016
May 2017
Initial release of data sheet
Typical Performance table: added VBWres, p. 4
1800–2200 MHz characterization fixture: added typical characteristic performance graphs, pp. 6
–
–
7
A2I20D020NR1 A2I20D020GNR1
RF Device Data
NXP Semiconductors
20
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright licenses
granted hereunder to design or fabricate any integrated circuits based on the information
in this document. NXP reserves the right to make changes without further notice to any
products herein.
How to Reach Us:
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including without limitation consequential or incidental damages. “Typical” parameters
that may be provided in NXP data sheets and/or specifications can and do vary in
different applications, and actual performance may vary over time. All operating
parameters, including “typicals,” must be validated for each customer application by
customer’s technical experts. NXP does not convey any license under its patent rights
nor the rights of others. NXP sells products pursuant to standard terms and conditions of
sale, which can be found at the following address:
nxp.com/Sales
T
e
rmsandConditions
.
NX
P
,
t
he NXP logo, Freescale, the Freescale logo, and Airfast are trademarks of
NXP B.
V
.
A
ll other product or service names are the property of their respective owners.
E
2016–2017 NXP B.
V
.
Document Number: A2I20D020N
Rev. 1, 05/2017
