NXP-Semicon-MFRC52302HN1-151

Part #	NXP-Semicon-MFRC52302HN1-151
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MFRC523

Standard 3V ISO/IEC 14443 A/B reader solution

Rev. 4.1 — 6 May 2015

115241

Product data sheet

COMPANY PUBLIC

1. Introduction

This document describes the functionality and electrical specifications of the contactless

reader/writer MFRC523.

1.1 Different

available versions

The MFRC523 is available in two versions:

•

MFRC52302 (HVQFN32), hereafter named as version 2.0

•

MFRC52301 (HVQFN32), hereafter named as version 1.0

The differences of the version 1.0 to the version 2.0 are summarized in

Section 11

2. General

description

The MFRC523 is a highly integrated reader/writer for contactless communication at

13.56 MHz. The MFRC523 reader supports ISO/IEC 14443 A/MIFARE mode.

The MFRC523’s internal transmitter is able to drive a reader/writer antenna designed to

communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional

active circuitry. The receiver module provides a robust and efficient implementation for

demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and

transponders. The digital module manages the complete ISO/IEC 14443 A framing and

error detection (parity and CRC) functionality.

All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication

standards are supported provided:

•

additional components, such as the oscillator, power supply, coil etc are correctly

applied

•

standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B

anticollision are correctly implemented

The MFRC523 supports contactless communication using MIFARE higher baud rates

(see

Section 8.3.4.11 on page 22

) at transfer speeds up to 848 kBd in both directions.

The following host interfaces are provided:

•

Serial Peripheral Interface (SPI)

•

Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)

•

C-bus interface

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

3. Features

and benefits



Highly integrated analog circuitry to demodulate and decode responses



Buffered output drivers for connecting an antenna with the minimum number of

external components



Supports ISO/IEC 14443 A/MIFARE



Supports ISO/IEC 14443 B Read/Write modes



Typical operating distance in Read/Write mode up to 50 mm depending on the

antenna size and tuning



Supports MIFARE Mini, MIFARE 1K and MIFARE 4K encryption in Read/Write mode



Supports ISO/IEC 14443 A higher transfer speed communication at 212 kBd, 424 kBd

and 848 kBd



Supports MFIN/MFOUT



Additional internal power supply to the smart card IC connected via MFIN/MFOUT



Supported host interfaces



SPI up to 10 Mbit/s



C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode



RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin

voltage supply



FIFO buffer handles 64 byte send and receive



Flexible interrupt modes



Hard reset with low power function



Power-down by software mode



Programmable timer



Internal oscillator for connection to 27.12 MHz quartz crystal



2.5 V to 3.3 V power supply



CRC coprocessor



Programmable I/O pins



Internal self-test

4. Quick

reference data

Table 1.

Quick reference data

Symbol Parameter

Conditions

Min

2.5

1.6

Typ

3.3

1.8

–

Max

3.6

Unit

[1][2]

[3]

DDA

DDD

analog supply voltage

digital supply voltage

DD(PVDD)



DDA

= V

DDD

= V

DD(TVDD)

;

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

DD(TVDD)

TVDD supply voltage

DD(PVDD)

PVDD supply voltage

DD(SVDD)

SVDD supply voltage

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V

hard power-down; pin NRSTPD set LOW

soft power-down; RF level detector on

pin DVDD; V

DDD

= 3 V

power-down current

[4]

–



–

DDD

digital supply current

6.5

MFRC523

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Product data sheet

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Standard 3V ISO/IEC 14443 A/B reader solution

Table 1.

Quick reference data

…continued

Symbol Parameter

Conditions

Min

Typ

Max

Unit

DDA

analog supply current

pin AVDD; V

DDA

= 3 V, CommandReg register’s

RcvOff bit = 0

–

pin AVDD; receiver switched off; V

DDA

= 3

CommandReg register’s RcvOff bit = 1

–

[5]

DD(PVDD)

PVDD supply current

DD(TVDD)

TVDD supply current

pin PVDD

–



[6][7][8]

pin TVDD; continuous wave

HVQFN32

–

100

+85

amb

ambient temperature



[1] Supply

voltages below 3 V reduce the performance in, for example, the achievable operating distance.

[2] V

DDA

, V

DDD

and V

DD(TVDD)

must always be the same voltage.

[3]

DD(PVDD)

must always be the same or lower voltage than V

DDD

[4] I

is the total current for all supplies.

[5] I

DD(PVDD)

depends on the overall load at the digital pins.

[6]

DD(TVDD)

depends on V

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

[7] During

typical circuit operation, the overall current is below 100 mA.

[8] Typical

value using a complementary driver configuration and an antenna matched to 40



between pins TX1 and TX2 at 13.56 MHz.

5. Ordering

information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

MFRC52302HN1/TRAYB

[1]

HVQFN32 plastic

thermal enhanced very thin quad flat package; no leads;

SOT617-1

32 terminal; body 5



0.85 mm

MFRC52302HN1/TRAYBM

[2]

HVQFN32 plastic

thermal enhanced very thin quad flat package; no leads;

SOT617-1

32 terminal; body 5



0.85 mm

MFRC52301HN1/TRAYB

[1]

HVQFN32 plastic

thermal enhanced very thin quad flat package; no leads;

32 terminal; body 5



0.85 mm

MFRC52301HN1/TRAYBM

[2]

HVQFN32 plastic

thermal enhanced very thin quad flat package; no leads;

32 terminal; body 5



0.85 mm

[1] Delivered

in one tray.

[2] Delivered

in five trays.

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

6. Block

diagram

The analog interface manages the modulation and demodulation of the analog signals.

The contactless UART manages the protocol requirements for the communication

protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data

transfers to/from the host and the contactless UAR

Various host interfaces are implemented to meet different customer requirements.

ANALOG

INTERFACE

CON

ACTLESS

UART

ANTENNA

FIFO

BUFFER

SERIAL UART

SPI

I C-BUS

HOST

001aaj627

Fig 1.

Simplified block diagram of the MFRC523

MFRC523

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Product data sheet

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MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

D6/ADR_0/

MOSI/MX

D2/ADR_4

D1/ADR_5 D3/ADR_3

25 26 27

D4/ADR_2

D5/ADR_1/

D7/SCL/

SDA/NSS/RX EA I2C

24 32

PVDD PVSS

SCK/DTRQ

MISO/TX

DVDD

DVSS

VOLTAGE

MONITOR

AND

POWER ON

DETECT

SPI, UAR

, I

-BUS INTERFACE CONTROL

AVDD

AVSS

FIFO CONTROL

STATE MACHINE

64-BYTE FIFO

BUFFER

RESET

CONTROL

COMMAND REGISTER

PROGRAMABLE TIMER

INTERRUPT CONTROL

CRC16

POWER-DOWN

CONTROL

NRSTPD

IRQ

CONTROL REGISTER

BANK

MIFARE CLASSIC UNIT

GENERATION AND CHECK

RANDOM NUMBER

GENERATOR

PARALLEL/SERIAL

CONVERTER

BIT COUNTER

PARITY GENERATION AND CHECK

FRAME GENERATION AND CHECK

BIT DECODING

BIT ENCODING

MFIN

SERIAL DATA SWITCH

MFOUT

SVDD

CLOCK

OSCIN

GENERATION,

FILTERING AND

DISTRIBUTION

AMPLITUDE

RATING

OSCILLATOR

ANALOG TO DIGITAL

CONVERTER

OSCOUT

REFERENCE

VOLTAGE

Q-CLOCK

GENERATION

TEMPERATURE

SENSOR

ANALOG TEST

MULTIPLEXOR

AND

DIGITAL TO

ANALOG

I-CHANNEL

AMPLIFIER

Q-CHANNEL

AMPLIFIER

TRANSMITTER CONTROL

I-CHANNEL

DEMODULATOR

Q-CHANNEL

DEMODULATOR

CONVERTER

10, 14

TVSS

TX1

TX2

VMID AUX1 AUX2

TVDD

001aak602

Fig 2.

Detailed block diagram of the MFRC523

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

7. Pinning

information

I2C

PVDD

SDA/NSS/RX

IRQ

DVDD

OSCOUT

OSCIN

AUX2

DVSS

MFRC523

PVSS

NRSTPD

MFIN

AUX1

AVSS

MFOUT

001aal155

ansparent top view

Fig 3.

Pinning configuration HVQFN32 (SOT617-1)

7.1 Pin

description

Table 3.

Pin description

Symbol

I2C

Type

[1]

Description

[2]

C-bus enable input

PVDD

DVDD

DVSS

PVSS

NRSTPD

pin power supply

digital power supply

[3]

digital ground

pin power supply ground

reset and power-down input:

reset: enabled by a positive edge

power-down: enabled when LOW; internal current sinks are switched off, the oscillator

is inhibited and the input pins are disconnected from the outside world

MFIN

MFOUT

SVDD

TVSS

TX1

MIFARE signal input

MIFARE signal output

MFIN and MFOUT pin power supply

transmitter output stage 1 ground

transmitter 1 modulated 13.56 MHz energy carrier output

transmitter power supply: supplies the output stage of transmitters 1 and 2

transmitter 2 modulated 13.56 MHz energy carrier output

transmitter output stage 2 ground

TVDD

TX2

TVSS

AVDD

analog power supply

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

Table 3.

Pin description

…continued

Symbol

VMID

Type

[1]

Description

internal reference voltage

RF signal input

AVSS

AUX1

AUX2

OSCIN

analog ground

auxiliary outputs for test purposes

crystal oscillator inverting amplifier input; also the input for an externally generated clock

clk

= 27.12 MHz)

OSCOUT

IRQ

SDA

[2]

NSS

[2]

crystal oscillator inverting amplifier output

interrupt request output: indicates an interrupt event

C-bus serial data line input/output

SPI signal input

I/O

UART address input

[2]

ADR_5

[2]

I/O

test port

C-bus address 5 input

test port

ADR_4

[2]

ADR_3

[2]

C-bus address 4 input

test port

C-bus address 3 input

I/O

test port

ADR_2

[2]

ADR_1

[2]

SCK

[2]

DTRQ

[2]

ADR_0

[2]

MOSI

[2]

C-bus address 2 input

test port

C-bus address 1 input

I/O

SPI serial clock input

UART request to send output to microcontroller

test port

C-bus address 0 input

SPI master out, slave in

UART output to microcontroller

test port

C-bus clock input/output

SPI master in, slave out

UART data output to microcontroller

external address input for coding I

C-bus address

I/O

SCL

[2]

MISO

[2]

[1] Pin

types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.

[2] The

pin functionality of these pins is explained in

Section 8.3 “Digital interfaces”

[3] Connection

of heatsink pad on package underside is not necessary. Optional connection to pin DVSS is possible.

MFRC523

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Product data sheet

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MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

8. Functional

description

The MFRC523 transmission module supports ISO/IEC 14443 A and ISO/IEC 14443 B

Read/Write mode at various transfer speeds and modulation protocols.

BATTERY

MFRC523

ISO/IEC 14443 A CARD

MICROCONTROLLER

contactless card

reader/writer

001aal156

Fig 4.

MFRC523 Read/Write mode

8.1 ISO/IEC

14443 A functionality

The physical level communication is shown in

Figure 5

(1)

ISO/IEC 14443 A

READER

ISO/IEC 14443 A CARD

(2)

MFRC523

001aal157

(1) Reader

to card (MFRC523 sends data to a card).

(2) Card

to reader (card sends data to the MFRC523).

Fig 5.

ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram

The physical parameters are described in

ble 4

Table 4.

Communication overview for ISO/IEC 14443 A reader/writer

Communication

direction

Signal type

Transfer speed

106 kBd

212 kBd

424 kBd

848 kBd

Reader to card

reader side

100 % ASK

(MFRC523 sends data

modulation

to a card)

bit encoding

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

bit length

128 (13.56



64 (13.56



32 (13.56



16 (13.56



Card to reader (card

sends data to the

MFRC523)

card side

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier

frequency

13.56 MHz / 16

bit encoding

Manchester

encoding

BPSK

The MFRC523’s contactless UART and dedicated external host must manage the

ISO/IEC 14443 A protocol.

Figure 6

shows the data coding and framing according to

ISO/IEC 14443 A.

MFRC523

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Product data sheet

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MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

ISO/IEC 14443 A framing at 106 kBd

start

8-bit data

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

start

even

parity

8-bit data

odd

parity

odd

parity

start bit is 0

burst of 32

subcarrier clocks

even parity at the

end of the frame

001aak585

Fig 6.

Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A

part 3 and handles parity generation internally based on the transfer speed. Automatic

parity generation can be switched off using the ManualRCVReg register’s ParityDisable

bit.

8.2 ISO/IEC

14443 B functionality

The MFRC523 reader IC fully supports the ISO 14443 international standard which

includes the communication schemes ISO 14443 A and ISO 14443 B. Refer to the

ISO 14443 reference documents

Identification cards – Contactless integrated circuit cards

– Proximity cards

(parts 1 to 4).

8.3 Digital

interfaces

8.3.1 Automatic

microcontroller interface detection

The MFRC523 supports direct interfacing to hosts using SPI, I

C-bus or serial UART

interfaces. The MFRC523 resets its interface and checks the current host interface type

automatically after performing a power-on or hard reset.

The MFRC523 identifies the host interface by sensing the logic levels on the control pins

after the reset phase. This is done using a combination of fixed pin connections.

ble 5

shows the different pin connection configurations.

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

Table 5.

Connection protocol for detecting different interface types

Interface type

UART (input)

SPI (output)

C-bus (I/O)

SDA

I2C

NSS

MISO

SCL

MOSI

ADR_0

ADR_1

ADR_2

ADR_3

ADR_4

ADR_5

DTRQ

SCK

–

8.3.2 Serial

Peripheral Interface

The 5-wire Serial Peripheral Interface (SPI) is supported and enables high-speed

communication with the host. The interface can manage data speeds up to 10 Mbit/s.

When communicating with a host, the MFRC523 acts as a slave. As such, it receives data

from the external host for register settings, sends and receives data relevant for RF

interface communication.

An interface compatible with SPI enables high-speed serial communication between the

MFRC523 and a microcontroller. The implemented interface meets with the SPI standard.

The timing specification is given in

Section 15.1 on page 78

MFRC523

SCK

MOSI

MISO

NSS

001aal159

Fig 7.

SPI connection to host

The MFRC523 acts as a slave during SPI communication and is timed using the SPI clock

signal (SCK) generated by the master. Data communication from the master to the slave

uses the MOSI line. The MISO line is used to send data from the MFRC523 to the master.

Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI

and MISO lines must be stable on the rising edge of the clock and can be changed on the

falling edge. Data is sent by the MFRC523 on the falling clock edge and is stable during

the rising clock edge.

8.3.2.1 SPI

read data

Reading data using SPI requires the byte order shown in

ble 6

to be used. It is possible

to read out up to n-data bytes.

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

The first byte sent defines both the mode and the address.

Table 6.

MOSI and MISO byte order

Line

Byte 0

address 0

[1]

Byte 1

Byte 2

…

Byte n

Byte n + 1

MOSI

MISO

address 1

data 0

address 2

data 1

address n

data n



…

data n

[1] X

= Do not care.

Remark:

The MSB must be sent first.

8.3.2.2 SPI

write data

rite data to the MFRC523 using SPI requires the byte order shown in

ble 7

. It is

possible to write up to n-data bytes by only sending one address byte.

The first send byte defines both the mode and the address byte.

Table 7.

Line

MOSI and MISO byte order

Byte 0

address 0

[1]

Byte 1

data 0

[1]

Byte 2

data 1

[1]

…

Byte n

data n



[1]

Byte n + 1

data n

[1]

MOSI

MISO

…

[1] X

= Do not care.

Remark:

The MSB must be sent first.

8.3.2.3 SPI

Read and Write address byte

The read address byte must meet the following criteria:

•

the Most Significant Bit (MSB) of the first byte sets the mode.

ead data from the

MFRC523, the MSB is set to logic 1; see

ble 8

•

bits [6:1] define the address

•

the Least Significant Bit (LSB) should be set to logic 0

Table 8.

SPI read address

Address

(MOSI)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

byte 0

address address address address address address

MFRC523

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The write address byte must meet the following criteria:

•

the MSB of the first byte sets the mode.

rite data to the MFRC523, the MSB is set

to logic 0; see

ble 9

•

bits [6:1] define the address

•

the LSB should be set to logic 0

Table 9.

SPI write address

Address line

(MOSI)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

byte 0

address address address address address address

8.3.3 UART

interface

8.3.3.1 Connection

to a host

MFRC523

DTRQ

001aal158

Fig 8.

UART connection to microcontrollers

Remark:

Signals DTRQ and MX can be disabled by clearing

stPinEnReg register’s

RS232LineEn bit.

8.3.3.2 Selectable

UART transfer speeds

The internal UART interface is compatible with the RS232 serial interface.

The default transfer speed is 9.6 kBd.

hange the transfer speed, the host controller

must write a value for the new transfer speed to the SerialSpeedReg register. Bits

BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the

SerialSpeedReg register.

The BR_T0[2:0] and BR_T1[4:0] settings are described in

ble 10

. Examples of different

transfer speeds and the relevant register settings are given in

ble 11

Table 10.

BR_T0 and BR_T1 settings

BR_Tn

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

BR_T0 factor

BR_T1 range

1 to 32

33 to 64

MFRC523

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Table 11.

Selectable UART transfer speeds

Transfer speed (kBd)

SerialSpeedReg value

Transfer speed accuracy (%)

[1]

Decimal

250

235

218

203

171

154

122

116

Hexadecimal

FAh

7.2



0.25

0.32

9.6

EBh

14.4

19.2

38.4

57.6

115.2

128

DAh



0.25

0.32

CBh

ABh

0.32

9Ah



0.25



0.25



0.06



0.25



0.25

1.45

7Ah

74h

230.4

460.8

921.6

1228.8

5Ah

3Ah

1Ch

15h

0.32

[1] The

resulting transfer speed error is less than 1.5 % for all described transfer speeds.

The selectable transfer speeds shown in

ble 11

are calculated according to the

following equations:

If BR_T0[2:0] = 0:

27.12







transfer speed

(1)

(2)

——————————-

If BR_T0[2:0] > 0:









27.12







——————————–

–

transfer speed





———————————-



–



Remark:

Transfer speeds above 1228.8 kBd are not supported.

8.3.3.3 UART

framing

Table 12.

UART framing

Bit

Length

1-bit

Value

Start

Data

Stop

8-bit

data

1-bit

Remark:

The LSB for data and address bytes must be sent first. No parity bit is used

during transmission.

ead data using the UART interface, the flow shown in

ble 13

must be used. The first

byte sent defines both the mode and the address.

MFRC523

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Standard 3V ISO/IEC 14443 A/B reader solution

Table 13.

Read data byte order

Byte 0

address

–

Byte 1

–

data 0

ADDRESS

(1)

R/W SO

DATA

DTRQ

001aak588

(1) Reserved.

Fig 9.

UART read data timing diagram

rite data to the MFRC523 using the UART interface, the structure shown in

ble 14

must be used.

The first byte sent defines both the mode and the address.

Table 14.

Write data byte order

Byte 0

Byte 1

address 0

–

data 0

address 0

MFRC523

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ADDRESS

DATA

SA A0 A1 A2 A3 A4 A5

(1)

R/W SO

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

ADDRESS

SA A0 A1 A2 A3 A4 A5

(1)

R/W SO

DTRQ

001aak589

(1) Reserved.

Remark:

The data byte can be sent directly after the address byte on pin RX.

Fig 10.

UART write data timing diagram

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

The address byte must meet the following formats:

•

the MSB of the first byte sets the mode used

–

the MSB is set to logic 0 to write data to the MFRC523

–

the MSB is set to logic 1 to read data from the MFRC523

•

bit 6 is reserved for future use

•

bits [5:0] define the address; see

ble 15

Table 15.

Address byte 0 register; address MOSI

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

1 or 0

reserved

address

8.3.4 I

C Bus Interface

An I

C-bus interface is supported and enables implementation of a low-cost, low pin count

serial bus interface to the host. The I

C-bus interface is implemented based on

NXP Semiconductors’

C-bus interface specification, rev. 2.1, January 2000

. The

interface can only act in slave mode. Therefore the MFRC523 does not perform clock

generation or access arbitration.

PULL-UP

NETWORK

PULL-UP

NETWORK

MFRC523

SDA

SCL

MICROCONTROLLER

I2C

CONFIGURATION

WIRING

ADR_[5:0]

001aal160

Fig 11.

C-bus interface

The MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast

mode and High-speed mode.

SDA is a bidirectional line connected to a positive supply voltage using a current source or

a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The

MFRC523 has a 3-state output stage to perform the wired-AND function. Data on the

C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to

400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.

If the I

C-bus interface is selected, spike suppression is activated on lines SCL and SDA

as defined in the I

C-bus interface specification.

See

ble 156 on page 79

for timing requirements.

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8.3.4.1 Data

validity

Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW

state of the data line must only change when the clock signal on SCL is LOW.

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mbc621

Fig 12.

Bit transfer on the I

C-bus

8.3.4.2 START

and STOP conditions

anage the data transfer on the I

C-bus, unique START (S) and STOP (P) conditions

are defined.

•

A START condition is defined with a HIGH-to-LOW transition on the SDA line while

SCL is HIGH.

•

A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while

SCL is HIGH.

The I

C-bus master always generates the START and STOP conditions. The bus is busy

after the START condition. The bus is free again a certain time after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.

The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,

S is used as a generic term to represent both the START (S) and repeated START (Sr)

conditions.

SDA

SCL

SDA

SCL

START condition

STOP condition

mbc622

Fig 13.

START and STOP conditions

8.3.4.3 Byte

format

Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;

see

Figure 16

. The number of transmitted bytes during one data transfer is unrestricted

but must meet the read/write cycle format.

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8.3.4.4 Acknowledge

An acknowledge must be sent at the end of one data byte. The acknowledge-related clock

pulse is generated by the master. The transmitter of data, either master or slave, releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the

SDA line during the acknowledge clock pulse so that it remains stable LOW during the

HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer or a

repeated START (Sr) condition to start a new transfer.

A master-receiver indicates the end of data to the slave-transmitter by not generating an

acknowledge on the last byte that was clocked out by the slave. The slave-transmitter

releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

clock pulse for

acknowledgement

START

condition

mbc602

Fig 14.

Acknowledge on the I

C-bus

SDA

acknowledgement

signal from slave

acknowledgement

signal from receiver

MSB

byte complete,

interrupt within slave

clock line held LOW while

interrupts are serviced

SCL

3 – 8

ACK

START or

repeated START

condition

STOP or

repeated START

condition

msc608

Fig 15.

Data transfer on the I

C-bus

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8.3.4.5 7-Bit

addressing

During the I

C-bus address procedure, the first byte after the START condition is used to

determine which slave will be selected by the master.

Several address numbers are reserved. During device configuration, the designer must

ensure that collisions with these reserved addresses cannot occur. Check the

C-bus

specification

for a complete list of reserved addresses.

The I

C-bus address specification is dependent on the definition of pin EA. Immediately

after releasing pin NRSTPD or after a power-on reset, the device defines the I

C-bus

address according to pin EA.

If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by

NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits

(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer

to prevent collisions with other I

C-bus devices.

If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins

according to

ble 5 on page 10

. ADR_6 is always set to logic 0.

In both modes, the external address coding is latched immediately after releasing the

reset condition. Further changes at the used pins are not taken into consideration.

Depending on the external wiring, the I

C-bus address pins can be used for test signal

outputs.

MSB

bit 6

LSB

R/W

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

slave address

001aak591

Fig 16.

First byte following the START procedure

8.3.4.6 Register

write access

rite data from the host controller using the I

C-bus to a specific register in the

MFRC523 the following frame format must be used.

•

The first byte of a frame indicates the device address according to the I

C-bus rules.

•

The second byte indicates the register address followed by up to n-data bytes.

In one frame, all data bytes are written to the same register address. This enables fast

FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.

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8.3.4.7 Register

read access

ead out data from a specific register address in the MFRC523, the host controller must

use the following procedure:

•

Firstly, a write access to the specific register address must be performed as indicated

in the frame that follows

•

The first byte of a frame indicates the device address according to the I

C-bus rules

•

The second byte indicates the register address. No data bytes are added

•

The Read/Write bit is 0

After the write access, read access can start. The host sends the device address of the

MFRC523. In response, the MFRC523 sends the content of the read access register. In

one frame all data bytes can be read from the same register address. This enables fast

FIFO buffer access or register polling.

The Read/Write (R/W) bit is set to logic 1.

write cycle

I C-BUS

SLAVE ADDRESS

[A7:A0]

(W)

JOINER REGISTER

ADDRESS [A5:A0]

DATA

[7:0]

[0:n]

read cycle

I C-BUS

(W)

JOINER REGISTER

ADDRESS [A5:A0]

SLAVE ADDRESS

[A7:A0]

optional, if the previous access was on the same register address

[0:n]

I C-BUS

(R)

DATA

[7:0]

SLAVE ADDRESS

[A7:A0]

[0:n]

DATA

[7:0]

sent by master

start condition

stop condition

acknowledge

not acknowledge

write cycle

sent by slave

read cycle

001aak592

Fig 17.

MFRC523

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8.3.4.8 High-speed

mode

In High-speed mode (HS mode), the device can transfer information at data rates of up to

3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard modes

(F/S modes) for bidirectional communication in a mixed-speed bus system.

8.3.4.9 High-speed

transfer

chieve data rates of up to 3.4 Mbit/s the following improvements have been made to

C-bus operation.

•

The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger

on the SDA and SCL inputs and different timing constants when compared to

F/S mode

•

The output buffers of the device in HS mode incorporate slope control of the falling

edges of the SDA and SCL signals with different fall times compared to F/S mode

8.3.4.10 Serial

data transfer format in HS mode

The HS mode serial data transfer format meets the Standard mode I

C-bus specification.

HS mode can only start after all of the following conditions (all of which are in F/S mode):

1. START

condition (S)

2. 8-bit

master code (00001 XXXb)

3. Not-acknowledge

bit (A)

When HS mode starts, the active master sends a repeated START condition (Sr) followed

by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from

the selected MFRC523.

Data transfer continues in HS mode after the next repeated START (Sr), only switching

back to F/S mode after a STOP condition (P).

educe the overhead of the master code,

a master links a number of HS mode transfers, separated by repeated START conditions

(Sr).

HS mode (current-source for SCL HIGH enabled)

F/S mode

MASTER CODE

Sr SLAVE

ADDRESS R/W

DATA

A/A

(n-bytes + A)

HS mode continues

SLAVE ADDRESS

001aak749

Fig 18.

C-bus HS mode protocol switch

MFRC523

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8-bit master code 0000 1xxx

SDA high

SCL high

2 to 5

F/S mode

n + (8-bit data

A/A)

R/W

7-bit SLA

Sr P

SDA high

SCL high

2 to 5

If P then

HS mode

F/S mode

If Sr (dotted lines)

then HS mode

= Master current source pull-up

= Resistor pull-up

msc618

Fig 19.

C-bus HS mode protocol frame

8.3.4.11 Switching

between F/S mode and HS mode

After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as

Fast mode is downward-compatible with Standard mode). The connected MFRC523

recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast

mode setting to the HS mode setting.

The following actions are taken:

1. Adapt

the SDA and SCL input filters according to the spike suppression requirement

in HS mode.

2. Adapt

the slope control of the SDA output stages.

It is possible for system configurations that do not have other I

C-bus devices involved in

the communication to switch to HS mode permanently. This is implemented by setting

Status2Reg register’s I

CForceHS bit to logic 1. In permanent HS mode, the master code

is not required to be sent. This is not defined in the specification and must only be used

when no other devices are connected on the bus. In addition, spikes on the I

C-bus lines

must be avoided because of the reduced spike suppression.

8.3.4.12 MFRC523

in lower speed modes

MFRC523 is fully downward-compatible and can be connected to an F/S mode I

C-bus

system. The device stays in F/S mode and communicates at F/S mode speeds because a

master code is not transmitted in this configuration.

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8.4 Analog

interface and contactless UART

8.4.1 General

The integrated contactless UART supports the external host online with framing and error

checking of the protocol requirements up to 848 kBd. An external circuit can be connected

to the communication interface pins MFIN and MFOUT to modulate and demodulate the

data.

The contactless UART manage the protocol requirements for the communication

protocols in cooperation with the host. Protocol handling generates bit and byte-oriented

framing. In addition, it manages error detection such as parity and CRC, based on the

various supported contactless communication protocols.

Remark:

The size and tuning of the antenna and the power supply voltage have an

important impact on the achievable operating distance.

8.4.2 TX

p-driver

The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an

envelope signal. It can be used to drive an antenna directly using a few passive

components for matching and filtering; see

Section 16 on page 81

. The signal on pins TX1

and TX2 can be configured using the TxControlReg register; see

Section 9.2.2.5 on

page 49

The modulation index can be set by adjusting the impedance of the drivers. The

impedance of the p-driver can be configured using registers CWGsPReg and

ModGsPReg. The impedance of the n-driver can be configured using the GsNReg

The TxModeReg and TxSelReg registers control the data rate and framing during

transmission and the antenna driver setting to support the different requirements at the

different modes and transfer speeds.

Table 16.

Bit

Tx1RFEn Force

100ASK

Bit

Envelope Pin

TX1

GSPMos GSNMos Remarks

InvTx1RFOn InvTx1RFOff

[1]

not specified if RF is

switched off

pMod

pCW

pMod

pCW

pMod

nMod

nCW

nMod

nCW

nMod

nCW

100 % ASK: pin TX1

pulled to logic 0,

independently of the

InvTx1RFOff bit

[1]

RF_n pCW

[1] X

= Do not care.

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Table 17.

Bit

Tx1RFEn Force

100ASK

Bit

Envelope Pin

TX2

GSPMos GSNMos Remarks

Tx2CW InvTx2RFOn

InvTx2RFOff

[1]

not specified if

RF is switched

off

[1]

pMod

pCW

nMod

nCW

nMod

nCW

–

RF_n pMod

RF_n pCW

[1]

pCW

conductance

always CW for

the Tx2CW bit

RF_n pCW

[1]

pMod

pCW

pMod

nMod

nCW

nMod

nCW

100 % ASK: pin

TX2 pulled

to logic 0

(independent of

the

InvTx2RFOn/Inv

Tx2RFOff bits)

RF_n pCW

RF pCW

RF_n pCW

[1]

[1] X

= Do not care.

The following abbreviations have been used in

ble 16

and

ble 17

•

RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2

•

RF_n: inverted 13.56 MHz clock

•

GSPMos: conductance, configuration of the PMOS array

•

GSNMos: conductance, configuration of the NMOS array

•

pCW: PMOS conductance value for continuous wave defined by the CWGsPReg

•

pMod: PMOS conductance value for modulation defined by the ModGsPReg register

•

nCW: NMOS conductance value for continuous wave defined by the GsNReg

•

nMod: NMOS conductance value for modulation defined by the GsNReg register’s

ModGsN[3:0] bits

•

X = Do not care

Remark:

If only one driver is switched on, the values for CWGsPReg, ModGsPReg and

GsNReg registers are used for both drivers.

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8.4.3 Serial

data switch

Two main blocks are implemented in the MFRC523. The digital block comprises the state

machines, encoder/decoder logic. The analog block comprises the modulator and

antenna drivers, the receiver and amplifiers. It is possible for the interface between these

two blocks to be configured so that the interfacing signals are routed to pins MFIN and

MFOU

his topology allows the analog block of the MFRC523 to be connected to the

digital block of another device.

The serial signal switch is controlled by the TxSelReg and RxSelReg registers.

Figure 20

shows the serial data switch for TX1 and TX2.

DriverSel[1:0]

3-state

envelope

INTERNAL

CODER

INVERT IF

InvMod = 1

to driver TX1 and TX2

0 = impedance = modulated

1 = impedance = CW

INVERT IF

PolMFin = 0

MFIN

001aak593

Fig 20.

Serial data switch for TX1 and TX2

8.4.4 MFIN

and MFOUT interface support

The MFRC523 is divided into a digital circuit block and an analog circuit block. The digital

block contains state machines, encoder and decoder logic, etc. The analog block contains

the modulator and antenna drivers, receiver and amplifiers. The interface between these

two blocks can be configured to enable the interfacing signals to be routed to pins MFIN

and MFOU

;

Figure 21 on page 26

. This configuration is implemented using

TxSelReg register’s MFOutSel[3:0]/DriverSel[1:0] bits and RxSelReg register’s

UARTSel[1:0] bits. This topology allows some parts of the analog block to be connected to

the digital block of another device.

Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and

ISO/IEC14443 A related signals. This is especially important during the design-in phase

or for testing purposes as it enables checking of the transmitted and received data.

The most important use of pins MFIN and MFOUT is found in the active antenna concept.

An external active antenna circuit can be connected to the MFRC523’s digital block.

Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to

pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a

Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).

It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the

appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at

the same time. In this configuration, two RF circuits can be driven (one after another) by a

single host processor.

Remark:

Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground

on pin PVSS.

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MFOUT

3-state

LOW

3-state

internal envelope

envelope from pin MFIN

HIGH

TX2

TX1

TX bit stream

MILLER

CODER

MODULATOR

DRIVER

MFOutSel[3:0]

HIGH

DRIVER

Sel[1:0]

test bus

internal envelope

TX serial data stream

reserved

DIGITAL MODULE

ANALOG MODULE

MFRC523

RX serial data stream

MFRC523

SUBCARRIER

DEMODULATOR

LOW

Manchester with subcarrier

internal modulated

RX bit stream

MANCHESTER

DECODER

DEMODULATOR

UART

NRZ coding without subcarrier (> 106 kBd)

Sel[1:0]

MFIN

001aal161

Fig 21.

Overview of MFIN and MFOUT signal routing

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

8.4.5 CRC

coprocessor

The following CRC coprocessor parameters can be configured:

•

The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on

the ModeReg register’s CRCPreset[1:0] bits setting

•

The CRC polynomial for the 16-bit CRC is fixed to x

+ x

+ 1

•

The CRCResultReg register indicates the result of the CRC calculation. This register

is split into two 8-bit registers representing the higher and lower bytes.

•

The ModeReg register’s MSB first bit indicates that data will be loaded with the MSB

first.

Table 18.

CRC coprocessor parameters

Parameter

Value

CRC register length

CRC algorithm

CRC preset value

16-bit CRC

algorithm according to ISO/IEC 14443 A and ITU-T

0000h, 6363h, A671h or FFFFh depending on the setting of the

ModeReg register’s CRCPreset[1:0] bits

8.5 FIFO

buffer

An 8



64 bit FIFO buffer is used in the MFRC523. It buffers the input and output data

stream between the host and the MFRC523’s internal state machine. This makes it

possible to manage data streams up to 64 bytes long without the need to take timing

constraints into account.

8.5.1 Accessing

the FIFO buffer

The FIFO buffer input and output data bus is connected to the FIFODataReg register.

Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO

buffer write pointer. Reading from this register shows the FIFO buffer contents stored in

the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance

between the write and read pointer can be obtained by reading the FIFOLevelReg

When the microcontroller starts a command, the MFRC523 can, while the command is in

progress, access the FIFO buffer according to that command. Only one FIFO buffer has

been implemented which can be used for input and output. The microcontroller must

ensure that there are not any unintentional FIFO buffer accesses.

8.5.2 Controlling

the FIFO buffer

The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit

to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg

accessible allowing the FIFO buffer to be filled with another 64 bytes.

8.5.3 FIFO

buffer status information

The host can get the following FIFO buffer status information:

•

Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]

•

FIFO buffer almost full warning: Status1Reg register’s HiAlert bit

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•

FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit

•

FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit

can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.

The MFRC523 can generate an interrupt signal when:

•

ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s LoAlert bit changes to logic 1.

•

ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s HiAlert bit changes to logic 1.

If the maximum number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or

less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according

Equation 3

HiAlert



–

FIFOLength

 

WaterLevel

(3)

If the number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or less are

stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to

Equation 4

LoAlert

FIFOLength



WaterLevel

(4)

8.6 Interrupt

request system

The MFRC523 indicates certain events by setting the Status1Reg register’s IRq bit and, if

activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its

interrupt handling capabilities. This allows the implementation of efficient host software.

8.6.1 Interrupt

sources overview

ble 19

shows the available interrupt bits, the corresponding source and the condition for

its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by

the timer unit which is set when the timer decrements from 1 to 0.

The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state

changes from sending data to transmitting the end of the frame pattern, the transmitter

unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg

CRCReady bit = 1.

The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received

data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and

the Command[3:0] value in the CommandReg register changes to idle (see

ble 150 on

page 69

The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s

HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level

indicated by the WaterLevel[5:0] bits.

The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s

LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level

indicated by the WaterLevel[5:0] bits.

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The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART

during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.

Table 19.

Interrupt sources

Interrupt flag

Interrupt source

Trigger action

TimerIRq

TxIRq

timer unit

the timer counts from 1 to 0

a transmitted data stream ends

all data from the FIFO buffer has been processed

a received data stream ends

command execution finishes

the FIFO buffer is almost full

the FIFO buffer is almost empty

an error is detected

transmitter

CRCIRq

RxIRq

CRC coprocessor

receiver

IdleIRq

ComIrqReg register

FIFO buffer

HiAlertIRq

LoAlertIRq

ErrIRq

FIFO buffer

contactless UART

8.7 Timer

unit

The MFRC523A has a timer unit which the external host can use to manage timing tasks.

The timer unit can be used in one of the following timer/counter configurations:

•

Timeout counter

•

Watchdog counter

•

Stop watch

•

Programmable one shot

•

Periodic trigger

The timer unit can be used to measure the time interval between two events or to indicate

that a specific event occurred after a specific time. The timer can be triggered by events

explained in the paragraphs below. The timer does not influence any internal events, for

example, a time-out during data reception does not automatically influence the reception

process. In addition, several timer-related bits can be used to generate an interrupt.

The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal

oscillator. The timer consists of two stages: prescaler and counter.

The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and

TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg

The reload value for the counter is defined by 16 bits between 0 and 65535 in the

TReloadReg register.

The current value of the timer is indicated in the TCounterValReg register.

When the counter reaches 0, an interrupt is automatically generated, indicated by the

ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on

pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the

configuration, the timer will stop at 0 or restart with the value set in the TReloadReg

The timer status is indicated by the Status1Reg register’s TRunning bit.

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The timer can be started manually using the ControlReg register’s TStartNow bit and

stopped using the ControlReg register’s TStopNow bit.

The timer can also be activated automatically to meet any dedicated protocol

requirements, by setting the TModeReg register’s TAuto bit to logic 1.

The delay time of a timer stage is set by the reload value + 1. The total delay time (t

) is

calculated using

Equation 5



TPrescaler



  

TReloadVal



(5)

———————————————————————————————————

13.56 MHz

or if the TPrescalEven bit is set, using

Equation 6



TPrescaler



  

TReloadVal



———————————————————————————————————

(6)

13.56 MHz

An example of calculating total delay time (t

) is shown in

Equation 7

, where the

TPrescaler value = 4095 and TReloadVal = 65535:



4095



  

65535



39.59 s

(7)

———————————————————————-

13.56 MHz

Example:

ive a delay time of 25



s requires 339 clock cycles to be counted and a

TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for

every 25



s period.

Available prescaler modes for version 1.0 (B1h) can be seen in

Section 11

8.8 Power

reduction modes

8.8.1 Hard

power-down

Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current

sinks including the oscillator. All digital input buffers are separated from the input pins and

clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or

LOW level.

8.8.2 Soft

power-down mode

Soft power-down mode is entered immediately after the CommandReg register’s

PowerDown bit is set to logic 1. All internal current sinks are switched off, including the

oscillator buffer. However, the digital input buffers are not separated from the input pins

and keep their functionality. The digital output pins do not change their state.

During soft power-down, all register values, the FIFO buffer content and the configuration

keep their current contents.

After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down

mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately

clear it. It is automatically cleared by the MFRC523 when Soft power-down mode is

exited.

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Remark:

When the internal oscillator is used, time (t

osc

) is required for the oscillator to

become stable. This is because the internal oscillator is supplied by V

DDA

and any clock

cycles will not be detected by the internal logic until V

DDA

is stable. It is recommended for

the serial UAR

o first send the value 55h to the MFRC523. The oscillator must be stable

for further access to the registers.

nsure this, perform a read access to address 0 until

the MFRC523 answers to the last read command with the register content of address 0.

This indicates that the MFRC523 is ready.

8.8.3 Transmitter

Power-down mode

The Transmitter Power-down mode switches off the internal antenna drivers and the RF

field. Transmitter Power-down mode is entered by setting either the TxControlReg

8.9 Oscillator

circuit

MFRC523

OSCOUT

OSCIN

27.12 MHz

001aal162

Fig 22.

Quartz crystal connection

The clock applied to the MFRC523 provides a time basis for the synchronous system’s

encoder and decoder. The stability of the clock frequency is an important factor for correct

operation.

btain optimum performance, clock jitter must be reduced as much as

possible. This is best achieved using the internal oscillator buffer with the recommended

circuitry.

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this

case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock

quality has been verified.

8.10 Reset

and oscillator start-up time

8.10.1 Reset

timing requirements

The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the

digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,

the signal must be LOW for at least 100 ns.

8.10.2 Oscillator

start-up time

If the MFRC523 has been set to a Power-down mode or is powered by a V

DDX

supply, the

start-up time for the MFRC523 depends on the oscillator used and is shown in

Figure 23

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The time (t

startup

) is the start-up time of the crystal oscillator circuit. The crystal oscillator

start-up time is defined by the crystal.

The time (t

) is the internal delay time of the MFRC523 when the clock signal is stable

before the MFRC523 can be addressed.

The delay time is calculated by:

1024



37.74



(8)

————-

The time (t

osc

) is the sum of t

and t

startup

device activation

oscillator

clock stable

clock ready

startup

osc

001aak596

Fig 23.

Oscillator start-up time

9. MFRC523

registers

9.1 Register

bit behavior

Depending on the functionality of a register, the access conditions to the register can vary.

In principle, bits with same behavior are grouped in common registers. The access

conditions are described in

ble 20

Table 20.

Behavior of register bits and their designation

Abbreviation Behavior

Description

R/W

read and write

These bits can be written and read by the microcontroller. Since

they are used only for control purposes, their content is not

influenced by internal state machines, for example the

ComIEnReg register can be written and read by the

microcontroller. It will also be read by internal state machines but

never changed by them.

dynamic

These bits can be written and read by the microcontroller.

Nevertheless, they can also be written automatically by internal

state machines, for example the CommandReg register changes

its value automatically after the execution of the command.

read only

These register bits hold values which are determined by internal

states only, for example the CRCReady bit cannot be written

externally but shows internal states.

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Table 20.

Behavior of register bits and their designation

…continued

Abbreviation Behavior

Description

write only

–

Reading these register bits always returns zero.

reserved

Registers which are indicated as being reserved must not be

changed. However, in the case of a write access, it is

recommended that 0 is always written.

–

Registers which are indicated as being reserved for future use or

are for production tests must not be changed.

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9.1.1 MFRC523

Table 21.

MFRC523 register overview

Subaddress Register

name

(Hex)

Function

Refer to

Page 0: Command and status

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

Reserved

reserved for future use

ble 22 on page 37

CommandReg

ComlEnReg

DivlEnReg

starts and stops command execution

enable and disable interrupt request control bits

interrupt request bits

ble 24 on page 37

ble 26 on page 38

ble 28 on page 38

ble 30 on page 39

ble 32 on page 40

ComIrqReg

DivIrqReg

interrupt request bits

ErrorReg

error bits showing the error status of the last command executed

ble 36 on page 41

Status1Reg

Status2Reg

FIFODataReg

FIFOLevelReg

WaterLevelReg

ControlReg

BitFramingReg

CollReg

communication status bits

ble 36 on page 41

ble 38 on page 42

ble 40 on page 43

ble 42 on page 43

ble 44 on page 44

ble 46 on page 44

ble 48 on page 45

ble 50 on page 45

ble 52 on page 46

receiver and transmitter status bits

input and output of 64 byte FIFO buffer

number of bytes stored in the FIFO buffer

level for FIFO underflow and overflow warning

miscellaneous control registers

adjustments for bit-oriented frames

bit position of the first bit-collision detected on the RF interface

reserved for future use

Reserved

Page 1: Command

Reserved

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

reserved for future use

ble 54 on page 46

ble 56 on page 47

ble 58 on page 48

ble 60 on page 48

ble 62 on page 49

ble 64 on page 50

ble 66 on page 50

ble 68 on page 51

ble 70 on page 52

ble 72 on page 52

ble 74 on page 53

ble 76 on page 53

ble 78 on page 53

ble 80 on page 54

ble 82 on page 54

ble 84 on page 55

ModeReg

defines general modes for transmitting and receiving

defines transmission data rate and framing

defines reception data rate and framing

controls the antenna driver pins TX1 and TX2

controls the setting of the transmission modulation

selects the internal sources for the antenna driver

selects internal receiver settings

TxModeReg

RxModeReg

TxControlReg

TxASKReg

TxSelReg

RxSelReg

RxThresholdReg selects

thresholds for the bit decoder

DemodReg

Reserved

MfTxReg

MfRxReg

TypeBReg

defines demodulator settings

reserved for future use

controls MIFARE communication transmit parameters

controls MIFARE communication receive parameters

controls the ISO/IEC 14443 B functionality

SerialSpeedReg selects

the speed of the serial UART interface

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Table 21.

MFRC523 register overview

…continued

Subaddress Register

name

(Hex)

Function

Refer to

Page 2: Configuration

20h

21h

22h

23h

24h

25h

26h

27h

Reserved

reserved for future use

ble 86 on page 56

CRCResultReg

Reserved

shows the MSB and LSB values of the CRC calculation

reserved for future use

ble 88 on page 56

ble 90 on page 56

ble 92 on page 57

ble 94 on page 57

ble 96 on page 57

ble 98 on page 58

ModWidthReg

Reserved

controls the ModWidth setting

reserved for future use

RFCfgReg

GsNReg

configures the receiver gain

selects the conductance of the antenna driver pins TX1 and TX2

ble 100 on

for modulation

page 58

28h

29h

2Ah

2Bh

CWGsPReg

ModGsPReg

TModeReg

defines the conductance of the p-driver output when not active

ble 102 on

page 59

defines the conductance of the p-driver output during modulation

ble 104 on

page 59

defines settings for the internal timer

ble 106 on

page 59

TPrescalerReg

ble 108 on

page 60

2Ch

2Dh

2Eh

2Fh

TReloadReg

defines the 16-bit timer reload value

ble 110 on page 61

ble 112 on page 61

ble 114 on page 61

ble 116 on page 62

TCounterValReg shows

the 16-bit timer value

TCounterValReg shows

the 16-bit timer value

Page 3: Test register

30h

31h

Reserved

reserved for future use

ble 118 on page 62

stSel1Reg

stSel2Reg

stPinEnReg

general test signal configuration

ble 120 on

page 62

32h

33h

34h

35h

36h

37h

38h

39h

general test signal configuration and PRBS control

enables pin output driver on pins D1 to D7

ble 122 on

page 63

ble 124 on

page 63

stPinValueReg defines

the values for D1 to D7 when it is used as an I/O bus

ble 126 on

page 64

stBusReg

Auto

stReg

VersionReg

shows the status of the internal test bus

controls the digital self-test

ble 128 on

page 64

ble 130 on

page 64

shows the software version

ble 132 on

page 65

Analog

stReg

stDAC1Reg

controls the pins AUX1 and AUX2

defines the test value for

stDAC1

ble 134 on

page 65

ble 136 on

page 67

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Table 21.

MFRC523 register overview

…continued

Subaddress Register

name

(Hex)

Function

Refer to

3Ah

stDAC2Reg

stADCReg

Reserved

defines the test value for

stDAC2

shows the value of ADC I-channel and Q-channel

reserved for production tests

ble 138 on

page 67

3Bh

ble 140 on

page 67

3Ch to 3Fh

ble 142

ble 148 on

page 68

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9.2 Register

descriptions

9.2.1 Page

0: Command and status

9.2.1.1 Reserved

Functionality is reserved for future use.

Table 22.

Reserved register (address 00h); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 23.

Reserved register bit descriptions

Bit Symbol

Value Description

7 to 0

reserved reserved

for future use

–

9.2.1.2 CommandReg

Starts and stops command execution.

Table 24.

CommandReg register (address 01h); reset value: 20h bit allocation

Bit

PowerDown

Symbol:

Access:

–

RcvOff

R/W

Command[3:0]

Table 25.

CommandReg register bit descriptions

Bit Symbol

Value Description

7 to 6

reserved

RcvOff

PowerDown

analog part of the receiver is switched off

Soft Power-down mode entered

MFRC523 starts the wake up procedure during which this bit is

read as a logic 1; it is read as a logic 0 when the MFRC523 is

ready; see

Section 8.8.2 on page 30

Remark:

The PowerDown bit cannot be set when the SoftReset

command is activated

3 to 0

Command[3:0] –

activates a command based on the Command value; reading this

Section 10.3 on

page 69

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9.2.1.3 ComIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 26.

ComIEnReg register (address 02h); reset value: 80h bit allocation

Bit

Symbol

Access

IRqInv

R/W

TxIEn

R/W

RxIEn

R/W

IdleIEn HiAlertIEn

LoAlertIEn ErrIEn TimerIEn

R/W R/W

R/W

Table 27.

ComIEnReg register bit descriptions

Bit Symbol

Value Description

IRqInv

signal on pin IRQ is inverted with respect to the Status1Reg register’s IRq

bit

signal on pin IRQ is equal to the IRq bit; in combination with the

DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures

that the output level on pin IRQ is 3-state

TxIEn

RxIEn

–

allows the transmitter interrupt request (TxIRq bit) to be propagated to pin

IRQ

allows the receiver interrupt request (RxIRq bit) to be propagated to pin

IRQ

IdleIEn

–

allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ

HiAlertIEn

allows the high alert interrupt request (HiAlertIRq bit) to be propagated to

pin IRQ

LoAlertIEn –

allows the low alert interrupt request (LoAlertIRq bit) to be propagated to

pin IRQ

ErrIEn

–

allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ

TimerIEn

allows the timer interrupt request (TimerIRq bit) to be propagated to pin

IRQ

9.2.1.4 DivIEnReg

Control bits to enable and disable the passing of interrupt requests.

Table 28.

DivIEnReg register (address 03h); reset value: 00h bit allocation

Bit

Symbol

Access

IRQPushPull

R/W

reserved

–

MfinActIEn

R/W

reserved

–

CRCIEn

R/W

reserved

–

Table 29.

DivIEnReg register bit descriptions

Bit

Symbol

Value Description

IRQPushPull

–

pin IRQ is a standard CMOS output pin

pin IRQ is an open-drain output pin

reserved for future use

6 to 5

reserved

MfinActIEn

–

allows the MFIN active interrupt request to be propagated to

pin IRQ

reserved

CRCIEn

–

reserved for future use

allows the CRC interrupt request, indicated by the DivIrqReg

1 to 0

reserved

–

reserved for future use

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9.2.1.5 ComIrqReg

Interrupt request bits.

Table 30.

ComIrqReg register (address 04h); reset value: 14h bit allocation

Bit

HiAlertIRq

LoAlertIRq

Symbol

Access

Set1 TxIRq RxIRq IdleIRq

ErrIRq TimerIRq

Table 31.

ComIrqReg register bit descriptions

All bits in the ComIrqReg register are cleared by software.

Bit Symbol

Value Description

Set1

indicates that the marked bits in the ComIrqReg register are set

indicates that the marked bits in the ComIrqReg register are cleared

set immediately after the last bit of the transmitted data was sent out

receiver has detected the end of a valid data stream

TxIRq

RxIRq

if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is

only set to logic 1 when data bytes are available in the FIFO

IdleIRq

if a command terminates, for example, when the CommandReg changes

its value from any command to the Idle command (see

ble 150 on

page 69

)

if an unknown command is started, the CommandReg register

Command[3:0] value changes to the idle state and the IdleIRq bit is set

the microcontroller starting the Idle command does not set the IdleIRq bit

the Status1Reg register’s HiAlert bit is set

HiAlertIRq

LoAlertIRq

the HiAlertIRq bit stores this event and can only be reset as indicated by

the Set1 bit in this register

Status1Reg register’s LoAlert bit is set

the LoAlertIRq bit stores this event and can only be reset as indicated by

the Set1 bit in this register

ErrIRq

any error bit in the ErrorReg register is set

TimerIRq

the timer decrements the timer value in register TCounterValReg to zero

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9.2.1.6 DivIrqReg

Interrupt request bits.

Table 32.

DivIrqReg register (address 05h); reset value: x0h bit allocation

Bit

Symbol

Access

Set2

reserved

MfinActIRq reserved CRCIRq

reserved

–

Table 33.

DivIrqReg register bit descriptions

All bits in the DivIrqReg register are cleared by software.

Bit

Symbol

Value Description

Set2

–

indicates that the marked bits in the DivIrqReg register are set

indicates that the marked bits in the DivIrqReg register are cleared

reserved for future use

6 to 5

reserved

MfinActIRq 1

MFIN is active; this interrupt is set when either a rising or falling signal

edge is detected

reserved

CRCIRq

–

reserved for future use

–

the CalcCRC command is active and all data is processed

reserved for future use

1 to 0

reserved

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9.2.1.7 ErrorReg

Error bit register showing the error status of the last command executed.

Table 34.

ErrorReg register (address 06h); reset value: 00h bit allocation

Bit

Symbol WrErr

mpErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr

Access

–

Table 35.

ErrorReg register bit descriptions

Bit Symbol

Value Description

WrErr

data is written into the FIFO buffer by the host during the MFAuthent

command or if data is written into the FIFO buffer by the host during the

time between sending the last bit on the RF interface and receiving the

last bit on the RF interface

mpErr

[1]

internal temperature sensor detects overheating, in which case the

antenna drivers are automatically switched off

reserved

–

reserved for future use

BufferOvfl

the host or a MFRC523’s internal state machine (e.g. receiver) tries to

write data to the FIFO buffer even though it is already full

CollErr

a bit-collision is detected

cleared automatically at receiver start-up phase

only valid during the bitwise anticollision at 106 kBd

always set to logic 0 during communication protocols at 212 kBd,

424 kBd and 848 kBd

CRCErr

the RxModeReg register’s RxCRCEn bit is set and the CRC calculation

fails

automatically cleared to logic 0 during receiver start-up phase

parity check failed

ParityErr

automatically cleared during receiver start-up phase

only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd

set to logic 1 if the SOF is incorrect

ProtocolErr

automatically cleared during receiver start-up phase

bit is only valid for 106 kBd

during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the

number of bytes received in one data stream is incorrect

[1] Command

execution clears all error bits except the

mpErr bit. Cannot be set by software.

9.2.1.8 Status1Reg

Contains status bits of the CRC, interrupt and FIFO buffer.

Table 36.

Status1Reg register (address 07h); reset value: 21h bit allocation

Bit

Symbol reserved

CRCOk CRCReady

Access

IRq

LoAlert

TRunning reserved

HiAlert

–

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Table 37.

Status1Reg register bit descriptions

Bit Symbol

Value Description

reserved

CRCOk

–

reserved for future use

the CRC result is zero

the CRCOk bit is undefined for data transmission and reception: use

the ErrorReg register’s CRCErr bit

indicates the status of the CRC coprocessor, during calculation the

value changes to logic 0, when the calculation is done correctly the

value changes to logic 1

CRCReady

IRq

–

the CRC calculation has finished; only valid for the CRC coprocessor

calculation using the CalcCRC command

indicates if any interrupt source requests attention with respect to the

setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg

registers

TRunning

MFRC523’s timer unit is running, i.e. the timer will decrement the

TCounterValReg register with the next timer clock

Remark:

in gated mode, the TRunning bit is set to logic 1 when the

timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not

influenced by the gated signal

reserved

HiAlert

–

reserved for future use

the alert level for the number of bytes in the FIFO buffer

(FIFOLength[6:0]) is:

HiAlert



–

FIFOLength

 

WaterLevel

otherwise value = logic 0

Example:

FIFOLength = 60, WaterLevel = 4 then HiAlert = logic 1

FIFOLength = 59, WaterLevel = 4 then HiAlert = logic 0

LoAlert

the alert level for number of bytes in the FIFO buffer (FIFOLength[6:0])

is:

LoAlert

FIFOLength



WaterLevel

otherwise value = logic 0

Example:

FIFOLength = 4, WaterLevel = 4 then LoAlert = logic 1

FIFOLength = 5, WaterLevel = 4 then LoAlert = logic 0

9.2.1.9 Status2Reg

Contains status bits of the receiver, transmitter and data mode detector.

Table 38.

Status2Reg register (address 08h); reset value: 00h bit allocation

Bit

Symbol

mpSensClear

CForceHS

Access R/W

R/W

reserved

–

MFCrypto1On

ModemState[2:0]

Table 39.

Status2Reg register bit descriptions

Bit

Symbol

Value Description

mpSensClear

clears the temperature error if the temperature is below the

alarm limit of 125



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Table 39.

Status2Reg register bit descriptions

…continued

Bit

Symbol

Value Description

CForceHS

C-bus input filter settings:

the I

C-bus input filter is set to the High-speed mode

independent of the I

C-bus protocol

–

the I

C-bus input filter is set to the I

C-bus protocol used

5 to 4

reserved

MFCrypto1On

–

indicates that the MIFARE Crypto1 unit is switched on and

all data communication with the card is encrypted; this bit is

cleared by software; can only be set to logic 1 by a

successful execution of the MFAuthent command only valid

in Read/Write mode for MIFARE standard cards

2 to 0

ModemState[2:0]

–

shows the state of the transmitter and receiver state

machines:

000

001

010

idle

wait for the BitFramingReg register’s StartSend bit

TxWait: wait until RF field is present if the TModeReg

time for TxWait is defined by the TxWaitReg register

011

100

transmitting

RxWait: wait until RF field is present if the TModeReg

time for RxWait is defined by the RxWaitReg register

101

110

wait for data

receiving

9.2.1.10 FIFODataReg

Input and output of 64 byte FIFO buffer.

Table 40.

FIFODataReg register (address 09h); reset value: xxh bit allocation

Bit

Symbol

Access

FIFOData[7:0]

Table 41.

FIFODataReg register bit descriptions

Bit

Symbol

Description

7 to 0

FIFOData[7:0] data

input and output port for the internal 64-byte FIFO buffer. FIFO

buffer acts as parallel in/parallel out converter for all serial data stream

inputs and outputs

9.2.1.11 FIFOLevelReg

Indicates the number of bytes stored in the FIFO.

Table 42.

FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation

Bit

Symbol FlushBuffer

Access

FIFOLevel[6:0]

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Table 43.

FIFOLevelReg register bit descriptions

Bit

Symbol

Value Description

FlushBuffer

immediately clears the internal FIFO buffer’s read and write

pointer and ErrorReg register’s BufferOvfl bit. Reading this bit

always returns 0

6 to 0

FIFOLevel[6:0]

–

indicates the number of bytes stored in the FIFO buffer. Writing to

the FIFODataReg register increments and reading decrements

the FIFOLevel value

9.2.1.12 WaterLevelReg

Defines the level for FIFO under- and overflow warning.

Table 44.

WaterLevelReg register (address 0Bh); reset value: 08h bit allocation

Bit

Symbol

Access

reserved

–

WaterLevel[5:0]

R/W

Table 45.

WaterLevelReg register bit descriptions

Bit

Symbol

Description

7 to 6

reserved

reserved for future use

5 to 0

WaterLevel[5:0] defines

a warning level to indicate a FIFO buffer overflow or underflow:

Status1Reg register’s HiAlert bit is set to logic 1 if the remaining

number of bytes in the FIFO buffer space is equal to, or less than the

defined number of WaterLevel[5:0] bits

Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less

than the WaterLevel[5:0] bits in the FIFO buffer

Remark:

to calculate values for HiAlert and LoAlert, see

Section 9.2.1.9 on page 42

9.2.1.13 ControlReg

Miscellaneous control bits.

Table 46.

ControlReg register (address 0Ch); reset value: 10h bit allocation

Bit

Symbol TStopNow

TStartNow

Access

reserved

–

RxLastBits[2:0]

Table 47.

ControlReg register bit descriptions

Bit

Symbol

Value Description

TStopNow

TStartNow

–

timer stops immediately

timer starts immediately. Reading this bit always returns it to 0

reserved for future use

5 to 3

reserved

2 to 0

RxLastBits[2:0]

–

indicates the number of valid bits in the last received byte. If this

value is zero, the whole byte is valid

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9.2.1.14 BitFramingReg

Adjustments for bit-oriented frames.

Table 48.

BitFramingReg register (address 0Dh); reset value: 00h bit allocation

Bit

Symbol StartSend

Access

RxAlign[2:0]

R/W

reserved

–

TxLastBits[2:0]

R/W

Table 49.

BitFramingReg register bit descriptions

Bit

Symbol

Value Description

StartSend

starts the transmission of data

only valid in combination with the Transceive command

6 to 4

RxAlign[2:0]

used for reception of bit-oriented frames: defines the bit

position for the first bit received to be stored in the FIFO buffer

example:

LSB of the received bit is stored at bit position 0, the second

received bit is stored at bit position 1

LSB of the received bit is stored at bit position 1, the second

received bit is stored at bit position 2

LSB of the received bit is stored at bit position 7, the second

received bit is stored in the next byte that follows at bit

position 0

These bits are only to be used for bitwise anticollision at

106 kBd, for all other modes they are set to 0

reserved

–

reserved for future use

2 to 0

TxLastBits[2:0]

used for transmission of bit oriented frames: defines the

number of bits of the last byte that will be transmitted. 000b

indicates that all bits of the last byte will be transmitted

9.2.1.15 CollReg

Defines the first bit-collision detected on the RF interface.

Table 50.

CollReg register (address 0Eh); reset value: xxh bit allocation

Bit

Symbol ValuesAfterColl

reserved CollPosNotValid

Access R/W

CollPos[4:0]

–

Table 51.

CollReg register bit descriptions

Bit

Symbol

Value Description

ValuesAfterColl

all received bits will be cleared after a collision

only used during bitwise anticollision at 106 kBd,

otherwise it is set to logic 1

reserved

–

reserved for future use

CollPosNotValid

no collision detected or the position of the collision is

out of the range of CollPos[4:0]

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Table 51.

CollReg register bit descriptions

…continued

Bit Symbol

Value Description

4 to 0

CollPos[4:0]

–

shows the bit position of the first detected collision in a

received frame

only data bits are interpreted

example:

00h

01h

08h

indicates a bit-collision in the 32

bit

indicates a bit-collision in the 1

bit

indicates a bit-collision in the 8

bit

these bits will only be interpreted if the

CollPosNotValid bit is set to logic 0

9.2.1.16 Reserved

Functionality is reserved for future use.

Table 52.

Reserved register (address 0Fh); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 53.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.2 Page

1: Communication

9.2.2.1 Reserved

Functionality is reserved for future use.

Table 54.

Reserved register (address 10h); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 55.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

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9.2.2.2 ModeReg

Defines general mode settings for transmitting and receiving.

Table 56.

ModeReg register (address 11h); reset value: 3Fh bit allocation

Bit

Symbol MSBFirst

reserved TxWaitRF reserved PolMFin reserved

Access R/W

R/W R/W

CRCPreset[1:0]

R/W

–

Table 57.

ModeReg register bit descriptions

Bit

Symbol

Value Description

MSBFirst

CRC coprocessor calculates the CRC with MSB first. In the

CRCResultReg register the values for the CRCResultMSB[7:0]

bits and the CRCResultLSB[7:0] bits are bit reversed

Remark:

during RF communication this bit is ignored

reserved for future use

reserved

TxWaitRF

reserved

PolMFin

–

transmitter can only be started if an RF field is generated

reserved for future use

defines the polarity of pin MFIN

Remark:

the internal envelope signal is encoded active LOW,

changing this bit generates a MFinActIRq event

–

polarity of pin MFIN is active HIGH

polarity of pin MFIN is active LOW

reserved for future use

reserved

1 to 0

CRCPreset

[1:0]

defines the preset value for the CRC coprocessor for the CalcCRC

command

Remark:

during any communication, the preset values are

selected automatically according to the definition of bits in the

RxModeReg and TxModeReg registers

0000h

6363h

A671h

FFFFh

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9.2.2.3 TxModeReg

Defines the data rate during transmission.

Table 58.

TxModeReg register (address 12h); reset value: 00h bit allocation

Bit

Symbol TxCRCEn

Access R/W

TxSpeed[2:0]

TxFraming

InvMod

R/W

Table 59.

TxModeReg register bit descriptions

Bit

Symbol

Value

Description

TxCRCEn

enables CRC generation during data transmission

Remark:

can only be set to logic 0 at 106 kBd

defines the bit rate during data transmission

6 to 4

TxSpeed[2:0]

the MFRC523 handles transfer speeds up to

848 kBd

000

001

010

011

100

101

110

111

106 kBd

212 kBd

424 kBd

848 kBd

reserved

InvMod

modulation of transmitted data is inverted

defines the framing used for data transmission

ISO/IEC 14443 A/MIFARE

reserved

2 to 0

TxFraming[1:0]

reserved

ISO/IEC 14443 B

9.2.2.4 RxModeReg

Defines the data rate during reception.

Table 60.

RxModeReg register (address 13h); reset value: 00h bit allocation

Bit

Symbol RxCRCEn

Access R/W

RxSpeed[2:0]

RxNoErr RxMultiple

R/W R/W

RxFraming

Table 61.

RxModeReg register bit descriptions

Bit

Symbol

Value Description

RxCRCEn

enables the CRC calculation during reception

Remark:

can only be set to logic 0 at 106 kBd

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Table 61.

RxModeReg register bit descriptions

…continued

Bit Symbol

Value Description

6 to 4

RxSpeed[2:0]

defines the bit rate while receiving data. The MFRC523

manages transfer speeds up to 848 kBd

000

001

010

011

100

101

110

111

106 kBd

212 kBd

424 kBd

848 kBd

reserved

RxNoErr

an invalid received data stream (less than 4 bits received) will

be ignored and the receiver remains active

RxMultiple

receiver is deactivated after receiving a data frame

able to receive more than one data frame

only valid for data rates above 106 kBd in order to handle the

polling command

after setting this bit, the Receive and Transceive commands will

not terminate automatically. Multiple reception can only be

deactivated by writing any command (except the Receive

command) to the CommandReg register, or by the host clearing

the bit

if set to logic 1, an error byte is added to the FIFO buffer at the

end of a received data stream which is a copy of the ErrorReg

For version 1.0 please see

Section 11

defines the expected framing for data reception

ISO/IEC 14443 A/MIFARE

reserved

1 to 0

RxFraming

reserved

ISO/IEC 14443 B

9.2.2.5 TxControlReg

Controls the logical behavior of the antenna driver pins TX1 and TX2.

Table 62.

TxControlReg register (address 14h); reset value: 80h bit allocation

Bit

Symbol InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn

Off

Access

R/W

–

R/W

Table 63.

TxControlReg register bit descriptions

Bit Symbol

Value Description

InvTx2RFOn 1

output signal on pin TX2 inverted when driver TX2 is enabled

output signal on pin TX1 inverted when driver TX1 is enabled

output signal on pin TX2 inverted when driver TX2 is disabled

InvTx1RFOn 1

InvTx2RFOff 1

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Table 63.

TxControlReg register bit descriptions

…continued

Bit Symbol

Value Description

InvTx1RFOff 1

output signal on pin TX1 inverted when driver TX1 is disabled

Tx2CW

output signal on pin TX2 continuously delivers the unmodulated

13.56 MHz energy carrier

–

Tx2CW bit is enabled to modulate the 13.56 MHz energy carrier

reserved for future use

reserved

Tx2RFEn

output signal on pin TX2 delivers the 13.56 MHz energy carrier

modulated by the transmission data

Tx1RFEn

output signal on pin TX1 delivers the 13.56 MHz energy carrier

modulated by the transmission data

9.2.2.6 TxASKReg

Controls transmit modulation settings.

Table 64.

TxASKReg register (address 15h); reset value: 00h bit allocation

Bit

Symbol reserved

Force100ASK

Access R/W

reserved

–

Table 65.

TxASKReg register bit descriptions

Bit

Symbol

Value Description

– reserved

for future use

reserved

Force100ASK 1

forces 100 % ASK modulation independently of the ModGsPReg

5 to 0

reserved

–

reserved for future use

9.2.2.7 TxSelReg

Selects the internal sources for the analog module.

Table 66.

TxSelReg register (address 16h); reset value: 10h bit allocation

Bit

Symbol:

Access:

reserved

–

DriverSel[1:0]

R/W

MFOutSel[3:0]

R/W

Table 67.

TxSelReg register bit descriptions

Bit Symbol

Value Description

7 to 6

reserved

–

reserved for future use

5 to 4

DriverSel[1:0]

–

selects the input of drivers TX1 and TX2

3-state; in soft power-down the drivers are only in 3-state

mode if the DriverSel[1:0] value is set to 3-state mode

modulation signal (envelope) from the internal encoder, Miller

pulse encoded

modulation signal (envelope) from pin MFIN

HIGH; the HIGH level depends on the setting of bits

InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff

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Table 67.

TxSelReg register bit descriptions

…continued

Bit Symbol

Value Description

selects the input for pin MFOUT

3-state

3 to 0

MFOutSel[3:0]

0000

0001

0010

0011

LOW

HIGH

test bus signal as defined by the

stSel1Reg register’s

tBusBitSel[2:0] value

0100

0101

modulation signal (envelope) from the internal encoder, Miller

pulse encoded

serial data stream to be transmitted, data stream before Miller

encoder

0110

0111

reserved

serial data stream received, data stream after Manchester

decoder

1000

reserved

1111

9.2.2.8 RxSelReg

Selects internal receiver settings.

Table 68.

RxSelReg register (address 17h); reset value: 84h bit allocation

Bit

Symbol

Access

UARTSel[1:0]

R/W

RxWait[5:0]

R/W

Table 69.

RxSelReg register bit descriptions

Bit Symbol

Value Description

7 to 6

UARTSel[1:0]

selects the input of the contactless UART

constant LOW

Manchester with subcarrier from pin MFIN

modulated signal from the internal analog module, default

NRZ coding without subcarrier from pin MFIN which is only

valid for transfer speeds above 106 kBd

5 to 0

RxWait[5:0]

–

after data transmission the activation of the receiver is delayed

for RxWait bit-clocks, during this ‘frame guard time’ any signal on

pin RX is ignored

this parameter is ignored by the Receive command

all other commands, such as Transceive, MFAuthent use this

parameter

the counter starts immediately after the external RF field is

switched on

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9.2.2.9 RxThresholdReg

Selects thresholds for the bit decoder.

Table 70.

RxThresholdReg register (address 18h); reset value: 84h bit allocation

Bit

Symbol

Access

MinLevel[3:0]

R/W

reserved

–

CollLevel[2:0]

R/W

Table 71.

RxThresholdReg register bit descriptions

Bit

Symbol

Description

7 to 4

MinLevel[3:0]

defines the minimum signal strength at the decoder input that will be

accepted. If the signal strength is below this level it is not evaluated

reserved

reserved for future use

2 to 0

CollLevel[2:0] defines

the minimum signal strength at the decoder input that must be

reached by the weaker half-bit of the Manchester encoded signal to

generate a bit-collision relative to the amplitude of the stronger half-bit

9.2.2.10 DemodReg

Defines demodulator settings.

Table 72.

DemodReg register (address 19h); reset value: 4Dh bit allocation

Bit

Symbol

AddIQ[1:0]

FixIQ

TPrescal

Even

uRcv[1:0]

uSync[1:0]

Access

R/W

–

R/W

Table 73.

DemodReg register bit descriptions

Bit Symbol

Value Description

7 to 6

AddIQ[1:0]

–

defines the use of I-channel and Q-channel during reception

Remark:

the FixIQ bit must be set to logic 0 to enable the

following settings:

selects the stronger channel

selects the stronger channel and freezes the selected channel

during communication

reserved

FixIQ

if the bits of AddIQ are set to X0, the reception is fixed to

I-channel

if the bits of AddIQ are set to X1, the reception is fixed to

Q-channel

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Table 73.

DemodReg register bit descriptions

…continued

Bit

Symbol

Value Description

TPrescalEven 0

the following formula is used to calculate f

Timer

of the prescaler:

Timer

= 13.56 MHz / (2 * TPreScaler + 1).

the following formula is used to calculate f

Timer

of the prescaler:

Timer

= 13.56 MHz / (2 * TPreScaler + 2).

(Default TPrescalEven is logic 0)

This cannot be used in version, see

Section 11 “Errata sheet”

3 to 2

uRcv[1:0]

1 to 0

uSync[1:0]

–

changes the time-constant of the internal PLL during data

reception

Remark:

if set to 00b the PLL is frozen during data reception

changes the time constant of the internal PLL during burst

9.2.2.11 Reserved

Functionality is reserved for future use.

Table 74.

Reserved register (address 1Ah); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 75.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.2.12 Reserved

Functionality is reserved for future use.

Table 76.

Reserved register (address 1Bh); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 77.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.2.13 MfTxReg

Controls some MIFARE communication transmit parameters.

Table 78.

MfTxReg register (address 1Ch); reset value: 62h bit allocation

Bit

Symbol

Access

reserved

–

TxWait[1:0]

R/W

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Table 79.

MfTxReg register bit descriptions

Bit

Symbol

reserved

TxWait

Description

7 to 2

1 to 0

reserved for future use

defines the additional response time. 7 bits are added to the value of

the register bit by default

9.2.2.14 MfRxReg

Table 80.

MfRxReg register (address 1Dh); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

ParityDisable

R/W

reserved

–

Table 81.

MfRxReg register bit descriptions

Bit Symbol

Value Description

7 to 5

reserved reserved

for future use

ParityDisable 1

–

generation of the parity bit for transmission and the parity check for

receiving is switched off. The received parity bit is handled like a

data bit

3 to 0

reserved

–

reserved for future use

9.2.2.15 TypeBReg

Configures the ISO/IEC 14443 B functionality.

Table 82.

TypeBReg register (address 1Eh); reset value: 00h bit allocation

Bit

Symbol RxSOFReq

RxEOFReq reserved EOFSOF NoTxSOF NoTxEOF

Width

TxEGT[1:0]

Access

R/W

–

R/W

Table 83.

TypeBReg register bit descriptions

Bit

Symbol

Value Description

RxSOFReq

requires SOF; a datastream starting without SOF is ignored

accepts a datastream starting with or without SOF; an SOF is

removed and not written into the FIFO

RxEOFReq

reserved

–

requires EOF; a datastream ending without EOF generates a

protocol error

accepts a datastream ending with or without EOF; an EOF is

removed and not written into the FIFO

reserved for future use

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Table 83.

TypeBReg register bit descriptions

…continued

Bit

Symbol

Value Description

EOFSOFWidth

if this bit is set to logic 1 and EOFSOFAdjust bit (Auto

stReg

length defined in ISO/IEC 14443 B.

if this bit is set to logic 1 and the EOFSOFAadjust bit is logic 1:

then

SOF low = (11 ETU



8 cycles) / f

clk

SOF high = (2 ETU + 8 cycles) / f

clk

EOF low = (11 ETU



8 cycles) / f

clk

if this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF

and EOF will have the minimum length defined in

ISO/IEC 14443 B.

if this bit is set to logic 0 and the EOFSOFAdjust bit is logic 1

results in an incorrect system behavior in respect to ISO

specification

NoTxSOF

NoTxEOF

SOF is suppressed

EOF is suppressed

defines EGT bit length

no bits

1 to 0

TxEGT

1 bit

2 bits

3 bits

For the available configuration on version 1.0, please see

Section 11

9.2.2.16 SerialSpeedReg

Selects the speed of the serial UART interface.

Table 84.

SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation

Bit

Symbol

Access

BR_T0[2:0]

R/W

BR_T1[4:0]

R/W

Table 85.

SerialSpeedReg register bit descriptions

Bit

Symbol

Description

7 to 5

BR_T0[2:0]

factor BR_T0 adjusts the transfer speed: for description, see

Section 8.3.3.2 on page 12

4 to 0

BR_T1[4:0]

factor BR_T1 adjusts the transfer speed: for description, see

Section 8.3.3.2 on page 12

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9.2.3 Page

2: Configuration

9.2.3.1 Reserved

Functionality is reserved for future use.

Table 86.

Reserved register (address 20h); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 87.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.3.2 CRCResultReg

registers

Shows the MSB and LSB values of the CRC calculation.

Remark:

The CRC is split into two 8-bit registers.

Table 88.

CRCResultReg (higher bits) register (address 21h); reset value: FFh bit allocation

Bit

Symbol

Access

CRCResultMSB[7:0]

Table 89.

CRCResultReg register higher bit descriptions

Bit

Symbol

Description

7 to 0

CRCResultMSB[7:0] shows

the value of the CRCResultReg register’s most

significant byte. Only valid if Status1Reg register’s CRCReady

bit is set to logic 1

Table 90.

CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation

Bit

Symbol

Access

CRCResultLSB[7:0]

Table 91.

CRCResultReg register lower bit descriptions

Bit Symbol

Description

7 to 0

CRCResultLSB[7:0] shows

the value of the least significant byte of the CRCResultReg

logic 1

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9.2.3.3 Reserved

Functionality is reserved for future use.

Table 92.

Reserved register (address 23h); reset value: 88h bit allocation

Bit

Symbol

Access

reserved

–

Table 93.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.3.4 ModWidthReg

Sets the modulation width.

Table 94.

ModWidthReg register (address 24h); reset value: 26h bit allocation

Bit

Symbol

Access

ModWidth[7:0]

R/W

Table 95.

ModWidthReg register bit descriptions

Bit

Symbol

Description

7 to 0

ModWidth[7:0] defines

the width of the Miller modulation as multiples of the carrier

frequency (ModWidth + 1 / f

clk

). The maximum value is half the bit

period

9.2.3.5 Reserved

Functionality is reserved for future use.

Table 96.

Reserved register (address 25h); reset value: 87h bit allocation

Bit

Symbol

Access

reserved

–

Table 97.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

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9.2.3.6 RFCfgReg

Configures the receiver gain.

Table 98.

RFCfgReg register (address 26h); reset value: 48h bit allocation

Bit

Symbol reserved

Access

RxGain[2:0]

R/W

reserved

–

Table 99.

RFCfgReg register bit descriptions

Bit

Symbol

Value

Description

reserved

RxGain[2:0]

–

reserved for future use

6 to 4

defines the receiver’s signal voltage gain factor:

000

001

010

011

100

101

110

111

–

18 dB

23 dB

18 dB

23 dB

33 dB

38 dB

43 dB

48 dB

3 to 0

reserved

reserved for future use

9.2.3.7 GsNReg

Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the

driver is switched on.

Table 100.

GsNReg register (address 27h); reset value: 88h bit allocation

Bit

Symbol

Access

CWGsN[3:0]

R/W

ModGsN[3:0]

R/W

Table 101.

GsNReg register bit descriptions

Bit

Symbol

Description

7 to 4

CWGsN[3:0] defines

the conductance of the output n-driver during periods without

modulation which can be used to regulate the output power and

subsequently current consumption and operating distance. The value is

only used if driver TX1 or TX2 is switched on

during Soft power-down mode the highest bit is forced to logic 1

Remark:

the conductance value is binary-weighted

3 to 0

ModGsN[3:0] defines

the conductance of the output n-driver during periods without

modulation which can be used to regulate the modulation index. The

value is only used if driver TX1 or TX2 is switched on

during Soft power-down mode the highest bit is forced to logic 1

Remark:

the conductance value is binary weighted

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9.2.3.8 CWGsPReg

Defines the conductance of the p-driver output during periods of no modulation.

Table 102.

CWGsPReg register (address 28h); reset value: 20h bit allocation

Bit

Symbol

Access

reserved

–

CWGsP[5:0]

R/W

Table 103.

CWGsPReg register bit descriptions

Bit

Symbol

Description

7 to 6

5 to 0

reserved

reserved for future use

CWGsP[5:0]

defines the conductance of the p-driver output which can be used to

regulate the output power and subsequently current consumption and

operating distance

during Soft power-down mode the highest bit is forced to logic 1

Remark:

the conductance value is binary weighted

9.2.3.9 ModGsPReg

Defines the conductance of the p-driver output during modulation.

Table 104.

ModGsPReg register (address 29h); reset value: 20h bit allocation

Bit

Symbol

Access

reserved

–

ModGsP[5:0]

R/W

Table 105.

ModGsPReg register bit descriptions

Bit

Symbol

Description

7 to 6

5 to 0

reserved

reserved for future use

ModGsP[5:0] defines

the conductance of the p-driver output during modulation

which can be used to regulate the modulation index. If the TxASKReg

no effect

during Soft power-down mode the highest bit is forced to logic 1

Remark:

the conductance value is binary weighted

9.2.3.10 TModeReg

and TPrescalerReg registers

These registers define the timer settings.

Remark:

The TPrescaler setting higher 4 bits are in the TModeReg register and the lower

8 bits are in the TPrescalerReg register.

Table 106.

TModeReg register (address 2Ah); reset value: 00h bit allocation

Bit

Symbol

Access

TAuto

R/W

TGated[1:0]

R/W

TAutoRestart

R/W

TPrescaler_Hi[3:0]

R/W

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Table 107.

TModeReg register bit descriptions

Bit

Symbol

Value Description

TAuto

the timer starts automatically at the end of the transmission in

all communication modes at all speeds or when InvTxnRFOn

bits are set to logic 1 and the RF field is switched on

when RxMultiple bit in register RxModeReg is logic 0: in

MIFARE mode and ISO/IEC 14443 B at 106 kBd, the timer

stops after the 5

bit (1 start bit, 4 data bits). In all other

modes, the timer stops after the 4

bit

if the RxMultiple bit is set to logic 1, the timer never stops. In

this case the timer can be stopped by setting the TStopNow

bit in register ControlReg to logic 1

indicates that the timer is not influenced by the protocol

internal timer is runs in gated or non-gated mode

6 to 5

TGated[1:0]

Remark:

in gated mode, the Status1Reg register’s TRunning

bit is logic 1 when the timer is enabled by the TModeReg

these bits do not influence the gating signal

non-gated mode

gated by pin MFIN

gated by pin AUX1

–

TAutoRestart

timer automatically restarts its count-down from the 16-bit

timer reload value instead of counting down to zero

timer decrements to 0 and the ComIrqReg register’s

TimerIRq bit is set to logic 1

3 to 0

TPrescaler_Hi[3:0] –

defines the higher 4 bits of the TPrescaler value

the following formula is used to calculate f

Timer

TPrescalEven bit in Demod Reg is set to logic 0:

Timer

= 13.56 MHz / (2 * TPreScaler + 1).

where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]

(TPrescaler value on 12 bits). The default TPrescalEven is

logic 0

the following formula is used to calculate f

Timer

TPrescalEven bit in Demod Reg is set to logic 1:

Timer

= 13.56 MHz / (2 * TPreScaler + 2); see

Section 8.7

“Timer unit”

For the value applicable for version 1.0, see

Section 11

Table 108.

TPrescalerReg register (address 2Bh); reset value: 00h bit allocation

Bit

Symbol

Access

TPrescaler_Lo[7:0]

R/W

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Table 109.

TPrescalerReg register bit descriptions

Bit

Symbol

TPrescaler_Lo[7:0] defines

the lower 8 bits of the TPrescaler value

the following formula is used to calculate f

Timer

if TPrescalEven bit in

Description

7 to 0

Demot Reg is set to logic 0:

Timer

= 13.56 MHz / (2 * TPreScaler + 1)

where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler

value on 12 bits). The default TPrescalEven is logic 0;

Timer

= 13.56 MHz / (2 * TPreScaler + 2); see

Section 8.7 “Timer

unit”

The value applicable for version 1.0 can be seen at

Section 11

9.2.3.11 TReloadReg

Defines the 16-bit timer reload value.

Remark:

The reload value bits are contained in two 8-bit registers.

Table 110.

TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation

Bit

Symbol

Access

TReloadVal_Hi[7:0]

R/W

Table 111.

TReloadReg register higher bit descriptions

Bit

Symbol

Description

7 to 0

TReloadVal_Hi[7:0]

defines the higher 8 bits of the 16-bit timer reload value. On a

start event, the timer loads the timer reload value. Changing

this register affects the timer only at the next start event

Table 112.

TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation

Bit

Symbol

Access

TReloadVal_Lo[7:0]

R/W

Table 113.

TReloadReg register lower bit descriptions

Bit

Symbol

Description

7 to 0

TReloadVal_Lo[7:0] defines

the lower 8 bits of the 16-bit timer reload value. On a

start event, the timer loads the timer reload value. Changing this

9.2.3.12 TCounterValReg

Contains the timer value.

Remark:

The timer value bits are contained in two 8-bit registers.

Table 114.

TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit

allocation

Bit

Symbol

Access

TCounterVal_Hi[7:0]

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Table 115.

TCounterValReg register higher bit descriptions

Bit

Symbol

Description

7 to 0

TCounterVal_Hi[7:0] timer

value higher 8 bits

Table 116.

TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit

allocation

Bit

Symbol

Access

TCounterVal_Lo[7:0]

Table 117.

TCounterValReg register lower bit descriptions

Bit

Symbol

Description

7 to 0

TCounterVal_Lo[7:0] timer

value lower 8 bits

9.2.4 Page

3: Test

9.2.4.1 Reserved

Functionality is reserved for future use.

Table 118.

Reserved register (address 30h); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 119.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for future use

7 to 0

reserved

9.2.4.2 TestSel1Reg

General test signal configuration.

Table 120.

TestSel1Reg register (address 31h); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

tBusBitSel[2:0]

R/W

Table 121.

TestSel1Reg register bit descriptions

Bit

Symbol

Description

7 to 3

2 to 0

reserved

reserved for future use

tBusBitSel[2:0] selects

a test bus signal which is output at pin MFOU

AnalogSelAux2[3:0] = FFh in Analog

stReg register, test bus

signal is also output at pins AUX1 or AUX2

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9.2.4.3 TestSel2Reg

General test signal configuration and PRBS control.

Table 122.

TestSel2Reg register (address 32h); reset value: 00h bit allocation

Bit

Symbol

tBusFlip

Access R/W

PRBS9 PRBS15

R/W R/W

stBusSel[4:0]

R/W

Table 123.

TestSel2Reg register bit descriptions

Bit

Symbol

Value Description

tBusFlip

test bus is mapped to the parallel port in the following order:

tBusBit4,

tBusBit3,

tBusBit2,

tBusBit6,

tBusBit5,

tBusBit0; see

Section 17.1 on page 82

PRBS9

–

starts and enables the PRBS9 sequence according to

ITU-TO150; the data transmission of the defined sequence is

started by the Transmit command

Remark:

all relevant registers to transmit data must be

configured before entering PRBS9 mode

PRBS15

–

starts and enables the PRBS15 sequence according to

ITU-TO150; the data transmission of the defined sequence is

started by the Transmit command

Remark:

all relevant registers to transmit data must be

configured before entering PRBS15 mode

4 to 0

stBusSel[4:0]

selects the test bus; see

Section 17.1 “

st signals” on page 82

9.2.4.4 TestPinEnReg

Enables the test bus pin output driver.

Table 124.

TestPinEnReg register (address 33h); reset value: 80h bit allocation

Bit

Symbol RS232LineEn

Access R/W

stPinEn[5:0]

R/W

reserved

–

Table 125.

TestPinEnReg register bit descriptions

Bit

Symbol

Value Description

RS232LineEn

–

serial UART lines MX and DTRQ are disabled

6 to 1

stPinEn[5:0]

enables the output driver on one of the data pins D1 to D7 which

outputs a test signal

Example:

setting bit 1 to logic 1 enables pin D1 output

setting bit 5 to logic 1 enables pin D5 output

Remark:

If the SPI is used, only pins D1 to D4 can be used. If the

serial UART interface is used and the RS232LineEn bit is set to

logic 1 only pins D1 to D4 can be used.

reserved

–

reserved for future use

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9.2.4.5 TestPinValueReg

Defines the high and low values for the test port D1 to D7 when it is used as I/O.

Table 126.

TestPinValueReg register (address 34h); reset value: 00h bit allocation

Bit

Symbol

Access

UseIO

R/W

stPinValue[5:0]

R/W

reserved

–

Table 127.

TestPinValueReg register bit descriptions

Bit

Symbol

Value Description

UseIO

enables the I/O functionality for the test port when one of the

serial interfaces is used. The input/output behavior is defined

by value

stPinEn[5:0] in the

stPinEnReg register

6 to 1

stPinValue[5:0]

–

defines the value of the test port when it is used as I/O and

each output must be enabled by

stPinEn[5:0] in the

stPinEnReg register

Remark:

Reading the register indicates the status of pins D6

to D1 if the UseIO bit is set to logic 1. If the UseIO bit is set to

logic 0, the value of the

stPinValueReg register is read back.

reserved

–

reserved for future use

9.2.4.6 TestBusReg

Shows the status of the internal test bus.

Table 128.

TestBusReg register (address 35h); reset value: xxh bit allocation

Bit

Symbol

Access

stBus[7:0]

Table 129.

TestBusReg register bit descriptions

Bit

Symbol

Description

7 to 0

stBus[7:0]

shows the status of the internal test bus. The test bus is selected using

the

stSel2Reg register; see

Section 17.1 on page 82

9.2.4.7 AutoTestReg

Controls the digital self-test.

Table 130.

AutoTestReg register (address 36h); reset value: 40h bit allocation

Bit

Symbol reserved

AmpRcv reserved EOFSOF

Adjust

Self

st[3:0]

Access

–

R/W

–

R/W

For the configuration on version 1.0, please see

Section 11

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Table 131.

AutoTestReg register bit descriptions

Bit

Symbol

reserved

AmpRcv

Value Description

–

reserved for production tests

internal signal processing in the receiver chain is performed

non-linearly which increases the operating distance in

communication modes at 106 kBd

Remark:

due to non-linearity, the effect of the RxThresholdReg

non-linear

reserved

–

reserved for production tests

EOFSOFAdjust

If set to logic 0 and the EOFSOFwidth bit is set to logic 1 it

results in the maximum length of SOF and EOF according to

ISO/IEC 14443 B

If set to logic 0 and the EOFSOFwidth bit is set to logic 0 it

results in the minimum length of SOF and EOF according to

ISO/IEC 14443 B

–

If this bit is set to logic 1 and the EOFSOFwidth bit is logic 1, it

results in

SOF high = (2 ETU + 8 cycles) / f

clk

SOF low = (11 ETU



8 cycles) / f

clk

EOF low = (11 ETU



8 cycles) / f

clk

3 to 0

Self

st[3:0]

enables the digital self-test. The self-test can also be started by

the CalcCRC command; see

Section 10.3.1.4 “CalcCRC

command” on page 70

. Self-test is enabled by 1001b.

Remark:

for default operation the self-test must be disabled

by 0000b

9.2.4.8 VersionReg

Shows the MFRC523 software version.

Table 132.

VersionReg register (address 37h); reset value: xxh bit allocation

Bit

Symbol

Access

Version[7:0]

Table 133.

VersionReg register bit descriptions

Bit

Symbol

Description

7 to 0

Version[7:0]

indicates current MFRC523 software version. The value for the version

1.0 is B1h (see

Section 11

) and the value for the version 2.0 is B2h.

9.2.4.9 AnalogTestReg

Determines the analog output test signal at, and status of, pins AUX1 and AUX2.

Table 134.

AnalogTestReg register (address 38h); reset value: 00h bit allocation

Bit

Symbol

Access

AnalogSelAux1[3:0]

R/W

AnalogSelAux2[3:0]

R/W

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Table 135.

AnalogTestReg register bit descriptions

Bit Symbol

Value Description

7 to 4

AnalogSelAux1[3:0] controls

pin AUX1

3-state

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

output of

stDAC1 (AUX1), output of

stDAC2 (AUX2)

[1]

test signal Corr1

[1]

reserved

DAC: test signal MinLevel

[1]

DAC: test signal ADC_I

[1]

DAC: test signal ADC_Q

[1]

reserved

reserved, test signal for production test

[1]

reserved

HIGH

LOW

TxActive:

106 kBd: HIGH during start bit, data bit, parity and CRC

212 kBd, 424 kBd and 848 kBd: HIGH during data and

CRC

1101

1110

1111

RxActive:

106 kBd: HIGH during data bit, parity and CRC

212 kBd, 424 kBd and 848 kBd: HIGH during data and

CRC

subcarrier detected:

106 kBd: not applicable

212 kBd: 424 kBd and 848 kBd: HIGH during last part of

data and CRC

test bus bit as defined by the

stSel1Reg register’s

tBusBitSel[2:0] bits

Remark:

all test signals are described in

Section 17.1 “

signals” on page 82

3 to 0

AnalogSelAux2[3:0] –

controls pin AUX2 (see bit descriptions for AUX1)

[1]

Remark:

Current source output; the use of 1 k



pull-down resistor on AUXn is recommended.

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9.2.4.10 TestDAC1Reg

Defines the test value for

stDAC1.

Table 136.

TestDAC1Reg register (address 39h); reset value: xxh bit allocation

Bit

Symbol

Access

reserved

–

stDAC1[5:0]

R/W

Table 137.

TestDAC1Reg register bit descriptions

Bit

Symbol

reserved

Description

reserved for production tests

reserved for future use

5 to 0

stDAC1[5:0] defines

the test value for

stDAC1. Output of DAC1 can be routed to

AUX1 by setting value AnalogSelAux1[3:0] to 0001b in the

Analog

stReg register

9.2.4.11 TestDAC2Reg

Defines the test value for

stDAC2.

Table 138.

TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation

Bit

Symbol

Access

reserved

–

stDAC2[5:0]

R/W

Table 139.

TestDAC2Reg register bit descriptions

Bit

Symbol

Description

7 to 6

5 to 0

reserved

reserved for future use

stDAC2[5:0] defines

the test value for

stDAC2. DAC2 output can be routed to

AUX2 by setting value AnalogSelAux2[3:0] to 0001b in the

Analog

stReg register

9.2.4.12 TestADCReg

Shows the values of ADC I-channel and Q-channel.

Table 140.

TestADCReg register (address 3Bh); reset value: xxh bit allocation

Bit

Symbol

Access

ADC_I[3:0]

ADC_Q[3:0]

Table 141.

TestADCReg register bit descriptions

Bit

Symbol

Description

7 to 4

3 to 0

ADC_I[3:0]

ADC_Q[3:0]

ADC I-channel value

ADC Q-channel value

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9.2.4.13 Reserved

Functionality reserved for production test.

Table 142.

Reserved register (address 3Ch); reset value: FFh bit allocation

Bit

Symbol

Access

reserved

–

Table 143.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for production tests

7 to 0

reserved

Table 144.

Reserved register (address 3Dh); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 145.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for production tests

7 to 0

reserved

Table 146.

Reserved register (address 3Eh); reset value: 03h bit allocation

Bit

Symbol

Access

reserved

–

Table 147.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for production tests

7 to 0

reserved

Table 148.

Reserved register (address 3Fh); reset value: 00h bit allocation

Bit

Symbol

Access

reserved

–

Table 149.

Reserved register bit descriptions

Bit

Symbol

Description

reserved for production tests

7 to 0

reserved

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10. MFRC523 command set

The MFRC523 operation is determined by a state machine capable of performing a set of

commands. A command is executed by writing a command code (see

ble 150

) to the

CommandReg register.

Arguments and data necessary to process a command are exchanged using the FIFO

buffer.

10.1 General

description

The MFRC523 operation is determined by a state machine capable of performing a set of

commands. A command is executed by writing a command code (see

ble 150

) to the

CommandReg register.

Arguments and/or data necessary to process a command are exchanged via the FIFO

buffer.

10.2 General

behavior

•

Each command that needs a data bit stream (or data byte stream) as an input

immediately processes any data in the FIFO buffer. An exception to this rule is the

Transceive command. Using this command, transmission is started with the

BitFramingReg register’s StartSend bit.

•

Each command that needs a certain number of arguments, starts processing only

when it has received the correct number of arguments from the FIFO buffer.

•

The FIFO buffer is not automatically cleared when commands start. This makes it

possible to write command arguments and/or the data bytes to the FIFO buffer and

then start the command.

•

Each command can be interrupted by the host writing a new command code to the

CommandReg register, for example, the Idle command.

10.3 MFRC523

command overview

Table 150.

Command overview

Command

Command Action

code

Idle

0000

0001

no action, cancels current command execution

Mem

stores 25 bytes into the internal buffer

Generate RandomID

0010

generates a 10-byte random ID number

activates the CRC coprocessor or performs a self-test

transmits data from the FIFO buffer

CalcCRC

0011

0100

0111

Transmit

NoCmdChange

no command change, can be used to modify the

CommandReg register bits without affecting the command,

for example, the PowerDown bit

Receive

1000

1100

activates the receiver circuits

Transceive

transmits data from FIFO buffer to antenna and automatically

activates the receiver after transmission

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Standard 3V ISO/IEC 14443 A/B reader solution

Table 150.

Command overview

…continued

Command

Command Action

code

–

1101

1110

1111

reserved for future use

MFAuthent

SoftReset

performs the MIFARE standard authentication as a reader

resets the MFRC523

10.3.1 MFRC523

command descriptions

10.3.1.1 Idle

mode

Places the MFRC523 in Idle mode. The Idle command also terminates itself.

10.3.1.2 Mem

command

Transfers 25 bytes from the FIFO buffer to the internal buffer.

ead out the 25 bytes

from the internal buffer the Mem command must be started with an empty FIFO buffer. In

this case, the 25 bytes are transferred from the internal buffer to the FIFO.

During a hard power-down (using pin NRSTPD), the 25 bytes in the internal buffer remain

unchanged and are only lost if the power supply is removed from the MFRC523.

This command automatically terminates when finished and the Idle command becomes

active.

10.3.1.3 Generate

RandomID

This command generates a 10-byte random number which is initially stored in the internal

buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command

automatically terminates when finished and the MFRC523 returns to Idle mode.

10.3.1.4 CalcCRC

command

The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is

started. The calculation result is stored in the CRCResultReg register. The CRC

calculation is not limited to a dedicated number of bytes. The calculation is not stopped

when the FIFO buffer is empty during the data stream. The next byte written to the FIFO

buffer is added to the calculation.

The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The

value is loaded in to the CRC coprocessor when the command starts. This command

must be terminated by writing a command to the CommandReg register, such as, the Idle

command.

If the Auto

stReg register’s Self

st[3:0] bits are set correctly, the MFRC523 enters

Self-test mode. Starting the CalcCRC command initiates a digital self-test. The result of

the self-test is written to the FIFO buffer.

10.3.1.5 Transmit

command

The FIFO buffer content is immediately transmitted after starting this command. Before

transmitting the FIFO buffer content, all relevant registers must be set for data

transmission.

This command automatically terminates when the FIFO buffer is empty. It can be

terminated by another command written to the CommandReg register.

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10.3.1.6 NoCmdChange

command

This command does not influence any running command in the CommandReg register. It

can be used to manipulate any bit except the CommandReg register Command[3:0] bits,

for example, the RcvOff bit or the PowerDown bit.

10.3.1.7 Receive

command

The MFRC523 activates the receiver path and waits for a data stream to be received. The

correct settings must be chosen before starting this command.

This command automatically terminates when the data stream ends. This is indicated

either by the end of frame pattern or by the length byte depending on the selected frame

type and speed.

Remark:

If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive

command does not automatically terminate. It must be terminated by starting another

command in the CommandReg register.

10.3.1.8 Transceive

command

This command continuously repeats the transmission of data from the FIFO buffer and the

reception of data from the RF field. The first action is transmit and after transmission the

command is changed to receive a data stream.

Each transmit process must be started by setting the BitFramingReg register’s StartSend

bit to logic 1. This command must be cleared by writing any command to the

CommandReg register.

Remark:

If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive

command never leaves the receive state because this state cannot be cancelled

automatically.

10.3.1.9 MFAuthent

command

This command manages MIFARE authentication to enable a secure communication to

any MIFARE card. The following data is written to the FIFO buffer before the command

can be activated:

•

Authentication command code (60h, 61h)

•

Block address

•

Sector key byte 0

•

Sector key byte 1

•

Sector key byte 2

•

Sector key byte 3

•

Sector key byte 4

•

Sector key byte 5

•

Card serial number byte 0

•

Card serial number byte 1

•

Card serial number byte 2

•

Card serial number byte 3

12 bytes in total are written to the FIFO.

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Remark:

When the MFAuthent command is active all access to the FIFO buffer is

blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is

set.

This command automatically terminates when the MIFARE card is authenticated and the

Status2Reg register’s MFCrypto1On bit is set to logic 1.

This command does not terminate automatically if the card does not answer, so the timer

must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the

TimerIRq bit can be used as the termination criteria. During authentication processing, the

RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of

the MFAuthent command, either after processing the protocol or writing Idle to the

CommandReg register.

If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to

logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.

10.3.1.10 SoftReset

command

This command performs a reset of the device. The configuration data of the internal buffer

remains unchanged. All registers are set to the reset values. This command automatically

terminates when finished.

Remark:

The SerialSpeedReg register is reset and therefore the serial data rate is set to

9.6 kBd.

11. Errata

sheet

This chapter lists all differences from version 1.0 to version 2.0:

The value of the version in

Section 9.2.4.8 on page 65

is set to B1h.

The answer to the Selftest (see

Section 17.1 on page 82

) for version 1.0 (VersionReg

equal to B1h):

00h, C6h, 37h, D5h, 32h, B7h, 57h, 5Ch

C2h, D8h, 7Ch, 4Dh, D9h, 70h, C7h, 73h

10h, E6h, D2h, AAh, 5Eh, A1h, 3Eh, 5Ah

14h, AFh, 30h, 61h, C9h, 70h, DBh, 2Eh

64h, 22h, 72h, B5h, BDh, 65h, F4h, ECh

22h, BCh, D3h, 72h, 35h, CDh, AAh, 41h

1Fh, A7h, F3h, 53h, 14h, DEh, 7Eh, 02h

D9h, 0Fh, B5h, 5Eh, 25h, 1Dh, 29h, 79h

Only the default setting for the prescaler (see

Section 8.7 “Timer unit” on page 29

): t =

((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula f

Timer

13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in

ble 108

“TPrescalerReg register (address 2Bh); reset value: 00h bit allocation” on page 60

and

TPrescalerLo in

ble 109 “TPrescalerReg register bit descriptions” on page 61

. As there

is no option for the prescaler, also the TPrescalEven (see

ble 73 “DemodReg register

bit descriptions”

) shall be set to 0, see also

Section 9.2.3.10 “TModeReg and

TPrescalerReg registers” on page 59

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Especially when using time slot protocols, it is needed that the error flag is copied into the

status information of the frame. When using the RxMultiple feature (see

Section 9.2.2.4

on page 48

) within version 1.0 the protocol error flag is not included in the status

information for the frame. In addition the CRCOk is copied instead of the CRCErr. This

can be a problem in frames without length information e.g. ISO/IEC 14443-B.

The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits,

as such the configuration within

Section 9.2.2.15 “TypeBReg register” on page 54

bit 4 for

RxEOFReq does not exist. In addition the IC only has the possibility to select the

minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As

such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see

Section

9.2.4.7 “Auto

stReg register” on page 64

) does not exist and the configuration is limited

to only setting minimum and maximum length according ISO/IEC 14443-B, see

Section

9.2.2.15 “TypeBReg register” on page 54

, bit 4.

The available NXP NFC library is only tested with version 2.0.

12. Limiting values

Table 151.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

+4.0

Unit

DDA

DDD

analog supply voltage

digital supply voltage



0.5



0.5



0.5



0.5



0.5

DD(PVDD)

PVDD supply voltage

DD(TVDD)

TVDD supply voltage

DD(SVDD)

SVDD supply voltage

input voltage

all input pins except pins MFIN and

SS(PVSS)



0.5 V

DD(PVDD)

+ 0.5

pin MFIN

SS(PVSS)



0.5 V

DD(SVDD)

+ 0.5

tot

total power dissipation

junction temperature

per package; V

DDD

in shortcut

mode

–

200

–

100



ESD

electrostatic discharge voltage

HBM; 1500



, 100 pF;

2000

JESD22-A114-B

MM; 0.75



H, 200 pF;

–

200

JESD22-A114-A

Charged device model;

JESD22-C101-A

on all pins

–

200

500

on all pins except SVDD in

TFBGA64 package

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13. Recommended operating conditions

Table 152.

Operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max Unit

[1][2]

[3]

DDA

analog supply voltage

DD(PVDD)



DDA

= V

DDD

= V

DD(TVDD)

;

2.5

3.3

3.6

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

DDD

digital supply voltage

DD(PVDD)



DDA

= V

DDD

= V

DD(TVDD)

;

2.5

1.6

3.3

1.8

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

DD(PVDD)



DDA

= V

DDD

= V

DD(TVDD)

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

DD(PVDD)



DDA

= V

DDD

= V

DD(TVDD)

_{SSA
= V
SSD
= V
SS(PVSS)
= V
SS(TVSS)
= 0 V}

DD(TVDD)

TVDD supply voltage

DD(PVDD)

PVDD supply voltage

DD(SVDD)

SVDD supply voltage

;

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

HVQFN32

1.6

–

3.6

amb

ambient temperature



+85



[1] Supply

voltages below 3 V reduce the performance in, for example, the achievable operating distance.

[2]

DDA

, V

DDD

and V

DD(TVDD)

must always be the same voltage.

[3] V

DD(PVDD)

must always be the same or lower voltage than V

DDD

14. Thermal characteristics

Table 153.

Thermal characteristics

Symbol Parameter

th(j-a)

thermal resistance from junction to

ambient

Conditions

Package

Typ Unit

in still air with exposed pin soldered on a

4 layer JEDEC PCB

HVQFN32 40

K/W

15. Characteristics

Table 154.

Characteristics

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Input characteristics

Pins EA, I2C and NRSTPD

input leakage

current



–



HIGH-level input

voltage

0.7V

DD(PVDD)

–

LOW-level input

voltage

0.3V

DD(PVDD)

Pin MFIN

input leakage

current



–



HIGH-level input

voltage

0.7V

DD(SVDD)

–

LOW-level input

voltage

0.3V

DD(SVDD)

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Table 154.

Characteristics

…continued

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Pin SDA

input leakage

current



–



HIGH-level input

voltage

0.7V

DD(PVDD)

–

LOW-level input

voltage

0.3V

DD(PVDD)

Pin RX

[1]

input voltage



–

DDA

–

input capacitance

DDA

= 3 V; receiver active;

RX(p-p)

= 1 V; 1.5 V (DC)

offset

–

input resistance

DDA

= 3 V; receiver active;

–

350

–



_{RX(p-p)
= 1 V; 1.5 V (DC)}

offset

Input voltage range; see

Figure 24

i(p-p)(min)

minimum Manchester

encoded;

peak-to-peak input

DDA

= 3 V

–

100

–

voltage

i(p-p)(max)

maximum

Manchester encoded;

peak-to-peak input

DDA

= 3 V

voltage

Input sensitivity; see

Figure 24

mod

modulation voltage

minimum Manchester

encoded; V

DDA

= 3 V;

–

RxGain[2:0] = 111b (48 dB)

Pin OSCIN

input leakage

current



–



HIGH-level input

voltage

0.7V

DDA

–

LOW-level input

voltage

–

0.3V

DDA

–

input capacitance

DDA

= 2.8 V; DC = 0.65 V;

AC = 1 V (p-p)

Input/output characteristics

pins D1, D2, D3, D4, D5, D6 and D7

input leakage

current



–



HIGH-level input

voltage

0.7V

DD(PVDD)

–

DD(PVDD)



0.4

SS(PVSS)

–

LOW-level input

voltage

0.3V

DD(PVDD)

SS(PVSS)

+ 0.4

HIGH-level output

voltage

DD(PVDD)

= 3 V; I

= 4 mA

DD(PVDD)

= 3 V; I

= 4 mA

LOW-level output

voltage

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Table 154.

Characteristics

…continued

Symbol Parameter

HIGH-level output

Conditions

DD(PVDD)

= 3 V

Min

Typ

Max

Unit

–

current

LOW-level output

current

DD(PVDD)

= 3 V

–

Output characteristics

Pin MFOUT

HIGH-level output

voltage

DD(SVDD)

= 3 V; I

= 4 mA

DD(SVDD)

= 3 V; I

= 4 mA

DD(SVDD)

= 3 V

DD(SVDD)



0.4

–

DD(SVDD)

LOW-level output

voltage

SS(PVSS)

+ 0.4

LOW-level output

current

–

HIGH-level output

current

DD(SVDD)

= 3 V

Pin IRQ

HIGH-level output

voltage

DD(PVDD)

= 3 V; I

= 4 mA

DD(PVDD)

= 3 V; I

= 4 mA

DD(PVDD)

= 3 V

DD(PVDD)



0.4

–

DD(PVDD)

LOW-level output

voltage

SS(PVSS)

+ 0.4

LOW-level output

current

–

HIGH-level output

current

DD(PVDD)

= 3 V

Pins AUX1 and AUX2

HIGH-level output

voltage

DDD

= 3 V; I

= 4 mA

DDD

= 3 V; I

= 4 mA

DDD

= 3 V

DDD



0.4

–

DDD

LOW-level output

voltage

SS(PVSS)

+ 0.4

LOW-level output

current

–

HIGH-level output

current

DDD

= 3 V

Pins TX1 and TX2

HIGH-level output

voltage

DD(TVDD)

= 3 V;

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 3Fh

DD(TVDD)



0.15

DD(TVDD)



0.4

DD(TVDD)



0.24

DD(TVDD)



0.64

–

_{DD(TVDD)
= 3 V;}

_{DD(TVDD)
= 80 mA;}

CWGsP[5:0] = 3Fh

DD(TVDD)

= 2.5 V;

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 3Fh

DD(TVDD)

= 2.5 V;

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 3Fh

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Table 154.

Characteristics

…continued

Symbol Parameter

LOW-level output

voltage

Conditions

Min

Typ

Max

Unit

DD(TVDD)

= 3 V;

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 0Fh

–

0.15

_{DD(TVDD)
= 3 V;}

_{DD(TVDD)
= 80 mA;}

CWGsP[5:0] = 0Fh

–

0.4

DD(TVDD)

= 2.5 V;

0.24

0.64

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 0Fh

DD(TVDD)

= 2.5 V;

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 0Fh

Current consumption

power-down current

DDA

= V

DDD

= V

DD(TVDD)

DD(PVDD)

= 3 V

[2]

hard power-down; pin

NRSTPD set LOW

–



soft power-down; RF

level detector on

–

DDD

DDA

digital supply

current

pin DVDD; V

DDD

= 3 V

6.5

analog supply

current

pin AVDD; V

DDA

= 3 V;

CommandReg register’s

bit RcvOff = 0

pin AVDD; receiver

switched off; V

DDA

= 3 V;

CommandReg register’s

bit RcvOff = 1

–

[3]

[4][5][6]

[7]

DD(PVDD)

PVDD supply

current

pin PVDD

–

100

DD(TVDD)

TVDD supply

current

pin TVDD; continuous wave

pin SVDD

–

DD(SVDD)

SVDD supply

current

Clock frequency

clk



clk

jit

clock frequency

clock duty cycle

jitter time

–

27.12

–

MHz

–

RMS

Crystal oscillator

HIGH-level output

voltage

pin OSCOUT

–

1.1

0.2

–

LOW-level output

voltage

input capacitance

pin OSCOUT

pin OSCIN

–

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Table 154.

Characteristics

…continued

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Typical input requirements

xtal

crystal frequency

–

27.12

–

MHz

ESR

equivalent series

resistance

100



load capacitance

–

xtal

crystal power

dissipation

100



[1] The

voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.

[2] I

is the total current for all supplies.

[3]

DD(PVDD)

depends on the overall load at the digital pins.

[4] I

DD(TVDD)

depends on V

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

[5] During

typical circuit operation, the overall current is below 100 mA.

[6] Typical

value using a complementary driver configuration and an antenna matched to 40



between pins TX1 and TX2 at 13.56 MHz.

[7]

_{DD(SVDD)
depends on the load at pin MFOU
T
.}

mod

i(p-p)(min)

i(p-p)(max)

VMID

13.56 MHz

carrier

0 V

001aak012

Fig 24.

Pin RX input voltage range

15.1 Timing

characteristics

Table 155.

SPI timing characteristics

Symbol

Parameter

Conditions

line SCK

Min

Typ

Max Unit

pulse width LOW

pulse width HIGH

–

line SCK

h(SCKH-D)

SCK HIGH to data input

SCK to changing MOSI

hold time

su(D-SCKH)

data input to SCK HIGH

changing MOSI to SCK

set-up time

–

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Table 155.

SPI timing characteristics

…continued

Symbol Parameter

Conditions

h(SCKL-Q)

Min

Typ

Max Unit

SCK LOW to data output

SCK to changing MISO

hold time

–

(SCKL-NSSH)

SCK LOW to NSS HIGH

time

–

NSSH

NSS HIGH time

before communication

–

Table 156.

C-bus timing in Fast mode

Symbol Parameter

Conditions

Fast mode

High-speed Unit

mode

Min Max

SCL

SCL clock frequency

400

–

3400 kHz

HD;STA

hold time (repeated) START

condition

after this period,

the first clock pulse

is generated

600

160

–

SU;STA

set-up time for a repeated

START condition

600

–

160

–

SU;STO

set-up time for STOP condition

600

1300

600

–

160

–

LOW

HIGH

LOW period of the SCL clock

HIGH period of the SCL clock

–

HD;DAT

data hold time

900

–

SU;DAT

data set-up time

rise time

100

SCL signal

300 10

fall time

rise time

SDA and SCL

signals

fall time

SDA and SCL

signals

300 10

–

BUF

bus free time between a STOP

and START condition

1.3

–

1.3



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SCKL

SCKH

SHDX

SCK

SLDX

DXSH

MOSI

MISO

NSS

MSB

LSB

SLNH

001aaj634

Remark:

The signal NSS must be LOW to be able to send several bytes in one data stream.

end more than one data stream NSS must be set HIGH between the data streams.

Fig 25.

Timing diagram for SPI

SDA

SU;D

BUF

LOW

HD;S

SCL

SU;STO

HIGH

SU;S

HD;S

HD;D

001aaj635

Fig 26.

Timing for Fast and Standard mode devices on the I

C-bus

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16. Application information

A typical application diagram using a complementary antenna connection to the

MFRC523 is shown in

Figure 27

The antenna tuning and RF part matching is described in the application note

Ref. 1

and

Ref. 2

supply

DVDD

AVDD

TVDD

CRx

PVDD

SVDD

PVSS

Cvmid

VMID

TX1

NRSTPD

antenna

Lant

host

interface

MFRC523

TVSS

TX2

MICRO-

PROCESSOR

10, 14

IRQ

AVSS

DVSS

OSCOUT

OSCIN

27.12 MHz

001aal163

Fig 27.

Typical application diagram

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17. Test information

17.1 Test

signals

17.1.1 Self-test

The MFRC523 has the capability to perform a digital self-test. The self-test is started by

using the following procedure:

1. Perform

a soft reset.

2. Clear

the internal buffer by writing 25 bytes of 00h and implement the Config

command.

3. Enable

the self-test by writing 09h to the Auto

stReg register.

4. Write

00h to the FIFO buffer.

5. Start

the self-test with the CalcCRC command.

6. The

self-test is initiated.

7. When

the self-test has completed, the FIFO buffer contains the following 64 bytes:

FIFO buffer byte values for version B2h:

00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh, 9Dh,

3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h, 49h, 7Ch,

84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h, 21h, A9h, 86h,

96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh, 95h, 3Bh, 2Fh

The FIFO buffer byte values for version B1h are available at

Section 11

17.1.2 Test

bus

The test bus is used for production tests. The following configuration can be used to

improve the design of a system using the MFRC523. The test bus allows internal signals

to be routed to the digital interface. The test bus comprises two sets of test signals which

are selected using their subaddress specified in the

stSel2Reg register’s

stBusSel[4:0] bits. The test signals and their related digital output pins are described in

ble 157

and

ble 158

Table 157.

Test bus signals: TestBusSel[4:0] = 07h

Pins

Internal

Description

signal name

s_data

s_coll

received data stream

bit-collision detected (106 kBd only)

s_data and s_coll signals are valid

receiver has detected a stop condition

receiver is reset

s_valid

s_over

RCV_reset

–

reserved

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Table 158.

Test bus signals: TestBusSel[4:0] = 0Dh

Pins

Internal test

signal name

Description

clkstable

oscillator output signal

oscillator output signal divided by 8

reserved

clk27/8

D4 to D3

–

clk27

–

oscillator output signal

reserved

17.1.3 Test

signals on pins AUX1 or AUX2

The MFRC523 allows the user to select internal signals for measurement on pins AUX1 or

AUX2. These measurements can be helpful during the design-in phase to optimize the

design or used for test purposes.

ble 159

shows the signals that can be switched to pin AUX1 or AUX2 by setting

AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the Analog

stReg register.

Remark:

The DAC has a current output, therefore it is recommended that a 1 k



pull-down resistor is connected to pin AUX1 or pin AUX2.

Table 159.

Test signal descriptions

AnalogSelAuxn[3:0] Signal

on pin AUXn

0000

0001

0010

0011

3-state

DAC: register

stDAC1 or

stDAC2

DAC: test signal Corr1

reserved

0100

0101

0110

DAC: test signal MinLevel

DAC: test signal ADC_I

DAC: test signal ADC_Q

reserved

0111 to 1001

1010

1011

HIGH

LOW

1100

TxActive

1101

RxActive

1110

subcarrier detected

tBusBit

1111

17.1.3.1 Example:

Output test signals TestDAC1 and TestDAC2

The Analog

stReg register is set to 11h. The output on pin AUX1 has the test signal

stDAC1 and the output on pin AUX2 has the test signal

stDAC2. The signal values of

stDAC1 and

stDAC2 are controlled by the

stDAC1Reg and

stDAC2Reg

registers.

Figure 28

shows test signal

stDAC1 on pin AUX1 and

stDAC2 on pin AUX2 when the

stDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the

stDAC2Reg register is programmed with a rectangular signal defined by values 00h

and 3Fh.

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001aak597

(1)

(2)

100 ms/div

(1)

stDAC1

(500 mV/div) on pin AUX1.

(2)

stDAC2

(500 mV/div) on pin AUX2.

Fig 28.

Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2

17.1.3.2 Example:

Output test signals Corr1 and MinLevel

Figure 29

shows test signals Corr1 and MinLevel on pins AUX1 and AUX2, respectively.

The Analog

stReg register is set to 24h.

001aak598

(1)

(2)

(3)

s/div

(1) MinLevel

(1 V/div) on pin AUX2.

(2) Corr1

(1 V/div) on pin AUX1.

(3) RF

field.

Fig 29.

Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2

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17.1.3.3 Example:

Output test signals ADC I-channel and ADC Q-channel

Figure 30

shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and

AUX2, respectively. The Analog

stReg register is set to 56h.

001aak599

(1)

(2)

(3)

s/div

(1) ADC_I

(1 V/div) on pin AUX1.

(2) ADC_Q

(500 mV/div) on pin AUX2.

(3) RF

field.

Fig 30.

Output ADC I-channel on pin AUX1 and ADC Q-channel on pin AUX2

17.1.3.4 Example:

Output test signals RxActive and TxActive

Figure 31

shows the RxActive and TxActive test signals relating to RF communication.

The Analog

stReg register is set to CDh.

•

At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits

are not included

•

At 106 kBd, TxActive is HIGH during start bits, data bits, parity and CRC transmission

•

At 212 kBd, 424 kBd and 848 kBd, RxActive is HIGH during data bits and CRC

reception. Start bits are not included

•

At 212 kBd, 424 kBd and 848 kBd, TxActive is HIGH during data bits and CRC

transmission

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001aak600

(1)

(2)

(3)

s/div

(1) RxActive

(2 V/div) on pin AUX1.

(2) TxActive

(2 V/div) on pin AUX2.

(3) RF

field.

Fig 31.

Output RxActive on pin AUX1 and TxActive on pin AUX2

17.1.3.5 Example:

Output test signal RX data stream

Figure 32

shows the data stream that is currently being received. The

stSel2Reg

stBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6;

see

Section 17.1.2 “

st bus” on page 82

. The

stSel1Reg register’s

tBusBitSel[2:0]

bits are set 06h (pin D6 = s_data) and Analog

stReg register is set to FFh (

tBusBit)

which outputs the received data stream on pins AUX1 and AUX2.

001aak601

(1)

(2)

s/div

(1) s_data

(received data stream) (2 V/div).

(2) RF

field.

Fig 32.

Received data stream on pins AUX1 and AUX2

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17.1.3.6 Pseudo-Random

Binary Sequences (PRBS)

The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150

and are defined with the

stSel2Reg register. Transmission of either data stream is

started by the Transmit command. The preamble/sync byte/start bit/parity bit are

automatically generated depending on the mode selected.

Remark:

All relevant registers for transmitting data must be configured in accordance with

ITU-TO150 before selecting PRBS transmission.

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18. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm

SOT617-1

terminal 1

index area

detail X

1/2

A B

1/2

terminal 1

index area

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

0.05 0.30

0.00 0.18

5.1

4.9

3.25

2.95

5.1

4.9

3.25

2.95

0.5

0.3

0.05 0.1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-18

SOT617-1

– – –

MO-220

– – –

Fig 33.

Package outline SOT617-1 (HVQFN32)

MFRC523

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Detailed package information can be found at:

www.nxp.com/package/SOT617-1.html

19. Handling information

Moisture Sensitivity Level (MSL) evaluation has been performed according to

SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C)

. MSL for this package is level 1 which

means 260



C convection reflow temperature.

Dry pack is not required.

Unlimited out-of-pack floor life at maximum ambient 30



C/85 % RH.

20. Packing information

strap 46 mm from corner

The straps around the package of

stacked trays inside the plano-box

have sufficient pre-tension to avoid

loosening of the trays.

tray

ESD warning preprinted

barcode label (permanent)

barcode label (peel-off)

chamfer

PIN 1

chamfer

PIN 1

QA seal

Hyatt patent preprinted

In the traystack (2 trays)

only ONE tray type* allowed

printed plano box

*one supplier and one revision number.

001aaj740

Fig 34.

Packing information 1 tray

MFRC523

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strap 46 mm from corner

The straps around the package of

stacked trays inside the plano-box

have sufficient pre-tension to avoid

loosening of the trays.

tray

ESD warning preprinted

barcode label (permanent)

barcode label (peel-off)

chamfer

PIN 1

chamfer

PIN 1

QA seal

Hyatt patent preprinted

In the traystack (2 trays)

only ONE tray type* allowed

*one supplier and one revision number.

printed plano box

001aal164

Fig 35.

Packing information 5 trays

MFRC523

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21. Abbreviations

Table 160.

Abbreviations

Acronym

ADC

ASK

BPSK

CRC

Description

Analog-to-Digital Converter

Amplitude Shift Keying

Binary Phase Shift Keying

Cyclic Redundancy Check

Continuous Wave

DAC

EOF

ETU

HBM

Digital-to-Analog Converter

End Of Frame

Elementary Time Unit

Human Body Model

Inter-integrated Circuit

Least Significant Bit

Master In Slave Out

Machine Model

LSB

MISO

MOSI

MSB

NRZ

NSS

PCB

PLL

Master Out Slave In

Most Significant Bit

Not Return to Zero

Not Slave Select

Printed-Circuit Board

Phase-Locked Loop

Pseudo-Random Bit Sequence

Receiver

PRBS

SOF

SPI

Start Of Frame

Serial Peripheral Interface

Transmitter

UART

Universal Asynchronous Receiver Transmitter

22. Glossary

Modulation index —

Defined as the voltage ratio (V

max



min

) / (V

max

+ V

min

Load modulation index —

Defined as the voltage ratio for the card

max



min

) / (V

max

+ V

min

) measured at the card’s coil.

23. References

[1] Application

note —

MFRC52x Reader IC Family Directly Matched Antenna

Design

[2] Application

note —

MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity

Antennas

MFRC523

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24. Revision history

Table 161.

Revision history

Document ID

MFRC523 v. 4.1

20150506

Modifications:

MFRC523 v. 4.0

20141202

Modifications:

•

Section 8.2 “ISO/IEC 14443 B functionality”

: Remark removed

MFRC523 v. 3.9

20140917

Modifications:

•

ble 151 “Limiting values”

: updated

MFRC523 v. 3.8

20140312 Product

data sheet

Modifications:

Release date

Data sheet status

Change notice

Supersedes

Product data sheet

–

MFRC523 v. 4.0

•

Figure 27 “Typical application diagram”

: SVDD symbol corrected

Product data sheet

–

MFRC523 v. 3.9

MFRC523 v. 3.8

MFRC523 v. 3.7

Product data sheet

–

•

Section 2 “General description”

: updated

•

Section 11 “Errata sheet”

: section added

•

Descriptive title changed

MFRC523 v. 3.7

20111108

Product data sheet

–

MFRC523 v. 3.6

Modifications:

•

ble 2 “Ordering information”

: updated

•

ble 154 “Characteristics”

: unit of P

xtal

corrected

MFRC523 v. 3.6

20110628

Product data sheet

•

Section 9.2.1.7 “ErrorReg register” on page 40 added

20100924 Product

data sheet

–

MFRC523_35

MFRC523_34

MFRC523_33

Modifications:

MFRC523_35

Modifications:

MFRC523_34

Modifications:

•

ble 131 “VersionReg register bit descripitons” on page 63 changed

20100715 Product

data sheet

–

•

Section 9.2.2.10 “DemodReg register”: register updated.

•

Section 9.2.2.15 “TypeBReg register”: register updated.

•

Section 9.2.3.10 “TModeReg and TPrescalerReg registers”: register updated.

•

Section 9.2.4.7 “Auto

stReg register”: register updated.

•

Section 8.7 “Timer unit”: timer calculation updated.

•

Section 9.2.4.8 “VersionReg register”: version: B2h updated.

•

Section 16.1 “

st signals”: selftest result updated.

MFRC523_33

Modifications:

20100305

Product data sheet

–

MFRC523_32

•

ble 106 “TModeReg register bit descriptions” and

ble 108

“TPrescalerReg register bit descriptions”: text updated.

•

Section 8.7 “Timer unit”: input clock frequency changed to 13.56 MHz and

text updated.

•

ble 154 “SPI timing characteristics”: NSS HIGH time, t

NSSH

added.

MFRC523_32

20100112

Product data sheet

–

115231

MFRC523

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Table 161.

Revision history

…continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modifications:

•

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP

Semiconductors.

•

Legal texts have been adapted to the new company name where appropriate.

•

General re-wording of MIFARE designation and commercial conditions.

•

ble 106 “TModeReg register bit descriptions” and

ble 108 “TPrescalerReg register bit

descriptions”: changed value “f

Timer

= 13.56 MHz / (TPreScaler + 1)”.

•

Graphics: updated to latest standard.

•

Descriptive text: updated.

•

Parameter symbols: updated.

•

Section 9 “MFRC523 registers” now follows Section 8 “Functional description”.

•

Section 16 “

st information” added, incorporating Section 16.1 “

st signals”.

115231

115230

115220

May 2007

Product data sheet

Preliminary data sheet

–

115230

115220

–

September 2006

August 2006

MFRC523

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25. Legal information

25.1 Data

sheet status

Document status

[1][2]

Product status

[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet

Qualification

Product [short] data sheet

Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL

http://www.nxp.com

Suitability for use —

NXP Semiconductors products are not designed,

25.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft —

The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet —

A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications —

Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification —

The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

25.3 Disclaimers

Limited warranty and liability —

Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values —

Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including – without limitation – lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale —

NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at

http://www.nxp.com/profile/terms

, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the

rms and conditions of commercial sale

of NXP Semiconductors.

Right to make changes —

NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license —

Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

MFRC523

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Export control —

This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations —

A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Quick reference data —

The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

25.4 Licenses

Non-automotive qualified products —

Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

This NXP Semiconductors IC is ISO/IEC 14443 Type B

software enabled and is licensed under Innovatron’s

Contactless Card patents license for ISO/IEC 14443 B.

non-automotive qualified products in automotive equipment or applications.

The license includes the right to use the IC in systems

and/or end-user equipment.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

RATP/Innovatron

Technology

25.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

C-bus —

logo is a trademark of NXP Semiconductors N.

^{MIFARE —

is a trademark of NXP Semiconductors N.V.}

26. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

salesaddresses@nxp.com

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

95 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

27. Tables

ble 1.

Quick reference data

. . . . . . . . . . . . . . . . . . . . .2

ble 2.

Ordering information

. . . . . . . . . . . . . . . . . . . . .3

ble 3.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

ble 4.

Communication overview for ISO/IEC 14443 A

reader/writer .

. . . . . . . . . . . . . . . . . . . . . . . . . .8

ble 37.

Status1Reg register bit descriptions

. . . . . . . . 42

ble 38.

Status2Reg register (address 08h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 42

ble 39.

Status2Reg register bit descriptions

. . . . . . . . 42

ble 40.

FIFODataReg register (address 09h); reset

value: xxh bit allocation . . . . . . . . . . . . . . . . . . 43

ble 41.

FIFODataReg register bit descriptions

. . . . . . 43

ble 42.

FIFOLevelReg register (address 0Ah); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 43

ble 43.

FIFOLevelReg register bit descriptions . . . . . . 44

ble 44.

WaterLevelReg register (address 0Bh); reset

value: 08h bit allocation

. . . . . . . . . . . . . . . . . 44

ble 45.

WaterLevelReg register bit descriptions

. . . . . 44

ble 46.

ControlReg register (address 0Ch); reset

value: 10h bit allocation

. . . . . . . . . . . . . . . . . 44

ble 5.

Connection protocol for detecting different

interface types

. . . . . . . . . . . . . . . . . . . . . . . . .10

ble 6.

MOSI and MISO byte order . . . . . . . . . . . . . .

ble 7.

MOSI and MISO byte order . . . . . . . . . . . . . .

ble 8.

SPI read address . . . . . . . . . . . . . . . . . . . . . .

ble 9.

SPI write address

. . . . . . . . . . . . . . . . . . . . . .12

ble 10.

BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .12

ble 11.

Selectable UART transfer speeds

. . . . . . . . . .13

ble 12.

UART framing

. . . . . . . . . . . . . . . . . . . . . . . . .13

ble 13.

Read data byte order . . . . . . . . . . . . . . . . . . . .14

ble 14.

Write data byte order

. . . . . . . . . . . . . . . . . . . .14

ble 15.

Address byte 0 register; address MOSI . . . . . .16

ble 16.

on pin TX1

. . . . . . . . . . . . . . . . . . . . . . . . . . . .23

ble 47.

ControlReg register bit descriptions

. . . . . . . . 44

ble 48.

BitFramingReg register (address 0Dh); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 45

ble 49.

BitFramingReg register bit descriptions

. . . . . 45

ble 50.

CollReg register (address 0Eh); reset value:

xxh bit allocation

. . . . . . . . . . . . . . . . . . . . . . . 45

ble 51.

CollReg register bit descriptions

. . . . . . . . . . . 45

ble 52.

Reserved register (address 0Fh); reset value:

00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46

ble 53.

Reserved register bit descriptions . . . . . . . . . . 46

ble 54.

Reserved register (address 10h); reset value:

00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46

ble 55.

Reserved register bit descriptions . . . . . . . . . . 46

ble 56.

ModeReg register (address 11h); reset value:

3Fh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47

ble 57.

ModeReg register bit descriptions

. . . . . . . . . 47

ble 58.

TxModeReg register (address 12h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 48

ble 17.

on pin TX2

. . . . . . . . . . . . . . . . . . . . . . . . . . . .24

ble 18.

CRC coprocessor parameters

. . . . . . . . . . . . .27

ble 19.

Interrupt sources

. . . . . . . . . . . . . . . . . . . . . . .29

ble 20.

Behavior of register bits and their designation .32

ble 21.

MFRC523 register overview

. . . . . . . . . . . . . .34

ble 22.

Reserved register (address 00h); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .37

ble 23.

Reserved register bit descriptions

. . . . . . . . . .37

ble 24.

CommandReg register (address 01h); reset

value: 20h bit allocation . . . . . . . . . . . . . . . . . .37

ble 25.

CommandReg register bit descriptions

. . . . . .37

ble 26.

ComIEnReg register (address 02h); reset

value: 80h bit allocation . . . . . . . . . . . . . . . . . .38

ble 27.

ComIEnReg register bit descriptions . . . . . . . .38

ble 28.

DivIEnReg register (address 03h); reset

ble 59.

TxModeReg register bit descriptions

. . . . . . . 48

ble 60.

RxModeReg register (address 13h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 48

value: 00h bit allocation . . . . . . . . . . . . . . . . . .38

ble 29.

DivIEnReg register bit descriptions

. . . . . . . . .38

ble 30.

ComIrqReg register (address 04h); reset

value: 14h bit allocation . . . . . . . . . . . . . . . . . .39

ble 61.

RxModeReg register bit descriptions

. . . . . . . 48

ble 62.

TxControlReg register (address 14h); reset

value: 80h bit allocation

. . . . . . . . . . . . . . . . . 49

ble 31.

ComIrqReg register bit descriptions

. . . . . . . .39

ble 32.

DivIrqReg register (address 05h); reset value:

x0h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .40

ble 63.

TxControlReg register bit descriptions

. . . . . . 49

ble 64.

TxASKReg register (address 15h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 50

ble 33.

DivIrqReg register bit descriptions . . . . . . . . . .40

ble 34.

ErrorReg register (address 06h); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .41

ble 65.

TxASKReg register bit descriptions

. . . . . . . . 50

ble 66.

TxSelReg register (address 16h); reset

value: 10h bit allocation

. . . . . . . . . . . . . . . . . 50

ble 35.

ErrorReg register bit descriptions

. . . . . . . . . .41

ble 36.

Status1Reg register (address 07h); reset

value: 21h bit allocation . . . . . . . . . . . . . . . . . .41

ble 67.

TxSelReg register bit descriptions

. . . . . . . . . 50

ble 68.

RxSelReg register (address 17h); reset value:

84h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 51

continued >>

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

96 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

ble 69.

RxSelReg register bit descriptions . . . . . . . . . .51

ble 70.

RxThresholdReg register (address 18h); reset

value: 84h bit allocation . . . . . . . . . . . . . . . . . .52

ble 71.

RxThresholdReg register bit descriptions

. . . .52

ble 72.

DemodReg register (address 19h); reset

value: 4Dh bit allocation

. . . . . . . . . . . . . . . . .52

ble 73.

DemodReg register bit descriptions . . . . . . . . .52

ble 74.

Reserved register (address 1Ah); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .53

ble 75.

Reserved register bit descriptions

. . . . . . . . . .53

ble 76.

Reserved register (address 1Bh); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .53

ble 77.

Reserved register bit descriptions

. . . . . . . . . .53

ble 78.

MfTxReg register (address 1Ch); reset value:

62h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .53

ble 79.

MfTxReg register bit descriptions

. . . . . . . . . .54

ble 80.

MfRxReg register (address 1Dh); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .54

ble 81.

MfRxReg register bit descriptions

. . . . . . . . . .54

ble 82.

TypeBReg register (address 1Eh); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .54

ble 83.

TypeBReg register bit descriptions

. . . . . . . . .54

ble 84.

SerialSpeedReg register (address 1Fh); reset

value: EBh bit allocation

. . . . . . . . . . . . . . . . .55

ble 103. CWGsPReg register bit descriptions

. . . . . . . 59

ble 104. ModGsPReg register (address 29h); reset

value: 20h bit allocation

. . . . . . . . . . . . . . . . . 59

ble 105. ModGsPReg register bit descriptions . . . . . . . 59

ble 106. TModeReg register (address 2Ah); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 59

ble 107. TModeReg register bit descriptions

. . . . . . . . 60

ble 108. TPrescalerReg register (address 2Bh); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 60

ble 109. TPrescalerReg register bit descriptions

. . . . . 61

ble 110. TReloadReg (higher bits) register (address

2Ch); reset value: 00h bit allocation

. . . . . . . . 61

ble 111. TReloadReg register higher bit descriptions . . 61

ble 112. TReloadReg (lower bits) register (address

2Dh); reset value: 00h bit allocation

. . . . . . . . 61

ble 113. TReloadReg register lower bit descriptions

. . 61

ble 114. TCounterValReg (higher bits) register

(address 2Eh); reset value: xxh bit allocation

. 61

ble 115. TCounterValReg register higher bit

descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

ble 116. TCounterValReg (lower bits) register (address

2Fh); reset value: xxh bit allocation

. . . . . . . . 62

ble 117. TCounterValReg register lower bit

descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

ble 118. Reserved register (address 30h); reset value:

00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62

ble 119. Reserved register bit descriptions

. . . . . . . . . 62

ble 120.

stSel1Reg register (address 31h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 62

ble 121.

stSel1Reg register bit descriptions . . . . . . . 62

ble 122.

stSel2Reg register (address 32h); reset

value: 00h bit allocation

. . . . . . . . . . . . . . . . . 63

ble 123.

stSel2Reg register bit descriptions . . . . . . . 63

ble 124.

stPinEnReg register (address 33h); reset

value: 80h bit allocation

. . . . . . . . . . . . . . . . . 63

ble 125.

stPinEnReg register bit descriptions

. . . . . 63

ble 126.

stPinValueReg register (address 34h);

reset value: 00h bit allocation

. . . . . . . . . . . . . 64

ble 127.

stPinValueReg register bit descriptions

. . . 64

ble 128.

stBusReg register (address 35h); reset

value: xxh bit allocation . . . . . . . . . . . . . . . . . . 64

ble 129.

stBusReg register bit descriptions

. . . . . . . 64

ble 130. Auto

stReg register (address 36h); reset

value: 40h bit allocation

. . . . . . . . . . . . . . . . . 64

ble 131. Auto

stReg register bit descriptions . . . . . . . 65

ble 132. VersionReg register (address 37h); reset

value: xxh bit allocation . . . . . . . . . . . . . . . . . . 65

ble 133. VersionReg register bit descriptions . . . . . . . . 65

ble 134. Analog

stReg register (address 38h);

reset value: 00h bit allocation

. . . . . . . . . . . . . 65

ble 135. Analog

stReg register bit descriptions . . . . . 66

ble 85.

SerialSpeedReg register bit descriptions . . . . .55

ble 86.

Reserved register (address 20h); reset value:

00h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .56

ble 87.

Reserved register bit descriptions

. . . . . . . . . .56

ble 88.

CRCResultReg (higher bits) register (address

21h); reset value: FFh bit allocation

. . . . . . . .56

ble 89.

CRCResultReg register higher bit descriptions 56

ble 90.

CRCResultReg (lower bits) register (address

22h); reset value: FFh bit allocation

. . . . . . . .56

ble 91.

CRCResultReg register lower bit descriptions .56

ble 92.

Reserved register (address 23h); reset value:

88h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .57

ble 93.

Reserved register bit descriptions

. . . . . . . . . .57

ble 94.

ModWidthReg register (address 24h); reset

value: 26h bit allocation . . . . . . . . . . . . . . . . . .57

ble 95.

ModWidthReg register bit descriptions

. . . . . .57

ble 96.

Reserved register (address 25h); reset value:

87h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .57

ble 97.

Reserved register bit descriptions

. . . . . . . . . .57

ble 98.

RFCfgReg register (address 26h); reset value:

48h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .58

ble 99.

RFCfgReg register bit descriptions

. . . . . . . . .58

ble 100. GsNReg register (address 27h); reset value:

88h bit allocation

. . . . . . . . . . . . . . . . . . . . . . .58

ble 101. GsNReg register bit descriptions

. . . . . . . . . .58

ble 102. CWGsPReg register (address 28h); reset

value: 20h bit allocation . . . . . . . . . . . . . . . . . .59

continued >>

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

97 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

ble 136.

stDAC1Reg register (address 39h); reset

value: xxh bit allocation

. . . . . . . . . . . . . . . . . .67

ble 137.

stDAC1Reg register bit descriptions

. . . . . .67

ble 138.

stDAC2Reg register (address 3Ah); reset

value: xxh bit allocation

. . . . . . . . . . . . . . . . . .67

ble 139.

stDAC2Reg register bit descriptions

. . . . . .67

ble 140.

stADCReg register (address 3Bh); reset

value: xxh bit allocation

. . . . . . . . . . . . . . . . . .67

ble 141.

stADCReg register bit descriptions

. . . . . . .67

ble 142. Reserved register (address 3Ch); reset

value: FFh bit allocation . . . . . . . . . . . . . . . . . .68

ble 143. Reserved register bit descriptions . . . . . . . . . .68

ble 144. Reserved register (address 3Dh); reset

value: 00h bit allocation . . . . . . . . . . . . . . . . . .68

ble 145. Reserved register bit descriptions . . . . . . . . . .68

ble 146. Reserved register (address 3Eh); reset

value: 03h bit allocation . . . . . . . . . . . . . . . . . .68

ble 147. Reserved register bit descriptions . . . . . . . . . .68

ble 148. Reserved register (address 3Fh); reset

value: 00h bit allocation . . . . . . . . . . . . . . . . . .68

ble 149. Reserved register bit descriptions . . . . . . . . . .68

ble 150. Command overview

. . . . . . . . . . . . . . . . . . . .69

ble 151. Limiting values

. . . . . . . . . . . . . . . . . . . . . . . .73

ble 152. Operating conditions . . . . . . . . . . . . . . . . . . . .74

ble 153. Thermal characteristics . . . . . . . . . . . . . . . . . .74

ble 154. Characteristics

. . . . . . . . . . . . . . . . . . . . . . . .74

ble 155. SPI timing characteristics

. . . . . . . . . . . . . . . .78

ble 156. I

C-bus timing in Fast mode

. . . . . . . . . . . . . .79

ble 157.

st bus signals:

stBusSel[4:0] = 07h

. . . . .82

ble 158.

st bus signals:

stBusSel[4:0] = 0Dh . . . . .83

ble 159.

st signal descriptions . . . . . . . . . . . . . . . . . .83

ble 160. Abbreviations

. . . . . . . . . . . . . . . . . . . . . . . . .91

ble 161. Revision history . . . . . . . . . . . . . . . . . . . . . . . .92

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

98 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

28. Figures

Fig 1.

Simplified block diagram of the MFRC523. . . . . . .4

Fig 2.

Detailed block diagram of the MFRC52

. . . . . . . .5

Fig 3.

Pinning configuration HVQFN32 (SOT617-1) . . . .6

Fig 4.

MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8

Fig 5.

ISO/IEC 14443 A/MIFARE Read/Write mode

communication diagram. . . . . . . . . . . . . . . . . . . . .8

Fig 6.

Data coding and framing according to

ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 7.

SPI connection to hos

. . . . . . . . . . . . . . . . . . . . .10

Fig 8.

UART connection to microcontrollers

. . . . . . . . .12

Fig 9.

UART read data timing diagram

. . . . . . . . . . . . .14

Fig 10.

UART write data timing diagram . . . . . . . . . . . . .15

Fig 11.

C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .16

Fig 12.

Bit transfer on the I

C-bus . . . . . . . . . . . . . . . . . .17

Fig 13.

START and STOP conditions

. . . . . . . . . . . . . . .17

Fig 14.

Acknowledge on the I

C-bus . . . . . . . . . . . . . . . .18

Fig 15.

Data transfer on the I

C-bus . . . . . . . . . . . . . . . .18

Fig 16.

First byte following the START procedure . . . . . .19

Fig 17.

Fig 18.

C-bus HS mode protocol switch . . . . . . . . . . . .21

Fig 19.

C-bus HS mode protocol frame. . . . . . . . . . . . .22

Fig 20.

Serial data switch for TX1 and TX2 . . . . . . . . . . .25

Fig 21.

Overview of MFIN and MFOUT signal routin

. . .26

Fig 22.

Quartz crystal connection

. . . . . . . . . . . . . . . . . .31

Fig 23.

Oscillator start-up tim

. . . . . . . . . . . . . . . . . . . . .

Fig 24.

Pin RX input voltage range

. . . . . . . . . . . . . . . . .78

Fig 25.

Timing diagram for SPI

. . . . . . . . . . . . . . . . . . . .80

Fig 26.

Timing for Fast and Standard mode devices

on the I

C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Fig 27.

Typical application diagram . . . . . . . . . . . . . . . . .81

Fig 28.

Output test signals

stDAC1 on pin AUX1 and

stDAC2 on pin AUX2 . . . . . . . . . . . . . . . . . . . .84

Fig 29.

Output test signals Corr1 on pin AUX1 and

MinLevel on pin AUX2 . . . . . . . . . . . . . . . . . . . . .84

Fig 30.

Output ADC I-channel on pin AUX1 and ADC

Q-channel on pin AUX

. . . . . . . . . . . . . . . . . . .

Fig 31.

Output RxActive on pin AUX1 and TxActive

on pin AUX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Fig 32.

Received data stream on pins AUX1 and AUX2 .86

Fig 33.

Package outline SOT617-1 (HVQFN32) . . . . . . .88

Fig 34.

Packing information 1 tray . . . . . . . . . . . . . . . . . .89

Fig 35.

Packing information 5 trays . . . . . . . . . . . . . . . . .90

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

99 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

29. Contents

1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6.1

8.7

8.8

8.8.1

8.8.2

8.8.3

8.9

8.10

8.10.1

8.10.2

Interrupt sources overvie

. . . . . . . . . . . . . . .

Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power reduction modes . . . . . . . . . . . . . . . . .

Hard power-down. . . . . . . . . . . . . . . . . . . . . .

Soft power-down mode . . . . . . . . . . . . . . . . .

Transmitter Power-down mode . . . . . . . . . . .

Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . .

Reset and oscillator start-up time

. . . . . . . . .

Reset timing requirement

. . . . . . . . . . . . . . .

Oscillator start-up tim

. . . . . . . . . . . . . . . . . .

Different available versions. . . . . . . . . . . . . . . .

General descriptio

. . . . . . . . . . . . . . . . . . . . . .

Features and benefits . . . . . . . . . . . . . . . . . . . .

Quick reference data . . . . . . . . . . . . . . . . . . . . .

Ordering informatio

. . . . . . . . . . . . . . . . . . . . .

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .

Pinning informatio

. . . . . . . . . . . . . . . . . . . . . .

Pin description

. . . . . . . . . . . . . . . . . . . . . . . . .

7.1

9.1

9.1.1

9.2

MFRC523 registers . . . . . . . . . . . . . . . . . . . . .

MFRC523 register overview

. . . . . . . . . . . . .

Page 0: Command and status . . . . . . . . . . . .

Reserved register 00h . . . . . . . . . . . . . . . . . .

CommandReg registe

. . . . . . . . . . . . . . . . . .

ComIEnReg register

. . . . . . . . . . . . . . . . . . .

DivIEnReg registe

. . . . . . . . . . . . . . . . . . . . .

ComIrqReg register . . . . . . . . . . . . . . . . . . . .

DivIrqReg register . . . . . . . . . . . . . . . . . . . . .

ErrorReg register . . . . . . . . . . . . . . . . . . . . . .

Status1Reg register . . . . . . . . . . . . . . . . . . . .

Status2Reg register . . . . . . . . . . . . . . . . . . . .

8.1

8.2

8.3

8.3.1

8.3.2

Functional description

. . . . . . . . . . . . . . . . . . .

ISO/IEC 14443 A functionality . . . . . . . . . . . . .

ISO/IEC 14443 B functionality . . . . . . . . . . . . .

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . .

Automatic microcontroller interface detection. .

Serial Peripheral Interface . . . . . . . . . . . . . . .

SPI read data . . . . . . . . . . . . . . . . . . . . . . . . .

SPI write data . . . . . . . . . . . . . . . . . . . . . . . . .

SPI Read and Write address byte

. . . . . . . . .

UART interface . . . . . . . . . . . . . . . . . . . . . . . .

Connection to a host. . . . . . . . . . . . . . . . . . . .

Selectable UART transfer speeds

. . . . . . . . .

UART framin

. . . . . . . . . . . . . . . . . . . . . . . . .

C Bus Interface

. . . . . . . . . . . . . . . . . . . . . .

Data validity

. . . . . . . . . . . . . . . . . . . . . . . . . .

START and STOP conditions . . . . . . . . . . . . .

Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . .

Acknowledge .

. . . . . . . . . . . . . . . . . . . . . . . .

7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . .

High-speed mode . . . . . . . . . . . . . . . . . . . . . .

High-speed transfer . . . . . . . . . . . . . . . . . . . .

9.2.1

9.2.1.1

9.2.1.2

9.2.1.3

9.2.1.4

9.2.1.5

9.2.1.6

9.2.1.7

9.2.1.8

9.2.1.9

8.3.2.1

8.3.2.2

8.3.2.3

8.3.3

8.3.3.1

8.3.3.2

8.3.3.3

8.3.4

8.3.4.1

8.3.4.2

8.3.4.3

8.3.4.4

8.3.4.5

8.3.4.6

8.3.4.7

8.3.4.8

8.3.4.9

9.2.1.10 FIFODataReg

9.2.1.11 FIFOLevelReg

9.2.1.12 WaterLevelReg

9.2.1.13 ControlReg

9.2.1.14 BitFramingReg

9.2.1.15 CollReg

9.2.1.16 Reserved

9.2.2

Page 1: Communication. . . . . . . . . . . . . . . . .

Reserved register 10h . . . . . . . . . . . . . . . . . .

ModeReg register

. . . . . . . . . . . . . . . . . . . . .

TxModeReg register

. . . . . . . . . . . . . . . . . . .

RxModeReg register . . . . . . . . . . . . . . . . . . .

TxControlReg register . . . . . . . . . . . . . . . . . .

TxASKReg register

. . . . . . . . . . . . . . . . . . . .

TxSelReg register

. . . . . . . . . . . . . . . . . . . . .

RxSelReg register . . . . . . . . . . . . . . . . . . . . .

RxThresholdReg registe

. . . . . . . . . . . . . . . .

9.2.2.1

9.2.2.2

9.2.2.3

9.2.2.4

9.2.2.5

9.2.2.6

9.2.2.7

9.2.2.8

9.2.2.9

8.3.4.10 Serial

data transfer format in HS mode

. . . . .

8.3.4.11 Switching

between F/S mode and HS mode .

8.3.4.12 MFRC523

in lower speed modes . . . . . . . . . .

8.4

Analog interface and contactless UAR

. . . . .

Genera

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial data switch . . . . . . . . . . . . . . . . . . . . . .

MFIN and MFOUT interface support

. . . . . . .

CRC coprocessor . . . . . . . . . . . . . . . . . . . . . .

FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . .

Accessing the FIFO buffer . . . . . . . . . . . . . . .

Controlling the FIFO buffer . . . . . . . . . . . . . . .

FIFO buffer status information . . . . . . . . . . . .

Interrupt request syste

. . . . . . . . . . . . . . . . .

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.5

8.5.1

8.5.2

8.5.3

8.6

9.2.2.10 DemodReg

9.2.2.11 Reserved

9.2.2.12 Reserved

9.2.2.13 MfTxReg

9.2.2.14 MfRxReg

registe

. . . . . . . . . . . . . . . . . . . . . .

9.2.2.15 TypeBReg

9.2.2.16 SerialSpeedReg

continued >>

MFRC523

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 4.1 — 6 May 2015

115241

100 of 101

MFRC523

NXP Semiconductors

Standard 3V ISO/IEC 14443 A/B reader solution

9.2.3

Page 2: Configuratio

. . . . . . . . . . . . . . . . . . .

Test information

. . . . . . . . . . . . . . . . . . . . . . .

9.2.3.1

9.2.3.2

9.2.3.3

9.2.3.4

9.2.3.5

9.2.3.6

9.2.3.7

9.2.3.8

9.2.3.9

Reserved register 20h

. . . . . . . . . . . . . . . . . .

CRCResultReg registers

. . . . . . . . . . . . . . . .

Reserved register 23h

. . . . . . . . . . . . . . . . . .

ModWidthReg register . . . . . . . . . . . . . . . . . .

Reserved register 25h

. . . . . . . . . . . . . . . . . .

RFCfgReg register . . . . . . . . . . . . . . . . . . . . .

GsNReg registe

. . . . . . . . . . . . . . . . . . . . . . .

CWGsPReg register . . . . . . . . . . . . . . . . . . . .

ModGsPReg register . . . . . . . . . . . . . . . . . . .

17.1

st signals

. . . . . . . . . . . . . . . . . . . . . . . . . .

Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

st bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

st signals on pins AUX1 or AUX2. . . . . . . .

17.1.1

17.1.2

17.1.3

17.1.3.1 Example:

Output test signals

stDAC1 and

stDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.1.3.2 Example:

Output test signals Corr1 and

MinLevel. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.1.3.3 Example:

Output test signals ADC I-channel

and ADC Q-channel. . . . . . . . . . . . . . . . . . . .

17.1.3.4 Example:

Output test signals RxActive and

TxActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.1.3.5 Example:

Output test signal RX data stream .

17.1.3.6 Pseudo-Random

Binary Sequences (PRBS).

9.2.3.10 TModeReg

and TPrescalerReg registers . . . .

9.2.3.11 TReloadReg

. . . . . . . . . . . . . . . . . .

9.2.3.12 TCounterValReg

. . . . . . . . . . . . . . .

9.2.4

Page 3:

st . . . . . . . . . . . . . . . . . . . . . . . . . .

Reserved register 30h

. . . . . . . . . . . . . . . . . .

stSel1Reg register

. . . . . . . . . . . . . . . . . . .

stSel2Reg register

. . . . . . . . . . . . . . . . . . .

stPinEnReg register . . . . . . . . . . . . . . . . . .

stPinValueReg register . . . . . . . . . . . . . . . .

stBusReg register . . . . . . . . . . . . . . . . . . . .

Auto

stReg register . . . . . . . . . . . . . . . . . . .

VersionReg register . . . . . . . . . . . . . . . . . . . .

Analog

stReg register

. . . . . . . . . . . . . . . . .

9.2.4.1

9.2.4.2

9.2.4.3

9.2.4.4

9.2.4.5

9.2.4.6

9.2.4.7

9.2.4.8

9.2.4.9

Package outline. . . . . . . . . . . . . . . . . . . . . . . .

Handling information . . . . . . . . . . . . . . . . . . .

Packing information . . . . . . . . . . . . . . . . . . . .

Abbreviations .

. . . . . . . . . . . . . . . . . . . . . . . .

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

References. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Revision history

. . . . . . . . . . . . . . . . . . . . . . .

9.2.4.10

stDAC1Reg

9.2.4.11

stDAC2Reg

9.2.4.12

stADCReg

9.2.4.13 Reserved

Legal information . . . . . . . . . . . . . . . . . . . . . .

Data sheet status . . . . . . . . . . . . . . . . . . . . . .

Definitions .

. . . . . . . . . . . . . . . . . . . . . . . . . .

Disclaimers .

. . . . . . . . . . . . . . . . . . . . . . . . .

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .

25.1

25.2

25.3

25.4

25.5

MFRC523 command set

. . . . . . . . . . . . . . . . .

General description

. . . . . . . . . . . . . . . . . . . .

General behavior . . . . . . . . . . . . . . . . . . . . . .

MFRC523 command overview . . . . . . . . . . . .

MFRC523 command descriptions

. . . . . . . . .

10.1

10.2

10.3

10.3.1

Contact information

. . . . . . . . . . . . . . . . . . . .

Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100

10.3.1.1 Idle

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1.2 Mem

comman

. . . . . . . . . . . . . . . . . . . . . . . .

10.3.1.3 Generate

RandomID .

. . . . . . . . . . . . . . . . . .

10.3.1.4 CalcCRC

command . . . . . . . . . . . . . . . . . . . .

10.3.1.5 Transmit

comman

. . . . . . . . . . . . . . . . . . . . .

10.3.1.6 NoCmdChange

command . . . . . . . . . . . . . . .

10.3.1.7 Receive

command . . . . . . . . . . . . . . . . . . . . .

10.3.1.8 Transceive

command . . . . . . . . . . . . . . . . . . .

10.3.1.9 MFAuthent

command . . . . . . . . . . . . . . . . . . .

10.3.1.10 SoftReset

command . . . . . . . . . . . . . . . . . . . .

Errata sheet

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .

Recommended operating conditions. . . . . . .

Thermal characteristics

. . . . . . . . . . . . . . . . .

Characteristic

. . . . . . . . . . . . . . . . . . . . . . . . .

Timing characteristic

. . . . . . . . . . . . . . . . . . .

Application information. . . . . . . . . . . . . . . . . .

15.1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

2015.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 May 2015

115241

NXP-Semicon-MFRC52302HN1-151

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