NXP-Semicon-MKW35Z512VHT4

NXP Semiconductors  

MKW36Z512  

Data Sheet: Technical Data  

Rev. 8, 05/2020  

MKW36Z/35Z Data Sheet  

MKW36Z512VHT4  

MKW36Z512VFP4  

MKW35Z512VHT4  

An ultra low power, highly integrated Bluetooth® Low  

Energy 5.0 wireless microcontroller  

48 LQFN  

40 “Wettable” HVQFN  

7×7 mm Pitch 0.5 mm

 

6×6 mm Pitch 0.5 mm  

Multi-Standard Radio  

System peripherals  

• 2.4

 

GHz Bluetooth Low Energy (Bluetooth LE) version  

5.0 compliant supporting up to 8 simultaneous  

hardware connections  

• Nine

 

MCU low-power modes to provide power  

optimization based on application requirements  

• DC-DC

 

Converter supporting Buck and Bypass  

operating modes  

• Generic

 

FSK modulation  

• Data

 

Rate: 250, 500 and 1000 kbps  

• Modulations:

 

GFSK BT = 0.3, 0.5, and 0.7;  

FSK/MSK  

• Direct

 

memory access (DMA) Controller  

• Computer

 

operating properly (COP) watchdog  

• Serial

 

wire debug (SWD) Interface and Micro Trace  

buffer  

• Modulation

 

Index: 0.32, 0.5, 0.7, and 1.0  

Typical Receiver Sensitivity  

(Bluetooth LE 1 Mbps) = –95 dBm  

Typical Receiver Sensitivity  

•

•

• Bit

 

Manipulation Engine (BME)  

Analog Modules  

• 16-bit

 

Analog-to-Digital Converter (ADC)  

• 6-bit

 

High Speed Analog Comparator (CMP)  

• 1.2

 

V voltage reference (VREF)  

(250 kbps GFSK-BT=0.5, h=0.5) = –99 dBm  

• Programmable

 

Transmitter Output Power:  

–30 dBm to 5 dBm  

• Low

 

external component counts for low cost application  

• On-chip

 

balun with single ended bidirectional RF port  

Timers  

• 16-bit

 

low-power timer (LPTMR)  

• 3

 

Timer/PWM Modules(TPM): One 4 channel TPM  

and two 2 channel TPMs  

• Programmable

 

Interrupt Timer (PIT)  

• Real-Time

 

Clock (RTC)  

MCU and Memories  

• 256

 

KB program flash memory plus 256 KB FlexNVM  

on KW36Z  

• 8

 

KB FlexRAM supporting EEPROM emulation on  

KW36Z  

• 512

 

KB program flash memory on KW35Z  

• Up

 

to 48 MHz Arm® Cortex®-M0+ core  

• On-chip

 

64 KB SRAM  

Communication interfaces  

• 2

 

serial peripheral interface (SPI) modules  

• 2

 

inter-integrated circuit (I2C) modules  

• Low

 

Power UART (LPUART) module with LIN  

support (2x LPUART on KW36Z)  

Low Power Consumption  

• Carrier

 

Modulator Timer (CMT)  

• Transceiver

 

current (DC-DC buck mode, 3.6 V supply)  

• FlexCAN

 

module (with CAN FD support up to 3.2  

Mbps baudrate) on KW36Z  

NXP reserves the right to change the production detail specifications as may be  

required to permit improvements in the design of its products.  

• Typical

 

Rx Current: 6.3 mA  

• Typical

 

Tx current: 5.7 mA (0 dBm output)  

• Low

 

Power Mode (VLLS0) Current: 258 nA  

Security  

• AES-128

 

Hardware Accelerator (AESA)  

• True

 

Random Number Generator (TRNG)  

• Advanced

 

flash security on Program Flash  

• 80-bit

 

unique identification number per chip  

• 40-bit

 

unique media access control (MAC) sub-  

address  

Clocks  

• 26

 

and 32 MHz supported for Bluetooth LE and  

Generic FSK modes  

• 32.768

 

kHz Crystal Oscillator  

• LE

 

Secure Connections  

Operating Characteristics  

• Voltage

 

range: 1.71 V to 3.6 V  

• Ambient

 

temperature range: –40 to 105 °C  

• Industrial

 

Qualification  

Human-machine interface  

• General-purpose

 

input/output  

Orderable parts details  

Top Line  

Marking  

CAN  

FD  

Device  

Qualification  

2

nd

UART with LIN

 

FlexRAM  

Package  

MKW36Z512VHT4 (F)M36Z  

MKW36Z512VFP4 M36Z9V4  

MKW35Z512VHT4 (F)M35Z  

Industrial  

Y

Y

Y

Y

N

7X7 mm 48-pin  

LQFN  

Industrial  

Industrial  

Y

N

Y

N

6X6 mm 40-pin  

“Wettable” HVQFN  

7X7 mm 48-pin  

LQFN  

Related Resources  

Description  

Type  

Resource  

Product  

Selector  

The Product Selector lets you find the right Kinetis part for your design.  

Fact Sheet  

The Fact Sheet gives overview of the product key features and its uses.

 

Reference  

Manual  

The Reference Manual contains a comprehensive description of the  

structure and function (operation) of a device.  

MKW36A512RM

1  

Data Sheet  

The Data Sheet includes electrical characteristics and signal  

connections.  

This document.  

Chip Errata  

The chip mask set Errata provides additional or corrective information for

 

KINETIS_W_1N41U

1  

a particular device mask set.  

Package  

drawing  

Package dimensions are provided in package drawings.  

• 40-pin

 

“Wettable” HVQFN  

(6×6): 98ASA01025D

1  

• 48-pin

 

LQFN (7×7):  

98ASA00694D

1  

1. To

 

find the associated resource, go to

and perform a search using this term.  

2

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Table of Contents  

1

2

Introduction………………………………………………………………. 4  

6.4.1 Thermal

 

operating requirements…………………

.

4

5  

6.4.2 Thermal

 

attributes…………………………………….. 46  

6.5 Peripheral

 

operating requirements and behaviors……

.

4

6  

6.5.1 Core

 

modules……………………………………………46  

6.5.2 System

 

modules………………………………………. 47  

6.5.3 Clock

 

modules…………………………………………. 48  

6.5.4 Memories

 

and memory interfaces………………..52  

6.5.5 Security

 

and integrity modules……………………

.

5

4  

6.5.6 Analog…………………………………………………….

.

5

4  

6.5.7 Timers……………………………………………………..

 

62  

6.5.8 Communication

 

interfaces…………………………..62  

6.5.9 Human-machine

 

interfaces (HMI)……………….. 67  

6.6 DC-DC

 

Converter Operating Requirements……………. 67  

6.7 Ratings……………………………………………………………….70  

6.7.1 Thermal

 

handling ratings…………………………… 70  

6.7.2 Moisture

 

handling ratings…………………………..

.

7

0  

6.7.3 ESD

 

handling ratings………………………………… 70  

6.7.4 Voltage

 

and current operating ratings………….

.

7

1  

Pin Diagrams and Pin Assignments……………………………..

.

7

1  

7.1 KW36Z

 

Signal Multiplexing and Pin Assignments……. 71  

7.2 KW36Z

 

Pinouts…………………………………………………..

.

7

4  

7.3 KW35Z

 

Signal Multiplexing and Pin Assignments……. 75  

7.4 KW35Z

 

Pinouts…………………………………………………..

.

7

8  

7.5 Module

 

Signal Description Tables…………………………. 78  

7.5.1 Core

 

Modules……………………………………………79  

7.5.2 Radio

 

Modules…………………………………………. 79  

7.5.3 System

 

Modules………………………………………. 80  

7.5.4 Clock

 

Modules…………………………………………. 81  

7.5.5 Analog

 

Modules……………………………………….. 81  

7.5.6 Timer

 

Modules…………………………………………. 82  

7.5.7 Communication

 

Interfaces…………………………. 83  

7.5.8 Human-Machine

 

Interfaces(HMI)………………..

.

8

5  

Package Information………………………………………………….. 85  

8.1 Obtaining

 

package dimensions………………………………85  

Part identification………………………………………………………..85  

9.1 Description…………………………………………………………

.

8

5  

9.2 Format………………………………………………………………..86  

9.3 Fields…………………………………………………………………

 

86  

9.4 Example…………………………………………………………….

.

8

6  

Feature Descriptions………………………………………………….. 5  

2.1 Block

 

Diagram……………………………………………………..5  

2.2 Radio

 

features……………………………………………………..6  

2.3 Microcontroller

 

features……………………………………….. 7  

2.4 System

 

features………………………………………………….

.

8  

2.5 Peripheral

 

features……………………………………………….10  

2.6 Security

 

Features…………………………………………………14  

Transceiver Description……………………………………………….16  

3.1 Key

 

Specifications………………………………………………..16  

3.2 Channel

 

Map Frequency Plans ……………………………..16  

3.2.1 Channel

 

Plan for Bluetooth Low Energy………. 16  

3.2.2 Other

 

Channel Plans …………………………………18  

3.3 Transceiver

 

Functions…………………………………………..18  

Transceiver Electrical Characteristics…………………………… 19  

4.1 Radio

 

operating conditions…………………………………… 19  

4.2 Receiver

 

Feature Summary………………………………….

.

1

9  

4.3 Transmit

 

and PLL Feature Summary………………………22  

System and Power Management…………………………………. 26  

5.1 Power

 

Management……………………………………………..27  

5.1.1 DC-DC

 

Converter………………………………………27  

5.2 Modes

 

of Operation…………………………………………….. 27  

5.2.1 Power

 

modes…………………………………………… 27  

KW36Z/35Z Electrical Characteristics……………………………30  

6.1 AC

 

electrical characteristics…………………………………..30  

6.2 Nonswitching

 

electrical specifications……………………..30  

6.2.1 Voltage

 

and current operating requirements….30  

6.2.2 LVD

 

and POR operating requirements………… 31  

6.2.3 Voltage

 

and current operating behaviors……… 32  

6.2.4 Power

 

mode transition operating behaviors…..33  

6.2.5 Power

 

consumption operating behaviors……..

.

3

4  

6.2.6 Diagram:

 

Typical IDD_RUN operating  

3

4

5

7

6

behavior………………………………………………….. 40  

8

9

6.2.7 SoC

 

Power Consumption……………………………42  

6.2.8 Designing

 

with radiated emissions in mind…… 43  

6.2.9 Capacitance

 

attributes………………………………. 43  

6.3 Switching

 

electrical specifications…………………………..44  

6.3.1 Device

 

clock specifications………………………… 44  

6.3.2 General

 

switching specifications…………………

.

4

4  

6.4 Thermal

 

specifications…………………………………………. 45  

10 Revision History………………………………………………………… 87  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

3

NXP Semiconductors  

Introduction  

1 Introduction  

The KW36Z/35Z wireless microcontrollers (MCU), which includes the KW36Z and  

KW35Z families of devices, are highly integrated single-chip devices that enable  

Bluetooth Low Energy (Bluetooth LE) and Generic FSK connectivity for industrial and  

medical/healthcare embedded systems. The target applications center on wirelessly  

bridging the embedded world with mobile devices to enhance the human interface  

experience, share embedded data between devices and the cloud and enable wireless  

firmware updates.  

The KW36Z/35Z Wireless MCU integrates an Arm® Cortex®-M0+ CPU with up to  

512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE 5.0  

and Generic FSK modulations. The Bluetooth LE radio supports up to 8 simultaneous  

connections in any master/slave combination. The Medical Body Area Network  

(MBAN) frequencies from 2.36 to 2.4 GHz are also supported enabling wearable or  

implantable wireless medical devices.  

The KW36Z includes an integrated FlexCAN module enabling seamless integration  

into an industrial CAN communication network, enabling communication with external  

control and sensor monitoring devices over Bluetooth LE. The FlexCAN module can  

support CAN’s flexible data-rate (CAN FD) protocol for increased bandwidth and  

lower latency.  

The KW36Z/35Z devices can be used as a “BlackBox” modem in order to add  

Bluetooth LE or Generic FSK connectivity to an existing host MCU or MPU  

(microprocessor), or may be used as a standalone smart wireless sensor with embedded  

application where no host controller is required.  

The RF circuit of the KW36Z/35Z is optimized to require very few external  

components, achieving the smallest RF footprint possible on a printed circuit board.  

Extremely long battery life is achieved through the efficiency of code execution in the  

Cortex-M0+ CPU core and the multiple low power operating modes of the KW36Z/  

35Z. For power critical applications, an integrated DC-DC converter enables operation  

from a single coin cell or Li-ion battery with a significant reduction of peak receive and  

transmit current consumption.  

4

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

2 Feature

 

Descriptions  

This section provides a simplified block diagram and highlights the KW36Z/35Z  

features.  

2.1 Block

 

Diagram  

Arm Cortex M0+ Core  

32K Osc  

32M Osc  

IRC  

MCG  

DMA MUX  

4ch DMA  

Serial Wire Debug  

DAP MDM  

NVIC  

WIC  

4 MHz  

DWT  

MTB  

IRC  

32 kHz  

FLL  

IOPORT  

Unified Bus  

AHBLite  

AHBLite  

M2A  

M0  

Crossbar-Lite Switch (AXBS)  

S2  

S0  

S1  

SIM  

ADC  

BME  

PIT  

I2C x2  

GPIO  

Flash  

Controller  

64 KByte  

SRAM  

LTC(AESA)  

TRNG  

SMC  

RCM  

PMC  

CMP  

TPM x3  

LPTMR  

RTC  

LPUART x2  

SPI x2  

Flash  

AIPS-Lite  

256 KB  

FlexNVM  

256 KB  

FlexRAM  

8 KB  

Radio  

IPS  

APB  

VREF  

VDCDC_IN  

IPS  

DCDC  

CMT  

FlexCAN  

Figure 1. KW36 Detailed Block Diagram  

Arm Cortex M0+ Core  

32K Osc  

32M Osc  

IRC  

MCG  

DMA MUX  

4ch DMA  

Serial Wire Debug  

DAP MDM  

NVIC  

WIC  

4 MHz  

DWT  

MTB  

IRC  

32 kHz  

FLL  

IOPORT  

Unified Bus  

AHBLite  

AHBLite  

M2A  

M0  

Crossbar-Lite Switch (AXBS)  

S2  

S0  

S1  

SIM  

ADC  

BME  

PIT  

I2C x2  

GPIO  

Flash  

Controller  

64 KByte  

SRAM  

SMC  

RCM  

PMC  

CMP  

TPM x3  

LPTMR  

RTC  

LPUART  

SPI x2  

LTC(AESA)  

TRNG  

Flash  

AIPS-Lite  

512 KB  

Prg Acc RAM  

8 KB  

Radio  

IPS  

VREF  

APB  

VDCDC_IN  

DCDC  

CMT  

IPS  

Figure 2. KW35 Detailed Block Diagram  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

5

NXP Semiconductors  

Feature Descriptions  

2.2 Radio

 

features  

Operating frequencies:  

• 2.4

 

GHz ISM band (2400-2483.5 MHz)  

• Medical

 

Body Area Network (MBAN) 2360-2400 MHz  

Supported standards:  

• Bluetooth

 

Low Energy Version 5.0 compliant radio  

• Generic

 

FSK modulation supporting data rates up to 1 Mbit/s  

• Support

 

for up to 8 simultaneous Bluetooth LE hardware connections in any  

master, slave combination  

• Bluetooth

 

LE Application Profiles  

Receiver performance:  

• Receive

 

sensitivity of up to –95 dBm for Bluetooth LE  

• Receive

 

sensitivity of up to –99 dBm for a 250 kbit/s GFSK mode with a  

modulation index of 0.5. Receive sensitivity in Generic FSK modes depends on  

mode selection and data rate.  

Other features:  

• Programmable

 

transmit output power from –30 dBm to +5 dBm  

• 26

 

MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes  

• Bluetooth

 

Low Energy version 5.0 Link Layer hardware with 1 Mbit/s PHY  

support  

• Hardware

 

acceleration for Generic FSK packet processing  

• Generic

 

FSK modulation at 250, 500 and 1000 kbit/s  

• Supports

 

8 simultaneous Bluetooth LE connections in any master/slave  

combination  

• Enhanced

 

Bluetooth LE automatic deep sleep modes (DSM) supporting Slave  

Latency  

• Up

 

to 26 devices supported by whitelist in hardware  

• Up

 

to 8 private resolvable addresses supported in hardware  

• Supports

 

DMA capture of IQ data with sampling rate of up to 2 MHz, when using a  

32 MHz crystal  

• Integrated

 

on-chip balun  

• Single

 

ended bidirectional RF port shared by transmit and receive  

• Low

 

external component count  

• Supports

 

transceiver range extension using external PA and/or LNA  

6

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

2.3 Microcontroller

 

features  

Arm Cortex-M0+ CPU  

• Up

 

to 48 MHz CPU  

• As

 

compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline  

microarchitecture for reduced power consumption and improved architectural  

performance (cycles per instruction)  

• Supports

 

up to 32 interrupt request sources  

• Binary

 

compatible instruction set architecture with the Cortex-M0 core  

• Thumb

 

instruction set combines high code density with 32-bit performance  

• Serial

 

Wire Debug (SWD) reduces the number of pins required for debugging  

• Micro

 

Trace Buffer (MTB) provides lightweight program trace capabilities using  

system RAM as the destination memory  

Nested Vectored Interrupt Controller (NVIC)  

• 32

 

vectored interrupts, 4 programmable priority levels  

• Includes

 

a single non-maskable interrupt  

Wake-up Interrupt Controller (WIC)  

• Supports

 

interrupt handling when system clocking is disabled in low-power  

modes  

• Takes

 

over and emulates the NVIC behavior when correctly primed by the NVIC  

on entry to very-deep-sleep  

• A

 

rudimentary interrupt masking system with no prioritization logic signals for  

wake-up as soon as a non-masked interrupt is detected  

Debug Controller  

• Two-wire

 

Serial Wire Debug (SWD) interface  

• Hardware

 

breakpoint unit for 2 code addresses  

• Hardware

 

watchpoint unit for 2 data items  

• Micro

 

Trace Buffer for program tracing  

On-Chip Memory  

• Up

 

to 512 KB Flash  

• KW36Z

 

contains 256 KB program flash with ECC and 256 KB FlexNVM.  

• KW35Z

 

contains 512 KB program flash with ECC.  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

7

NXP Semiconductors  

Feature Descriptions  

• Flash

 

implemented as two equal blocks each of 256 KB block. Code can  

execute or read from one block while the other block is being erased or  

programmed on KW35Z only.  

• Firmware

 

distribution protection. Program flash can be marked execute-only  

on a per-sector (8 KB) basis to prevent firmware contents from being read by  

third parties.  

• 64

 

KB SRAM  

• KW36Z

 

contains 8 KB FlexRAM.  

• KW35Z

 

contains 8 KB program acceleration RAM.  

• Security

 

circuitry to prevent unauthorized access to RAM and flash contents  

through the debugger  

2.4 System

 

features  

Power Management Control Unit (PMC)  

• Programmable

 

power saving modes  

• Available

 

wake-up from power saving modes via internal and external sources  

• Integrated

 

Power-on Reset (POR)  

• Integrated

 

Low Voltage Detect (LVD) with reset (brownout) capability  

• Selectable

 

LVD trip points  

• Programmable

 

Low Voltage Warning (LVW) interrupt capability  

• Individual

 

peripheral clocks can be gated off to reduce current consumption  

• Internal

 

Buffered bandgap reference voltage  

• Factory

 

programmed trim for bandgap and LVD  

• 1

 

kHz Low-power Oscillator (LPO)  

DC-DC Converters  

• Internal

 

switched mode power supply supporting Buck and Bypass operating  

modes  

• Buck

 

operation supports external voltage sources of 2.1 V to 3.6 V  

• When

 

DC-DC is not used, the device supports an external voltage range of 1.5 V to  

3.6 V (1.5 – 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and  

VDD_1P5OUT_PMCIN pins. 1.71 – 3.6 V on VDD_0, VDD_1, and VDDA pins)  

• An

 

external inductor is required to support the Buck mode  

Direct Memory Access (DMA) Controller  

• All

 

data movement via dual-address transfers: read from source, write to  

destination  

8

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

• Programmable

 

source and destination addresses and transfer size  

• Support

 

for enhanced addressing modes  

• 4-channel

 

implementation that performs complex data transfers with minimal  

intervention from a host processor  

• Internal

 

data buffer, used as temporary storage to support 16- and 32-byte  

transfers  

• Connections

 

to the crossbar switch for bus mastering the data movement  

• Transfer

 

Control Descriptor (TCD) organized to support two-deep, nested transfer  

operations  

• 32-byte

 

TCD stored in local memory for each channel  

• An

 

inner data transfer loop defined by a minor byte transfer count  

• An

 

outer data transfer loop defined by a major iteration count  

• Channel

 

activation via one of three methods:  

• Explicit

 

software initiation  

• Initiation

 

via a channel-to-channel linking mechanism for continuous  

transfers  

• Peripheral-paced

 

hardware requests, one per channel  

• Fixed-priority

 

and round-robin channel arbitration  

• Channel

 

completion reported via optional interrupt requests  

• One

 

interrupt per channel, optionally asserted at completion of major iteration  

count  

• Optional

 

error terminations per channel and logically summed together to form  

one error interrupt to the interrupt controller  

• Optional

 

support for scatter/gather DMA processing  

• Support

 

for complex data structures  

DMA Channel Multiplexer (DMA MUX)  

• 4

 

independently selectable DMA channel routers  

• 2

 

periodic trigger sources available  

• Each

 

channel router can be assigned to 1 of the peripheral DMA sources  

COP Watchdog Module  

• Independent

 

clock source input (independent from CPU/bus clock)  

• Choice

 

between two clock sources  

• LPO

 

oscillator  

• Bus

 

clock  

System Clocks  

• Both

 

26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE  

and Generic FSK modes  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

9

NXP Semiconductors  

Feature Descriptions  

• MCU

 

can derive its clock either from the crystal reference oscillator or the  

Frequency-locked Loop (FLL)

1  

• 32.768

 

kHz crystal reference oscillator used to maintain precise Bluetooth Low  

Energy timing in low-power modes  

• Multipurpose

 

Clock Generator (MCG)  

• Internal

 

reference clocks — Can be used as a clock source for other on-chip  

peripherals  

• On-chip

 

RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy  

across full temperature range  

• On-chip

 

4 MHz oscillator with 5% accuracy across full temperature range  

• Frequency-locked

 

Loop (FLL) controlled by internal or external reference  

• 20

 

MHz to 48 MHz FLL output  

Unique Identifiers  

• 80-bit

 

Unique ID represents a unique identifier for each chip  

• 40-bit

 

unique Media Access Control (MAC) address, which can be used to build a  

unique 48-bit Bluetooth Low Energy MAC address  

2.5 Peripheral

 

features  

16-bit Analog-to-Digital Converter (ADC)  

• Linear

 

successive approximation algorithm with 16-bit resolution  

• Output

 

formatted in differential-ended 16-, 13-, 11-, and 9-bit mode  

• Output

 

formatted in single-ended 16-, 12-, 10-, and 8-bit mode  

• Single

 

or continuous conversion  

• Configurable

 

sample time and conversion speed/power  

• Conversion

 

rates in 16-bit mode with no averaging up to ~500Ksamples/sec  

• Input

 

clock selection  

• Operation

 

in low-power modes for lower noise operation  

• Asynchronous

 

clock source for lower noise operation  

• Selectable

 

asynchronous hardware conversion trigger  

• Automatic

 

compare with interrupt for less-than, or greater than, or equal to  

programmable value  

• Temperature

 

sensor  

• Battery

 

voltage measurement  

• Hardware

 

average function  

• Selectable

 

voltage reverence  

• Self-calibration

 

mode  

1. Clock

 

options can have restrictions based on the chosen SoC configuration.  

10  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

High-Speed Analog Comparator (CMP)  

• 6-bit

 

DAC programmable reference generator output  

• Up

 

to eight selectable comparator inputs; each input can be compared with any  

input by any polarity sequence  

• Selectable

 

interrupt on rising edge, falling edge, or either rising or falling edges of  

comparator output  

• Two

 

performance modes:  

• Shorter

 

propagation delay at the expense of higher power  

• Low-power,

 

with longer propagation delay  

• Operational

 

in all MCU power modes except VLLS0 mode  

Voltage Reference(VREF1)  

• Programmable

 

trim register with 0.5 mV steps, automatically loaded with factory  

trimmed value upon reset  

• Programmable

 

buffer mode selection:  

• Off  

• Bandgap

 

enabled/standby (output buffer disabled)  

• High-power

 

buffer mode (output buffer enabled)  

• 1.2

 

V output at room temperature  

• VREF_OUT

 

output signal  

Low-power Timer (LPTMR)  

• One

 

channel  

• Operation

 

as timer or pulse counter  

• Selectable

 

clock for prescaler/glitch filter  

• 1

 

kHz internal LPO  

• External

 

low-power crystal oscillator  

• Internal

 

reference clock  

• Configurable

 

glitch filter or prescaler  

• Interrupt

 

generated on timer compare  

• Hardware

 

trigger generated on timer compare  

• Functional

 

in all power modes  

Timer/PWM (TPM)  

• TPM0:

 

4 channels, TPM1 and TPM2: 2 channels each  

• Selectable

 

source clock  

• Programmable

 

prescaler  

• 16-bit

 

counter supporting free-running or initial/final value, and counting is up or  

up-down  

• Input

 

capture, output compare, and edge-aligned and center-aligned PWM modes  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

11  

NXP Semiconductors  

Feature Descriptions  

• Input

 

capture and output compare modes  

• Generation

 

of hardware triggers  

• TPM1

 

and TPM2: Quadrature decoder with input filters  

• Global

 

time base mode shares single time base across multiple TPM instances  

Programmable Interrupt Timer (PIT)  

• Up

 

to 2 interrupt timers for triggering ADC conversions  

• 32-bit

 

counter resolution  

• Clocked

 

by bus clock frequency  

Real-Time Clock (RTC)  

• 32-bit

 

seconds counter with 32-bit alarm  

• Can

 

be invalidated on detection of tamper detect  

• 16-bit

 

prescaler with compensation  

• Register

 

write protection  

• Hard

 

Lock requires MCU POR to enable write access  

• Soft

 

lock requires POR or software reset to enable write/read access  

• Capable

 

of waking up the system from low-power modes  

Inter-Integrated Circuit (I

2

C)  

• Two

 

channels  

• Compatible

 

with I2C bus standard and SMBus Specification Version 2 features  

• Up

 

to 400 kHz operation  

• Multi-master

 

operation  

• Software

 

programmable for one of 64 different serial clock frequencies  

• Programmable

 

slave address and glitch input filter  

• Interrupt

 

driven byte-by-byte data transfer  

• Arbitration

 

lost interrupt with automatic mode switching from master to slave  

• Calling

 

address identification interrupt  

• Bus

 

busy detection broadcast and 10-bit address extension  

• Address

 

matching causes wake-up when processor is in low-power mode  

LPUART  

• One

 

channel (2 channels on KW36Z)  

• Full-duplex

 

operation  

• Standard

 

mark/space Non-return-to-zero (NRZ) format  

• 13-bit

 

baud rate selection with fractional divide of 32  

• Programmable

 

8-bit or 9-bit data format  

• Programmable

 

1 or 2 stop bits  

12  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

• Separately

 

enabled transmitter and receiver  

• Programmable

 

transmitter output polarity  

• Programmable

 

receive input polarity  

• 13-bit

 

break character option  

• 11-bit

 

break character detection option  

• Two

 

receiver wake-up methods:  

• Idle

 

line wake-up  

• Address

 

mark wake-up  

• Address

 

match feature in receiver to reduce address mark wake-up ISR overhead  

• Interrupt

 

or DMA driven operation  

• Receiver

 

framing error detection  

• Hardware

 

parity generation and checking  

• Configurable

 

oversampling ratio to support from 1/4 to 1/32 bit-time noise  

detection  

• Operation

 

in low-power modes  

• Hardware

 

Flow Control RTSCTS  

• Functional

 

in Stop/VLPS modes  

• Break

 

detect supporting LIN  

Serial Peripheral Interface (SPI)  

• Two

 

independent SPI channels  

• Master

 

and slave mode  

• Full-duplex,

 

three-wire synchronous transfers  

• Programmable

 

transmit bit rate  

• Double-buffered

 

transmit and receive data registers  

• Serial

 

clock phase and polarity options  

• Slave

 

select output  

• Control

 

of SPI operation during wait mode  

• Selectable

 

MSB-first or LSB-first shifting  

• Support

 

for both transmit and receive by DMA  

Carrier Modulator Timer (CMT)  

• Four

 

modes of operation  

• Time;

 

with independent control of high and low times  

• Baseband  

• Frequency

 

shift key (FSK)  

• Direct

 

software control of CMT_IRO signal  

• Extended

 

space operation in time, baseband, and FSK modes  

• Selectable

 

input clock divider  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

13  

NXP Semiconductors  

Feature Descriptions  

• Interrupt

 

on end of cycle  

• Ability

 

to disable CMT_IRO signal and use as timer interrupt  

General Purpose Input/Output (GPIO)  

• Hysteresis

 

and configurable pull up device on all input pins  

• Independent

 

pin value register to read logic level on digital pin  

• All

 

GPIO pins can generate IRQ and wake-up events  

• Configurable

 

drive strength on some output pins  

• GPIO

 

can be configured to function as a interrupt driven keyboard scanning matrix  

• In

 

the 48-pin package there are a total of 25 digital pins  

• In

 

the 40-pin package there are a total of 18 digital pins  

FlexCAN

(for KW36Z only)  

• Full

 

implementation of the CAN with Flexible Data Rate (CAN FD) protocol  

specification and CAN protocol specification, Version 2.0 B  

• Flexible

 

Message Buffers (MBs); there are total 32 MBs of 8 bytes data length  

each, configurable as Rx or Tx, all supporting standard and extended messages  

• Programmable

 

clock source to the CAN Protocol Interface, either peripheral clock  

or oscillator clock  

• Capability

 

to select priority between mailboxes and Rx FIFO during matching  

process  

• Powerful

 

Rx FIFO ID filtering, capable of matching incoming IDs against either  

128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual  

masking capability  

2.6 Security

 

Features  

Advanced Encryption Standard Accelerator(AES-128 Accelerator)  

The Advanced Encryption Standard Accelerator (AESA) module is a standalone  

hardware coprocessor capable of accelerating the 128-bit advanced encryption standard  

(AES) cryptographic algorithms.  

The AESA engine supports the following cryptographic features.  

LTC includes the following features:  

• Cryptographic

 

authentication  

• Message

 

Authentication Codes (MAC)  

14  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Feature Descriptions  

• Cipher-based

 

MAC (AES-CMAC)  

• Extended

 

cipher block chaining message authentication code (AES-  

XCBC-MAC)  

• Auto

 

padding  

• Integrity

 

Check Value(ICV) checking  

• Authenticated

 

encryption algorithms  

• Counter

 

with CBC-MAC (AES-CCM)  

• Symmetric

 

key block ciphers  

• AES

 

(128-bit keys)  

• Cipher

 

modes:  

• AES-128

 

modes  

• Electronic

 

Codebook (ECB)  

• Cipher

 

Block Chaining (CBC)  

• Counter

 

(CTR)  

• Secure

 

scan  

True Random Number Generator (TRNG)  

True Random Number Generator (TRNG) is a hardware accelerator module that  

constitutes a high-quality entropy source.  

• TRNG

 

generates a 512-bit (4x 128-bit) entropy as needed by an entropy-  

consuming module, such as a deterministic random number generator.  

• TRNG

 

output can be read and used by a deterministic pseudo-random number  

generator (PRNG) implemented in software.  

• TRNG-PRNG

 

combination achieves NIST-compliant true randomness and  

cryptographic-strength random numbers using the TRNG output as the entropy  

source.  

• A

 

fully FIPS 180 compliant solution can be realized using the TRNG together  

with a FIPS-compliant deterministic random number generator and the SoC-level  

security.  

Flash Memory Protection  

The on-chip flash memory controller enables the following useful features:  

• Program

 

flash protection scheme prevents accidental program or erase of stored  

data.  

• Automated,

 

built-in, program and erase algorithms with verify.  

• Read

 

access to one program flash block is possible while programming or erasing  

data in the other program flash block.  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

15  

NXP Semiconductors  

Transceiver Description  

3 Transceiver

 

Description  

• Direct

 

Conversion Receiver (Zero IF)  

• Constant

 

Envelope Transmitter  

• 2.36

 

GHz to 2.483 GHz PLL Range  

• Low

 

Transmit and Receive Current Consumption  

• Low

 

BOM  

3.1 Key

 

Specifications  

KW36Z/35Z meets or exceeds all Bluetooth Low Energy version 5.0 performance  

specifications. The key specifications for the KW36Z/35Z are:  

Frequency Band:  

• ISM

 

Band: 2400 to 2483.5 MHz  

• MBAN

 

Band: 2360 to 2400 MHz  

Bluetooth Low Energy version 5.0 modulation scheme:  

• Symbol

 

rate: 1000 kbit/s  

• Modulation:

 

GFSK  

• Receiver

 

sensitivity: –95 dBm, typical  

• Programmable

 

transmitter output power: –30 dBm to +5 dBm  

Generic FSK modulation scheme:  

• Symbol

 

rate: 250, 500 and 1000 kbit/s  

• Modulation(s):

 

GFSK (modulation index = 0.32, 0.5, 0.7 and 1.0, BT =0.3, 0.5, and  

0.7), FSK and MSK  

• Receiver

 

Sensitivity: Mode and data rate dependent. –99 dBm typical for GFSK  

(r=250 kbit/s, BT = 0.5, h = 0.5)  

3.2 Channel

 

Map Frequency Plans  

16  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Transceiver Description  

3.2.1 Channel

 

Plan for Bluetooth Low Energy  

This section describes the frequency plan / channels associated with 2.4 GHz ISM and  

MBAN bands for Bluetooth Low Energy.  

2.4 GHz ISM Channel numbering:  

• Fc=2402

 

+ k * 2 MHz, k=0,………,39.  

MBAN Channel numbering:  

• Fc=2360

 

+ k in MHz, for k=0,…..,39  

where k is the channel number.  

Table 1.

 

2.4 GHz ISM and MBAN frequency plan and channel designations  

2.4 GHz ISM

1  

MBAN

2  

2.4GHz ISM + MBAN  

Channel  

Channel  

Freq (MHz)  

2402  

2404  

2406  

2408  

2410  

2412  

2414  

2416  

2418  

2420  

2422  

2424  

2426  

2428  

2430  

2432  

2434  

2436  

2438  

2440  

2442  

2444  

2446  

2448  

Channel  

Freq (MHz)  

2360  

2361  

2362  

2363  

2364  

2365  

2366  

2367  

2368  

2369  

2370  

2371  

2372  

2373  

2374  

2375  

2376  

2377  

2378  

2379  

2380  

2381  

2382  

2383  

Freq (MHz)  

2390  

2391  

2392  

2393  

2394  

2395  

2396  

2397  

2398  

2402  

2404  

2406  

2408  

2410  

2412  

2414  

2416  

2418  

2420  

2422  

2424  

2426  

2428  

2430  

0

1

0

1

28  

29  

30  

31  

32  

33  

34  

35  

36  

0

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10  

11  

12  

13  

14  

15  

16  

17  

18  

19  

20  

21  

22  

23  

10  

11  

12  

13  

14  

15  

16  

17  

18  

19  

20  

21  

22  

23  

1

2

3

4

5

6

7

8

9

10  

11  

12  

13  

14  

Table continues on the next page…  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

17  

NXP Semiconductors  

Transceiver Description  

Table 1.

 

2.4 GHz ISM and MBAN frequency plan and channel designations (continued)  

2.4 GHz ISM

1  

MBAN

2  

2.4GHz ISM + MBAN  

Channel  

Channel  

Freq (MHz)  

2450  

2452  

2454  

2456  

2458  

2460  

2462  

2464  

2466  

2468  

2470  

2472  

2474  

2476  

2478  

2480  

Channel  

24  

Freq (MHz)  

2384  

2385  

2386  

2387  

2388  

2389  

2390  

2391  

2392  

2393  

2394  

2395  

2396  

2397  

2398  

2399  

Freq (MHz)  

2432  

2434  

2436  

2438  

2440  

2442  

2444  

2446  

2448  

2450  

2452  

2454  

2456  

2476  

2478  

2480  

24  

25  

26  

27  

28  

29  

30  

31  

32  

33  

34  

35  

36  

37  

38  

39  

15  

16  

17  

18  

19  

20  

21  

22  

23  

24  

25  

26  

27  

37  

38  

39  

25  

26  

27  

28  

29  

30  

31  

32  

33  

34  

35  

36  

37  

38  

39  

1. ISM

 

frequency of operation divs from 2400.0 MHz to 2483.5 MHz  

2. Per

 

FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.  

3.2.2 Other

 

Channel Plans  

The RF synthesizer can be configured to use any channel frequency between 2.36 and  

2.487 GHz.  

3.3 Transceiver

 

Functions  

Receive  

The receiver architecture is Zero IF (ZIF) where the received signal after passing  

through RF front end is down-converted to a baseband signal. The signal is filtered and  

amplified before it is fed to analog-to-digital converter. The digital signal then  

decimates to a baseband clock frequency before it digitally processes, demodulates and  

passes on to packet processing/link-layer processing.  

18  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Transmit  

The transmitter transmits GFSK/FSK modulation having power and channel selection  

adjustment per user application. After the channel of operation is determined, coarse  

and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal  

lock is established, the modulated buffered signal is routed to a multi-stage amplifier  

for transmission..  

4 Transceiver

 

Electrical Characteristics  

4.1 Radio

 

operating conditions  

Table 2.

 

Radio operating conditions  

Characteristic  

Symbol  

f

in  

Min  

2.360  

–40  

Typ  

—

Max  

2.480  

105  

Unit  

GHz  

°C  

Input Frequency  

Ambient Temperature Range  

Maximum RF Input Power  

T

A  

25  

—

P

max  

f

ref  

—

10  

dBm  

Crystal Reference Oscillator Frequency  

26 MHz or 32 MHz  

1

1. The

 

recommended crystal accuracy is

 

40 ppm including initial accuracy, mechanical, temperature, and aging factors.  

4.2 Receiver

 

Feature Summary  

Table 3.

 

Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise  

noted)  

Characteristic

1  

Symbol  

I

pdn  

Min.  

—

Typ.  

200  

6.3  

Max.  

1000  

—

Unit  

nA  

Supply current power down on VDD_RFx supplies  

Supply current Rx On with DC-DC converter enable  

(Buck; V

DCDC_IN

= 3.6 V, VDD_1P5_buck=1.5 V)

,

2  

I

Rxon  

—

mA  

Supply current Rx On with DC-DC converter disabled  

(Bypass)

2  

I

Rxon  

—

17.2  

—

mA  

Input RF Frequency  

f

in  

2.360  

—

—

2.4835  

—

GHz  

dBm  

dBm  

dB  

GFSK Rx Sensitivity(250 kbit/s GFSK-BT=0.5, h=0.5)  

Bluetooth LE Rx Sensitivity

3  

SENS

GFSK  

SENS

BLE  

NF

HG  

–99  

–95  

7.5  

—

—

Noise Figure for maximum gain mode @ typical  

sensitivity  

—

—

Table continues on the next page…  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

19  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Table 3.

 

Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise  

noted) (continued)  

Characteristic

1  

Symbol  

RSSI

Range  

RSSI

Res  

Min.  

–100  

—

Typ.  

—

Max.  

5

5  

—

2

Unit  

dBm  

dB  

Receiver Signal Strength Indicator Range

4  

Receiver Signal Strength Indicator Resolution  

Typical RSSI variation over frequency  

Typical RSSI variation over temperature  

Narrowband RSSI accuracy

6  

1

–2  

—

dB  

–2  

—

2

dB  

RSSI

Acc  

–3  

—

3

dB  

Bluetooth LE Co-channel Interference (Wanted signal at  

–67 dBm, BER <0.1%. Measurement resolution 1  

MHz).  

–7  

dB  

Adjacent/Alternate Channel Performance

7  

Bluetooth LE Adjacent +/–1 MHz Interference offset  

(Wanted signal at –67 dBm, BER <0.1%. Measurement  

resolution 1 MHz.)  

SEL

BLE, 1 MHz  

SEL

BLE, 2 MHz  

SEL

BLE, 3 MHz  

SEL

BLE, 4+ MHz  

—

—

—

—

2

—

—

—

—

dB  

dB  

dB  

dB  

Bluetooth LE Adjacent +/–2 MHz Interference offset  

(Wanted signal at –67 dBm, BER <0.1%. Measurement  

resolution 1 MHz.)  

43  

50  

50  

Bluetooth LE Alternate +/–3 MHz Interference offset  

(Wanted signal at –67 dBm, BER <0.1%. Measurement  

resolution 1 MHz.)  

Bluetooth LE Alternate ≥ +/–4 MHz Interference offset  

(Wanted signal at –67 dBm, BER <0.1%. Measurement  

resolution 1 MHz.)  

Intermodulation Performance  

Bluetooth LE Intermodulation with continuous wave  

interferer at

 

3 MHz and modulated interferer is at  

MHz (Wanted signal at –67 dBm, BER<0.1%.)  

—

—

–23  

–24  

—

—

dBm  

dBm  

6

Bluetooth LE Intermodulation with continuous wave  

interferer at

 

5 MHz and modulated interferer is at

 

10  

MHz (Wanted signal at –67 dBm, BER<0.1%.)  

Blocking Performance  

Bluetooth LE Out of band blocking from 30 MHz to 1000  

MHz and 4000 MHz to 5000 MHz (Wanted signal at –67  

dBm, BER<0.1%. Interferer continuous wave signal.)

8  

—

—

–2  

—

—

—

—

dBm  

dBm  

Bluetooth LE Out of band blocking from 1000 MHz to  

2000 MHz and 3000 MHz to 4000 MHz (Wanted signal  

at –67 dBm, BER<0.1%. Interferer continuous wave  

signal.)  

–8.4  

Bluetooth LE Out of band blocking from 2001 MHz to  

2339 MHz and 2484 MHz to 2999 MHz (Wanted signal  

at –67 dBm, BER<0.1%. Interferer continuous wave  

signal.)

9  

—

—

–17  

—

—

—

—

dBm  

dBm  

Bluetooth LE Out of band blocking from 5000 MHz to  

12750 MHz (Wanted signal at –67 dBm, BER<0.1%.  

Interferer continuous wave signal.)

9  

10  

Table continues on the next page…  

20  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Table 3.

 

Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise  

noted) (continued)  

Characteristic

1  

Symbol  

Min.  

Typ.  

Max.  

Unit  

Spurious Emission < 1.6 MHz offset (Measured with  

100 kHz resolution and average detector. Device  

transmit on RF channel with center frequency fc and  

spurious power measured in 1 MHz at RF frequency f),  

where |f-fc|< 1.6 MHz  

—

—

–54  

—

dBc  

Spurious Emission > 2.5 MHz offset (Measured with  

100 kHz resolution and average detector. Device  

transmit on RF channel with center frequency fc and  

spurious power measured in 1 MHz at RF frequency f),  

where |f-fc|> 2.5 MHz

10  

—

—

–70  

—

dBc  

1. All

 

the Rx parameters are measured at the KW36Z/35Z RF pins.  

2. Transceiver

 

power consumption.  

3. Measured

 

at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.  

4. Narrow-band

 

RSSI mode.  

5. With

 

RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.  

6. With

 

one point calibration over frequency and temperature.  

7. Bluetooth

 

LE adjacent and alternate selectivity performance is measured with modulated interference signals.  

8. Exceptions

 

allowed for carrier frequency sub harmonics.  

9. Exceptions

 

allowed for carrier frequency harmonics.  

10. Exceptions

 

allowed for twice the reference clock frequency(fref) multiples.  

Table 4.

 

Receiver Specifications with Generic FSK Modulations  

Adjacent/Alternate Channel Selectivity (dB)

1  

Modulation  

Type  

Data  

Rate  

(kbit/s)  

Channel  

BW (kHz)

 

Sensitivity signal  

Typical  

Desired Interferer Interferer Interferer Interferer  

Co-  

channel  

at –/+1*  

channel  

BW  

at –/+ 2*  

channel  

BW  

at –/+ 3*  

channel  

BW  

at –/+ 4*  

channel  

BW  

(dBm)  

level  

(dBm)  

offset  

offset  

offset  

offset  

GFSK BT =  

0.5, h=0.5  

1000  

500  

2000  

1000  

500  

–95  

–97  

–99  

–89  

–92  

–93  

–97  

–98  

–99  

–91  

–93  

–95  

–96  

–97  

–67  

–85  

–85  

–67  

–85  

–85  

–85  

–85  

–85  

–85  

–85  

–85  

–85  

–85  

43  

40  

30  

10  

22  

20  

45  

40  

30  

40  

35  

30  

44  

40  

50  

50  

40  

38  

31  

25  

50  

50  

40  

46  

46  

40  

53  

50  

55  

55  

50  

42  

37  

30  

57  

55  

50  

53  

50  

40  

57  

55  

50  

55  

50  

47  

42  

34  

60  

55  

50  

55  

53  

50  

60  

55  

–7  

–7  

250  

–7  

GFSK, BT =  

0.5, h=0.3  

1000  

500  

1000  

800  

–10  

–10  

–13  

–7  

250  

500  

GFSK, BT =  

0.5, h=0.7  

1000  

500  

2000  

1000  

600  

–7  

250  

–7  

GMSK  

BT=0.3  

1000  

500  

1600  

800  

–8  

–7  

250  

500  

–7  

GMSK, BT =

 

1000  

2000  

1000  

–7  

0.7  

500  

–7  

Table continues on the next page…  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

21  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Table 4.

 

Receiver Specifications with Generic FSK Modulations  

(continued)  

Adjacent/Alternate Channel Selectivity (dB)

1  

Modulation  

Type  

Data  

Rate  

(kbit/s)  

Channel  

BW (kHz)

 

Sensitivity signal  

Typical  

Desired Interferer Interferer Interferer Interferer  

Co-  

channel  

at –/+1*  

channel  

BW  

at –/+ 2*  

channel  

BW  

at –/+ 3*  

channel  

BW  

at –/+ 4*  

channel  

BW  

(dBm)  

level  

(dBm)  

offset  

offset  

offset  

offset  

250  

1000  

500  

600  

3000  

1600  

800  

–99  

–96  

–97  

–99  

–96  

–97  

–98  

–85  

–85  

–85  

–85  

–85  

–85  

–85  

30  

43  

43  

35  

45  

40  

35  

40  

53  

50  

45  

55  

45  

45  

50  

60  

60  

55  

55  

50  

45  

50  

63  

60  

55  

59  

50  

50  

–7  

–7  

–8  

–7  

–8  

–8  

–8  

Generic  

MSK  

250  

GFSK  

BT=0.5, h=1  

1000  

500  

3000  

1400  

800  

250  

1. Selectivity

 

measured with an unmodulated blocker except for GFSK BT=0.5, h=0.5 1 Mbit/s and GFSK BT=0.5, h=0.32 1  

Mbit/s. The desired signal is set at –85 dBm.  

4.3 Transmit

 

and PLL Feature Summary  

• Supports

 

constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN  

frequency bands  

• Fast

 

PLL Lock time: < 25 µs  

• Reference

 

Frequency:  

• 26

 

MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK  

modes  

Table 5.

 

Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise  

noted)  

Characteristic

1  

Symbol  

I

pdn  

Min.  

—

Typ.  

200  

5.7  

Max.  

—

Unit  

nA  

Supply current power down on VDD_RFx supplies  

Supply current Tx On with P

RF

= 0 dBm and DC-DC  

converter enabled (Buck; VDD

DCDC_in

= 3.6 V,  

VDD_1P5_buck=1.5 V)

,

2  

I

Txone  

—

—

mA  

Supply current Tx On with P

RF

= 0 dBm and DC-DC  

converter disabled (Bypass)

2  

I

Txond  

—

—

16  

—

—

mA  

mA  

Supply current Tx On with P

RF

= +3.5 dBm and DC-DC  

converter enabled (Buck; VDD

DCDC_in

= 3.6 V,  

VDD_1P5_buck=1.5 V)

2  

I

TX3.5dBm  

6.9  

Supply current Tx On with P

RF

= +3.5 dBm and DC-DC  

converter disabled (Bypass)

2  

I

TX3.5dBmb  

—

19  

—

mA  

Table continues on the next page…  

22  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Table 5.

 

Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise  

noted) (continued)  

Characteristic

1  

Symbol  

Min.  

Typ.  

Max.  

Unit  

Supply current Tx On with P

RF

= +5 dBm and DC-DC  

converter enabled (Buck; VDD

DCDC_in

= 3.6 V,  

VDD_1P5_buck=1.55 V, LDO-HF bumped)

2

,

3  

I

TX5dBm  

—

8.0  

—

mA  

Supply current Tx On with P

RF

= +5 dBm and DC-DC  

converter disabled (Bypass, LDO-HF bumped)

2

,

3  

I

TX5dBmb  

—

21  

—

mA  

Output RF Frequency  

f

RFout  

2.360  

—

—

+5  

2.4835  

—

GHz  

dBm  

dBm  

dBm  

dB  

Maximum RF Output Power; LDO-HF bumped

4  

Maximum RF Output power, nominal power supply

5  

Minimum RF Output power, nominal power supply

5  

RF Output power control range  

P

RF,maxV  

P

RF,maxn  

P

RF,minn  

P

RFCR  

—

+3.5  

–30  

34  

—

—

—

—

—

Bluetooth LE Tx Output Spectrum 20dB BW  

TXBW

BLE  

Δ

f1

avg,BLE  

1.0  

—

MHz  

kHz  

Bluetooth LE average frequency deviation using a  

00001111 modulation sequence  

250  

220  

Bluetooth LE average frequency deviation using a  

01010101 modulation sequence  

Δ

f2

avg,BLE  

kHz  

Bluetooth LE RMS FSK Error  

FSK

err BLE  

,

3%  

3

Bluetooth LE Maximum Deviation of the Center  

Frequency

6  

F

cdev,BLE  

—

—

—

—

kHz  

dBm  

dBm  

Bluetooth LE Adjacent Channel Transmit Power at 2  

MHz offset

7  

P

RF2MHz,BLE  

P

RF3MHz,BLE  

—

—

–55  

–59  

Bluetooth LE Adjacent Channel Transmit Power at >= 3  

MHz offset

7  

Bluetooth LE Frequency Hopping Support  

YES  

–46  

Second Harmonic of Transmit Carrier Frequency (P

out  

=

TXH2  

TXH3  

—

—

—

—

dBm/MHz  

dBm/MHz  

,

8  

P

RF,max  

)

Third Harmonic of Transmit Carrier Frequency (P

out  

=

–58  

8

P

RF,max  

)

1. All

 

the Tx parameters are measured at test hardware SMA connector.  

2. Transceiver

 

power consumption.  

3. VDD_RFx

 

shall be equal to or higher than 1.55 V to support a TX Pout of +5 dBm.  

4. Measured

 

at KW36Z/35Z RF pins, with BB_LDO_HF_TRIM=1.44 V.  

5. Measured

 

at the KW36Z/35Z RF pins.  

6. Maximum

 

drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.  

7. Measured

 

at P

out

= +5 dBm and recommended Tx match.  

8. Harmonic

 

levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of  

matching components. Additional harmonic margin using a third matching component (1x shunt capacitor) is possible.  

Transmit PA driver output as a function of the PA_POWER[5:0] field when measured  

at the IC pins is as follows:  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

23  

NXP Semiconductors  

Transceiver Electrical Characteristics  

Figure 3. TX Pout (dBm) as function TX-PA Power Code for default LDO-HF  

Table 6.

 

Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF  

TX Pout (dBm)

1  

PA_POWER[5:0]  

T = –40 °C  

–30.1  

–24.0  

–17.9  

–14.5  

–12.0  

–10.1  

–8.5  

T = 25 °C  

–31.1  

–25.0  

–19.0  

–15.6  

–13.1  

–11.2  

–9.6  

T = 105 °C  

–32.6  

–26.4  

–20.4  

–17.0  

–14.5  

–12.6  

–11.0  

–9.7  

1

2

4

6

8

10  

12  

14  

16  

18  

20  

22  

24  

26  

28  

30  

32  

–7.2  

–8.3  

–6.1  

–7.2  

–8.6  

–5.1  

–6.2  

–7.6  

–4.2  

–5.3  

–6.7  

–3.4  

–4.5  

–5.9  

–2.7  

–3.8  

–5.2  

–2.0  

–3.1  

–4.5  

–1.4  

–2.5  

–3.9  

–0.8  

–1.9  

–3.3  

–0.3  

–1.4  

–2.8  

Table continues on the next page…  

24  

NXP Semiconductors  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

Transceiver Electrical Characteristics  

Table 6.

 

Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF  

(continued)  

TX Pout (dBm)

1  

PA_POWER[5:0]  

T = –40 °C  

0.2  

T = 25 °C  

–1.0  

–0.5  

–0.1  

0.3  

T = 105 °C  

–2.4  

–1.9  

–1.5  

–1.1  

–0.7  

–0.3  

0.0  

34  

36  

38  

40  

42  

44  

46  

48  

50  

52  

54  

56  

58  

60  

62  

0.6  

1.1  

1.5  

1.9  

0.7  

2.2  

1.1  

2.6  

1.4  

2.9  

1.8  

0.3  

3.2  

2.1  

0.6  

3.5  

2.4  

0.9  

3.7  

2.6  

1.2  

3.9  

2.9  

1.5  

4.2  

3.1  

1.7  

4.4  

3.3  

1.9  

4.5  

3.5  

2.1  

1. Tx

 

continuous wave power output at the RF pins with the recommended matching components mounted on PCB.  

Figure 4. TX Pout (dBm) as a function of TX-PA Power Code for LDO-HF bumped  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

25  

NXP Semiconductors  

System and Power Management  

Table 7.

 

Transmit Output Power as a function of PA_POWER[5:0] with LDO-HF Bumped  

TX Pout (dBm)

1  

PA_POWER[5:0]  

T = –40 °C  

–28.5  

–22.4  

–16.4  

–12.9  

–10.4  

–8.5  

–6.9  

–5.6  

–4.4  

–3.4  

–2.5  

–1.7  

–0.9  

–0.3  

0.4  

T = 25 °C  

–29.6  

–23.4  

–17.5  

–13.9  

–11.5  

–9.5  

–8.0  

–6.6  

–5.5  

–4.5  

–3.6  

–2.8  

–2.0  

–1.4  

–0.7  

–0.1  

0.3  

T = 105 °C  

–30.4  

–24.2  

–18.3  

–14.8  

–12.3  

–10.4  

–8.8  

–7.5  

–6.3  

–5.3  

–4.4  

–3.6  

–2.9  

–2.2  

–1.6  

–1.0  

–0.5  

0.0  

1

2

4

6

8

10  

12  

14  

16  

18  

20  

22  

24  

26  

28  

30  

32  

34  

36  

38  

40  

42  

44  

46  

48  

50  

52  

54  

56  

58  

60  

62  

1.0  

1.4  

2.0  

0.9  

2.4  

1.3  

0.4  

2.9  

1.8  

0.9  

3.3  

2.2  

1.3  

3.7  

2.6  

1.7  

4.1  

3.0  

2.1  

4.5  

3.4  

2.5  

4.8  

3.7  

2.8  

5.2  

4.0  

3.1  

5.5  

4.4  

3.4  

5.8  

4.6  

3.7  

6.0  

4.9  

4.0  

6.3  

5.2  

4.2  

6.5  

5.4  

4.5  

6.7  

5.6  

4.7  

1. Tx

 

continuous wave power output at the RF pins with the recommended matching components mounted on PCB.  

5 System

 

and Power Management  

26  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

System and Power Management  

5.1 Power

 

Management  

The KW36Z/35Z includes internal power management features that can be used to  

control the power usage. The power management of the KW36Z/35Z includes Power  

Management Controller (PMC) and a DC-DC converter which can operate in a buck  

or bypass configuration. The PMC is designed such that the RF radio remains in state-  

retention while the core is in various stop modes. It makes sure that the device can  

stay in low current consumption mode while the RF radio can wake-up quick enough  

for communication.  

5.1.1 DC-DC

 

Converter  

The features of the DC-DC converter include the following:  

• Single

 

inductor, multiple outputs.  

• Buck

 

mode (pin selectable; CFG=VDCDC_IN).  

• Continuous

 

or pulsed operation (hardware/software configurable).  

• Power

 

switch input to allow external control of power up, and to select DC-DC  

bypass mode in which all the SoC power supplies (see

Table 3

) are externally  

provided.  

• Output

 

signal to indicate power stable. Purpose is for the rest of the chip to be  

used as a POR.  

• Scaled

 

battery output voltage suitable for SAR ADC utilization.  

• Internal

 

oscillator for support when the reference oscillator is not present.  

5.2 Modes

 

of Operation  

The Arm Cortex-M0+ core in the KW36Z/35Z has three primary modes of operation:  

Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop  

mode. Wait modes are similar to Arm sleep modes. Stop modes are similar to Arm  

deep sleep modes. The very low-power run (VLPR) operation mode can drastically  

reduce runtime power when the maximum bus frequency is not required to handle the  

application needs.  

The WFI instruction invokes both wait and stop modes. The primary modes are  

augmented in a number of ways to provide lower power based on application needs.  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

27  

NXP Semiconductors  

System and Power Management  

5.2.1 Power

 

modes  

The power management controller (PMC) provides multiple power options to allow the  

user to optimize power consumption for the level of functionality needed.  

Depending on the stop requirements of the user application, various stop modes are  

available that provide state retention, partial power down, or full power down of certain  

logic and/or memory. I/O states are held in all modes of operation. The following table  

compares the various power modes available.  

For each run mode, there is a corresponding wait and stop mode. Wait modes are  

similar to Arm sleep modes. Stop modes (VLPS, STOP) are similar to Arm sleep deep  

mode. The very-low-power run (VLPR) operating mode can drastically reduce runtime  

power when the maximum bus frequency is not required to handle the application  

needs.  

The three primary modes of operation are run, wait, and stop. The WFI instruction  

invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System  

Control Register. The primary modes are augmented in a number of ways to provide  

lower power based on application needs.  

Table 8.

 

Power modes (At 25 deg C)  

Power mode  

Description  

CPU  

Radio  

recovery  

method  

Normal Run (all  

Allows maximum performance of chip.  

—

Radio can be active  

peripherals clock off)  

Normal Wait – via WFI

 

Allows peripherals to function, while allowing CPU to  

go to sleep reducing power.  

Interrupt  

Interrupt  

Interrupt  

Normal Stop – via  

WFI  

Places chip in static state. Lowest power mode that  

retains all registers while maintaining LVD protection.  

PStop2 (Partial Stop

 

Core and system clocks are gated. Bus clock  

2)  

remains active. Masters and slaves clocked by bus  

clock remain in Run or VLPRun mode. The clock  

generators in MCG and the on-chip regulator in the  

PMC also remain in Run or VLPRun mode.  

PStop1 (Partial Stop

 

Core, system clocks, and bus clock are gated. All  

Interrupt  

—

1)  

bus masters and slaves enter Stop mode. The clock  

generators in MCG and the on-chip regulator in the  

PMC also remain in Run or VLPRun mode.  

VLPR (Very Low-  

power Run) (all  

peripherals off)  

Reduced frequency (1 MHz) Flash access mode,  

regulator in low-power mode, LVD off. Internal  

oscillator can provide low-power 4 MHz source for  

core. (Values @2 MHz core/ 1 MHz bus and flash,  

module off, execution from flash).  

Radio operation is possible  

only when DC-DC is  

configured for continuous  

mode.

1

However, there may  

be insufficient MIPS with a 4  

MHz MCU to support much in  

the way of radio operation.  

Biasing is disabled when DC-DC is configured for  

continuous mode in VLPR/W  

Table continues on the next page…  

28  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

NXP Semiconductors  

System and Power Management  

Table 8.

 

Power modes (At 25 deg C) (continued)  

Power mode  

Description  

CPU  

Radio  

recovery  

method  

VLPW (Very Low-  

Similar to VLPR, with CPU in sleep to further reduce  

Interrupt  

power Wait) – via WFI

 

power. (Values @4 MHz core/ 1 MHz bus, module  

(all peripherals off)  

off)  

Biasing is disabled when DC-DC is configured for  

continuous mode in VLPR/W  

VLPS (Very Low-  

Places MCU in static state with LVD operation off.  

Interrupt  

power Stop) via WFI

 

Lowest power mode with ADC and all pin interrupts  

functional. LPTMR, RTC, CMP can be operational.  

Biasing is disabled when DC-DC is configured for  

continuous mode in VLPS.  

LLS3 (Low Leakage

 

State retention power mode. LLWU, LPTMR, RTC,  

Wake-up  

Interrupt  

Radio SOG is in state  

retention in LLSx. The  

Bluetooth LE/Generic FSK  

DSM

2

logic can be active  

using the 32 kHz clock  

Stop)  

CMP can be operational. All of the radio Sea of  

Gates(SOG) logic is in state retention.  

LLS2 (Low Leakage

 

State retention power mode. LLWU, LPTMR, RTC,  

Wake-up  

Interrupt  

Stop)  

CMP can be operational. 16 KB or 32 KB of  

programmable RAM can be powered on. All of the  

radio SOG logic is in state retention.  

VLLS3 (Very Low  

Leakage Stop3)  

Full SRAM retention. LLWU, LPTMR, RTC, CMP can  

be operational. All of the radio SOG logic is in state  

retention.  

Wake-up  

Reset  

Radio SOG is in state  

retention in VLLS3/2. The  

Bluetooth LE/Generic FSK  

DSM logic can be active  

using the 32 kHz clock.  

VLLS2 (Very Low  

Leakage Stop2)  

Partial SRAM retention. 16 KB or 32 KB of  

programmable RAM can be powered on. LLWU,  

LPTMR, RTC, CMP can be operational. All of the  

radio SOG logic is in state retention.  

Wake-up  

Reset  

VLLS1 (Very Low  

Leakage Stop1) with

 

file remains powered for customer-critical data.  

RTC + 32 kHz OSC  

All SRAM powered off. The 32-byte system register  

Wake-up  

Reset  

Radio operation not  

supported. The Radio SOG is  

power-gated in VLLS1. Radio  

state is lost at VLLS1 and  

lower power states.  

LLWU, LPTMR, RTC, CMP can be operational.  

Radio logic is power gated.  

VLLS1 (Very Low  

Leakage Stop1) with

 

file remains powered for customer-critical data.  

All SRAM powered off. The 32-byte system register  

Wake-up  

Reset  

LPTMR + LPO  

LLWU, LPTMR, RTC, CMP can be operational.  

VLLS0 (Very Low  

Leakage Stop0) with  

Brown-out Detection  

VLLS0 is not supported with DC-DC.  

Wake-up  

Reset  

Radio operation not  

supported. The Radio digital  

is power-gated in VLLS0.  

The 32-byte system register file remains powered for  

customer-critical data. Disable all analog modules in  

PMC and retains I/O state and DGO state. LPO  

disabled, POR brown-out detection enabled, Pin  

interrupt only. Radio logic is power gated.  

VLLS0 (Very Low  

Leakage Stop0)  

without Brown-out  

Detection  

VLLS0 is not supported with DC-DC buck  

configuration but is supported with bypass  

configuration.  

Wake-up  

Reset  

The 32-byte system register file remains powered for  

customer-critical data. Disable all analog modules in  

PMC and retains I/O state and DGO state. LPO  

disabled, POR brown-out detection disabled, Pin  

interrupt only. Radio logic is power gated.  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

29  

NXP Semiconductors  

KW36Z/35Z Electrical Characteristics  

1. Biasing

 

is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power savings  

over use of Run/Wait/Stop.  

2. DSM

 

refers to Radio’s deep sleep mode. DSM does not refer to the Arm sleep deep mode.  

6 KW36Z/35Z

 

Electrical Characteristics  

6.1 AC

 

electrical characteristics  

Unless otherwise specified, propagation delays are measured from the 50% to the 50%  

point, and rise and fall times are measured at the 20% and 80% points, as shown in the  

following figure.  

High  

Low  

V

IH  

80%  

50%  

20%  

Input Signal  

Midpoint1  

V

IL  

Fall Time  

Rise Time  

The midpoint is V

IL

+ (V

IH

– V

IL

) / 2  

Figure 5. Input signal measurement reference  

All digital I/O switching characteristics, unless otherwise specified, assume that the  

output pins have the following characteristics.  

• C

L

=30 pF loads  

• Slew

 

rate disabled  

• Normal

 

drive strength  

6.2 Nonswitching

 

electrical specifications  

6.2.1 Voltage

 

and current operating requirements  

Table 9.

 

Voltage and current operating requirements  

Symbol  

V

DD  

Description  

Min.  

1.71  

Max.  

3.6  

Unit  

V

Notes  

Supply voltage  

V

DD_1P5  

DCDC V

DD_1P5

output pin  

1.425  

3.6  

V

1

Table continues on the next page…  

30  

NXP Semiconductors  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

KW36Z/35Z Electrical Characteristics  

Table 9.

 

Voltage and current operating requirements (continued)  

Symbol  

Description  

Min.  

1.71  

–0.1  

–0.1  

Max.  

3.6  

Unit  

V

Notes  

V

DDA  

Analog supply voltage  

V

DD

– V

DDA

V

DD

-to-V

DDA

differential voltage  

V

SS

– V

SSA

V

SS

-to-V

SSA

differential voltage  

0.1  

V

0.1  

V

V

IH  

Input high voltage  

• 2.7

 

V ≤ V

DD

≤ 3.6 V  

• 1.7

 

V ≤ V

DD

≤ 2.7 V  

0.7 × V

DD  

—

—

V

V

0.75 × V

DD  

V

IL  

Input low voltage  

• 2.7

 

V ≤ V

DD

≤ 3.6 V  

• 1.7

 

V ≤ V

DD

≤ 2.7 V  

—

—

0.35 × V

DD  

0.3 × V

DD  

V

V

V

HYS  

I

ICIO  

Input hysteresis  

0.06 × V

DD  

–3  

—

—

V

IO pin negative DC injection current — single pin  

• V

IN

< V

SS

–0.3V  

2

mA  

I

ICcont  

Contiguous pin DC injection current —regional limit,  

includes sum of negative injection currents of 16  

contiguous pins  

–25  

—

mA  

• Negative

 

current injection  

V

ODPU  

V

RAM  

Open drain pullup voltage level  

V

DD  

1.2  

V

DD  

—

V

V

3

V

DD

voltage required to retain RAM  

1. This

 

limit applies in any DCDC mode.  

2. All

 

I/O pins are internally clamped to V

SS

through an ESD protection diode. There is no diode connection to V

DD

. If V

IN  

greater than V

IO_MIN

(= V

SS

–0.3 V) is observed, then there is no need to provide current limiting resistors at the pads.  

If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting  

resistor is calculated as R = (V

IO_MIN

– V

IN

)/|I

ICIO

|.  

3. Open

 

drain outputs must be pulled to V

DD  

.

6.2.2 LVD

 

and POR operating requirements  

Table 10.

 

V

DD

supply LVD and POR operating requirements  

Symbol Description  

Min.  

0.8  

Typ.  

1.1  

Max.  

1.5  

Unit  

V

Notes  

V

POR  

Falling V

DD

POR detect voltage  

V

POR_VDD_

V

DD_1P5

POR threshold  

1.25  

1.31  

1.37  

V

1P5  

V

LVDH  

Falling low-voltage detect threshold — high  

2.48  

2.56  

2.64  

V

range (LVDV = 01)  

Low-voltage warning thresholds — high range  

• Level

 

1 falling (LVWV = 00)  

• Level

 

2 falling (LVWV = 01)  

1

V

LVW1H  

V

LVW2H  

2.62  

2.72  

2.70  

2.80  

2.78  

2.88  

V

V

Table continues on the next page…  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

31  

NXP Semiconductors  

KW36Z/35Z Electrical Characteristics  

Table 10.

 

V

DD

supply LVD and POR operating requirements (continued)  

Symbol Description  

V

LVW3H

• Level

 

3 falling (LVWV = 10)  

V

LVW4H  

Min.  

Typ.  

Max.  

Unit  

Notes  

2.82  

2.90  

2.98  

V

• Level

 

4 falling (LVWV = 11)  

2.92  

—

3.00  

60  

3.08  

—

V

V

HYSH  

V

LVDL  

Low-voltage inhibit reset/recover hysteresis —  

high range  

mV  

Falling low-voltage detect threshold — low  

range (LVDV=00)  

1.54  

1.60  

1.66  

V

Low-voltage warning thresholds — low range  

• Level

 

1 falling (LVWV = 00)  

1

V

LVW1L  

V

LVW2L  

V

LVW3L  

V

LVW4L  

1.74  

1.84  

1.94  

2.04  

—

1.80  

1.90  

2.00  

2.10  

40  

1.86  

1.96  

2.06  

2.16  

—

V

V

• Level

 

2 falling (LVWV = 01)  

• Level

 

3 falling (LVWV = 10)  

V

• Level

 

4 falling (LVWV = 11)  

V

V

HYSL  

Low-voltage inhibit reset/recover hysteresis —  

low range  

mV  

V

BG  

t

LPO  

Bandgap voltage reference  

0.97  

900  

1.00  

1.03  

V

Internal low-power oscillator period — factory  

trimmed  

1000  

1100  

μs  

1. Rising

 

thresholds are falling threshold + hysteresis voltage  

6.2.3 Voltage

 

and current operating behaviors  

Table 11.

 

Voltage and current operating behaviors  

Symbol  

Description  

Min.  

Max.  

Unit  

Notes  

V

OH  

Output high voltage — Normal drive pad (except  

RESET_b)  

1

,

2  

V

DD

– 0.5  

V

DD

– 0.5  

V

DD

– 0.35  

—

—

—

V

V

V

• 2.7

 

V ≤ V

DD

≤ 3.6 V, I

OH

= –5 mA  

• 1.71

 

V ≤ V

DD

≤ 2.7 V, I

OH

= –2.5 mA  

• 1.71

 

V ≤ V

DD

≤ 2.7 V, I

OH

= –1 mA  

V

OH  

Output high voltage — High drive pad (except  

RESET_b)  

1

,

2  

V

DD

– 0.5  

V

DD

– 0.5  

—

—

—

V

V

• 2.7

 

V ≤ V

DD

≤ 3.6 V, I

OH

= –20 mA  

• 1.71

 

V ≤ V

DD

≤ 2.7 V, I

OH

= –10 mA  

I

OHT  

V

OL  

Output high current total for all ports  

Output low voltage — Normal drive pad  

• 2.7

 

V ≤ V

DD

≤ 3.6 V, I

OL

= 5 mA  

• 1.71

 

V ≤ V

DD

≤ 2.7 V, I

OL

= 2.5 mA  

100  

mA  

1

1

—

—

0.5  

0.5  

V

V

V

OL  

Output low voltage — High drive pad  

Table continues on the next page…  

32  

NXP Semiconductors  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

KW36Z/35Z Electrical Characteristics  

Table 11.

 

Voltage and current operating behaviors (continued)  

Symbol  

Description  

• 2.7

 

V ≤ V

DD

≤ 3.6 V, I

OL

= 20 mA  

Min.  

Max.  

Unit  

Notes  

—

0.5  

V

• 1.71

 

V ≤ V

DD

≤ 2.7 V, I

OL

= 10 mA  

—

0.5  

V

I

OLT  

I

IN  

Output low current total for all ports  

—

—

100  

500  

mA  

nA  

Input leakage current (per pin) for full temperature  

range  

3

I

IN  

I

IN  

Input leakage current (per pin) at 25 °C  

—

—

0.025  

5

μA  

μA  

3

3

Input leakage current (total all pins) for full  

temperature range  

R

PU  

Internal pullup resistors  

20  

50  

kΩ  

4

1. PTB0-1

 

and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by  

the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.  

2. The

 

reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When  

configured as a GPIO output, it acts as a pseudo open drain output.  

3. Measured

 

at V

DD

= 3.6 V.  

4. Measured

 

at V

DD

supply voltage = V

DD

min and V

input

= V

SS  

.

6.2.4 Power

 

mode transition operating behaviors  

All specifications except t

POR

and VLLSx

→

RUN recovery times in the following  

table assume this clock configuration:  

• CPU

 

and system clocks = 48 MHz  

• Bus

 

and flash clock = 24 MHz  

• FEI

 

clock mode  

POR and VLLSx

→

RUN recovery use FEI clock mode at the default CPU and system  

frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.  

Table 12.

 

Power mode transition operating behaviors  

Symbol  

Description  

Max.  

Unit  

Notes  

t

POR  

After a POR event, amount of time from the point V

DD  

reaches 1.8 V to execution of the first instruction across the  

operating temperature range of the chip.  

300  

μs  

1

• VLLS0

 

→

RUN  

169.0  

168.9  

97.3  

μs  

μs  

μs  

• VLLS1

 

→

RUN  

• VLLS2

 

→

RUN  

Table continues on the next page…  

MKW36Z/35Z Data Sheet, Rev. 8, 05/2020  

33  

NXP Semiconductors  

KW36Z/35Z Electrical Characteristics  

Table 12.

 

Power mode transition operating behaviors (continued)  

Symbol  

Description  

Max.  

97.3  

6.3  

Unit  

Notes  

• VLLS3

 

→

RUN  

μs  

• LLS

 

→

RUN  

• VLPS

 

→

RUN  

• STOP

 

→

RUN  

μs  

6.2  

μs  

6.2  

μs  

1. Normal

 

boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300  

µs spec when 1) VDD_1P5 < 1.6 V at 25 °C and 125 °C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8 V. For the bypass mode special case  

where VDD_1P5 = VDD_1P8, TPOR did not meet the 300 µs maximum spec when the supply slew rate <=100 V/s.  

6.2.5 Power

 

consumption operating behaviors  

Table 13.

 

Power consumption operating behaviors – Bypass Mode  

Symbol  

Description  

Typ.  

Max.  

Unit  

Notes  

1

I

DDA  

Analog supply current  

—

See note  

mA  

I

DD_RUNCO_C

Run mode current in compute operation – 48 MHz  

2

,

3  

core / 24 MHz flash / bus disabled, LPTMR running  

M

using LPO clock at 1kHz, CoreMark benchmark code  

executing from flash at 3.0 V  

6.80  

4.05  

8.41  

4.98  

mA  

mA  

I

DD_RUNCO

Run mode current in compute operation – 48 MHz  

core / 24 MHz flash / bus clock disabled, code of  

while(1) loop executing from flash at 3.0 V  

3

,

4  

3

,

4  

I

DD_RUN  

Run mode current – 48 MHz core / 24 MHz bus and  

flash, all peripheral clocks disabled, code of while(1)  

loop executing from flash at 3.0 V  

5.00