NXP-Semicon-MMRF1306HSR5
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Document Number: MMRF1306H
Rev. 1, 8/2014
Freescale Semiconductor
T
e
chnical Data
RF Power LDMOS Transistors
High Ruggedness N
–
–
Channel
MMRF1306HR5
MMRF1306HSR5
Enhancement
–
–
Mode Lateral MOSFE
T
s
These high ruggedness devices are designed for use in high VSWR CW or
pulse applications, such as H
F
,
V
H
F
,
a
nd low
–
–
band UHF radar and high power
radio communications. They are unmatched input and output designs allowing
wide frequency utilization from 1.8 to 600 MHz.
1.8–600 MHz, 1250 W CW, 50 V
WIDEBAND
RF POWER LDMOS TRANSISTORS
Typical Performance: V
DD
= 50 Vdc, I
DQ
= 100 mA
P
(W)
f
G
(dB)
D
(%)
out
ps
Signal Type
(MHz)
Pulse
1250 Peak
230
24.0
74.0
(100
sec, 20% Duty Cycle)
CW
1250 CW
230
22.9
74.6
Application Circuits
(1)
— Typical Performance
Frequency
(MHz)
P
out
(W)
G
(dB)
ps
D
NI
–
-1230H
–
-4S
MMRF1306HR5
Signal Type
(%)
81
85
84
80
78
30
66
27
40
CW
CW
1300
1300
1250
1100
1250
225
27
26
81.36
CW
27
87.5
–
–
108
144
–
–
148
170
–
–
230
352
CW
24
CW
26
DVB
–
–
T
25
NI
–
-1230S
–
-4S
MMRF1306HSR5
Pulse
(200
sec,
1250
21.5
20% Duty Cycle)
352
500
CW
CW
1150
1000
20.5
18
68
58
1. Contact
your local Freescale sales office for additional information on specific
circuit designs.
Load Mismatch/Ruggedness
Gate A
Gate B
Drain A
Drain B
3
4
1
2
Frequency
(MHz)
P
(W)
Test
Voltage
out
Signal Type
VSWR
Result
230
Pulse
>65:1 at all
1500 Peak
(3 dB
50
No Device
Degradation
(100
sec, 20%
Phase Angles
Duty Cycle)
Overdrive)
(
T
o
p View)
Features
Unmatched Input and Output Allowing Wide Frequency Range Utilization
Device can be used Single
–
–
Ended or in a Push
–
–
Pull Configuration
Qualified Up to a Maximum of 50 V
DD
Operation
Characterized from 30 V to 50 V for Extended Power Range
Suitable for Linear Application with Appropriate Biasing
Note: The backside of the package is the
source terminal for the transistors.
Figure 1. Pin Connections
Integrated ESD Protection with Greater Negative Gate
–
–
Source Voltage Range
for Improved Class C Operation
Characterized with Series Equivalent Large
–
–
Signal Impedance Parameters
In
T
a
pe and Reel. R5 Suffix = 50 Units, 56 mm
T
a
pe Width, 13
–
–
inch Reel.
Freescale Semiconductor, Inc., 2013–2014. All rights reserved.
Table 1. Maximum Ratings
Rating
Symbol
Value
–
–
0.5, +133
–
–
6.0, +10
—
6
5 to +150
150
Unit
Vdc
Vdc
C
Drain
–
–
Source Voltage
V
DSS
Gate
–
–
Source Voltage
V
GS
Storage
T
e
mperature Range
Case Operating
T
e
mperature
T
stg
T
C
C
D
T
o
tal Device Dissipation @ T
= 25
C
P
1333
6.67
W
W/
C
C
Derate above 25
C
(1)
Operating Junction
T
e
mperature
T
J
225
C
Table 2. Thermal Characteristics
(2)
Characteristic
Symbol
Value
Unit
Thermal Resistance, Junction to Case
R
0.15
C/W
JC
CW: Case
T
e
mperature 63
C, 1250 W CW, I
= 100 mA, 230 MHz
DQ
Thermal Impedance, Junction to Case
Z
0.027
C/W
JC
Pulse: Case
T
e
mperature 66
C, 1250 W Pulse, 100
sec Pulse Width, 20% Duty Cycle,
I
= 100 mA, 230 MHz
DQ
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22
–
–
A
1
14)
Machine Model (per EIA/JESD22
–
–
A
1
15)
Charge Device Model (per JESD22
–
–
C101)
2, passes 3500 V
B, passes 250 V
IV, passes 4000 V
Table 4. Electrical Characteristics
(T =
25
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
(3)
Off Characteristics
Gate
–
–
Source Leakage Current
I
—
133
—
—
—
—
—
1
Adc
Vdc
GSS
(V =
5 Vdc, V
= 0 Vdc)
GS
DS
Drain
–
–
Source Breakdown Voltage
(V =
0 Vdc, I
= 100 mA)
V
—
10
20
(BR)DSS
GS
D
Zero Gate Voltage Drain Leakage Current
(V =
50 Vdc, V
= 0 Vdc)
I
Adc
Adc
DSS
DSS
DS
GS
Zero Gate Voltage Drain Leakage Current
I
—
(V =
100 Vdc, V
= 0 Vdc)
DS
GS
On Characteristics
(3)
Gate Threshold Voltage
(V =
10 Vdc, I
= 1776
Adc)
V
V
1.7
1.9
—
2.2
2.2
2.7
2.9
—
Vdc
Vdc
Vdc
S
GS(th)
GS(Q)
DS(on)
DS
D
Gate Quiescent Voltage
(V =
50 Vdc, I
= 100 mAdc, Measured in Functional
T
e
st)
DD
D
(3)
Drain
–
–
Source On
–
–
V
oltage
(V =
10 Vdc, I
= 2 Adc)
V
0.15
28.0
GS
D
Forward Transconductance
(V =
10 Vdc, I
= 30 Adc)
g
—
—
fs
DS
D
(3)
Dynamic Characteristics
Reverse Transfer Capacitance
(V =
50 Vdc
30 mV(rms)ac @ 1 MHz, V
= 0 Vdc)
DS
C
—
—
—
2.8
185
562
—
—
—
pF
pF
pF
rss
GS
Output Capacitance
(V =
50 Vdc
30 mV(rms)ac @ 1 MHz, V
= 0 Vdc)
DS
C
oss
GS
Input Capacitance
C
iss
(V =
50 Vdc, V
= 0 Vdc
30 mV(rms)ac @ 1 MHz)
DS
GS
1. Continuous
use at maximum temperature will affect MTT
F
.
2. Refer
to AN1955,
Thermal Measurement Methodology of RF Power Amplifiers.
Go to http://www.freescale.com/rf.
Select Documentation/Application Notes
–
–
A
N1955.
3. Each
side of device measured separately.
(continued)
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
2
Table 4. Electrical Characteristics
(T =
25
C unless otherwise noted)
(continued)
A
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests
(In Freescale
T
e
st Fixture, 50 ohm system) V
= 50 Vdc, I
= 100 mA, P
= 1250 W Peak (250 W Avg.),
DD
DQ
out
f = 230 MHz, 100
sec Pulse Width, 20% Duty Cycle
Power Gain
G
23.0
72.5
—
24.0
74.0
— 1 4
26.0
—
dB
%
ps
D
Drain Efficiency
Input Return Loss
IRL
— 1 0
dB
Table 5. Load Mismatch/Ruggedness
(In Freescale
T
e
st Fixture, 50 ohm system) I
= 100 mA
DQ
Frequency
(MHz)
P
out
(W)
Signal Type
VSWR
Test Voltage, V
Result
No Device Degradation
DD
230
Pulse
>65:1 at all
1500 Peak
50
(100
sec, 20% Duty Cycle)
Phase Angles
(3 dB Overdrive)
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
3
– – –
–
C22
C23
C24
C13
C10
C11
C12
C21
COAX1
COAX3
R1
L3
C16
L1
C5
C4
C17
C2
C3
C15
C14
C18
C19
L2
C20
C1
L4
R2
COAX2
C6
COAX4
C25
C9
C8
C7
C26
C27
C28
— —
Figure 2. MMRF1306HR5(HSR5) 230 MHz Production Test Circuit Component Layout — Pulse
Table 6. MMRF1306HR5(HSR5) 230 MHz Production Test Circuit Component Designations and Values — Pulse
Part
Description
Part Number
ATC100B200JT500XT
ATC100B270JT500XT
27291SL
Manufacturer
C1
20 pF Chip Capacitor
ATC
C2, C3, C5
C4
27 pF Chip Capacitors
ATC
0.8
–
–
8.0 pF Variable Capacitor, Gigatrim
22
F
,
3
5 V
T
a
ntalum Capacitors
0.1
F Chip Capacitors
220 nF Chip Capacitors
1000 pF Chip Capacitors
43 pF Chip Capacitor
Johanson
Kemet
AVX
C6, C10
C7, C11
C8, C12
T491X226K035AT
CDR33BX104AKYS
C1812C224K5RACTU
ATC100B102JT50XT
ATC100B430JT500XT
MIN02
–
–
002EC750J
–
–
F
ATC100B241JT200XT
ATC100B6R2BT500XT
MCGPR63V477M13X26
–
–
RH
UT
–
–
141C
–
–
25
Kemet
ATC
C9, C13, C21, C25
C14
ATC
C15
75 pF Metal Mica
CDE
C16, C17, C18, C19
C20
240 pF Chip Capacitors
6.2 pF Chip Capacitor
ATC
ATC
C22, C23, C24, C26, C27, C28
470
F
,
6
3 V Electrolytic Capacitors
Multicomp
Micro
–
–
Coax
Coilcraft
Coilcraft
Vishay
Arlon
Coax1, 2, 3, 4
L1, L2
25
Semi Rigid Coax, 2.2
Shield Length
5 nH Inductors
A02TKLC
L3, L4
6.6 nH Inductors
GA3093
–
–
ALC
R1, R2
PCB
10
Chip Resistors
CRCW120610R0JNEA
AD255A
0.030
,
= 2.55
r
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
4
+
+
+
+
+
+
+
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
2000
1000
66
Ideal
P3dB = 61.9 dBm (1553 W)
P2dB = 61.7 dBm (1472 W)
C
iss
65
64
63
62
61
60
59
C
oss
100
10
1
P1dB = 61.3 dBm
(1333 W)
Actual
C
rss
V
= 50 Vdc, I
= 100 mA, f = 230 MHz
DQ
Pulse Width = 100
sec, 20% Duty Cycle
DD
Measured with
30 mV(rms)ac @ 1 MHz
= 0 Vdc
V
GS
0
10
20
30
40
50
35
36
37
38
39
40
41
42
V
, DRAIN
–
–
SOURCE VOLTAGE (VOLTS)
P ,
INPUT POWER (dBm) PEAK
in
DS
Note:
Each side of device measured separately.
Figure 5. Output Power versus Input Power
Figure 4. Capacitance versus Drain
–
-Source Voltage
26
25
24
23
22
21
20
26
25
24
23
22
90
I
= 100 mA, f = 230 MHz
DQ
V
= 50 Vdc, I
= 100 mA, f = 230 MHz
DQ
DD
Pulse Width = 100
sec, 20% Duty Cycle
Pulse Width = 100
sec, 20% Duty Cycle
80
70
60
50
50 V
21
20
19
18
G
ps
45 V
40 V
35 V
40
30
17
16
D
V
= 30 V
DD
100
1000
, OUTPUT POWER (WATTS) PEAK
2000
0
200
400
600
800
1000 1200
1400 1600
P
P
, OUTPUT POWER (WATTS) PEAK
out
out
Figure 7. Power Gain versus Output Power
Figure 6. Power Gain and Drain Efficiency
versus Output Power
26
25
24
23
22
90
80
70
60
50
40
30
20
90
— 3 0
_
C
25
_
C
45 V
50 V
40 V
35 V
80
70
60
50
40
V
= 30 V
DD
85
_
C
T
=
–
–
30
_
C
C
25
_
C
G
ps
85
_
C
21
20
19
I
= 100 mA, f = 230 MHz
V
= 50 Vdc, I
= 100 mA, f = 230 MHz
DQ
Pulse Width = 100
sec, 20% Duty Cycle
30
20
DQ
DD
Pulse Width = 100
sec, 20% Duty Cycle
D
0
200
400
600
800
1000
1200 1400
1600
100
1000
2000
P
, OUTPUT POWER (WATTS) PEAK
P
, OUTPUT POWER (WATTS) PEAK
out
out
Figure 9. Power Gain and Drain Efficiency versus
Output Power
Figure 8. Drain Efficiency versus Output Power
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
6
TYPICAL CHARACTERISTICS
9
8
10
10
7
6
5
10
10
10
4
10
90
110
130
150
170
190
210
230
250
T , JUNCTION TEMPERATURE (
C)
J
This above graph displays calculated MTTF in hours when the device
is operated at V
= 50 Vdc, P
= 1250 W CW, and
= 74.6%.
DD
out
D
Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
Figure 10. MTTF versus Junction Temperature — CW
V
= 50 Vdc, I
= 100 mA, P
= 1250 W Peak
DQ out
DD
f
Z
Z
load
source
MHz
230
1.29 + j3.54
2.12 + j2.68
Z
Z
=
=
T
e
st circuit impedance as measured from
gate to gate, balanced configuration.
source
T
e
st circuit impedance as measured from
drain to drain, balanced configuration.
load
Device
Under
Test
Output
Matching
Network
Input
Matching
Network
+
—
50
50
—
+
load
Z
Z
source
Figure 11. Series Equivalent Test Circuit Source and Load Impedance — 230 MHz Pulse
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
7
V
= 50 Vdc, I
= 100 mA
DQ
DD
f
Z
Z
load
source
(MHz)
(
)
(
)
(1)
(1)
(1)
1.8
34.4 + j192.0
5.00 – j4.00
27
40
12.5 + j7.00
5.75 + j5.06
4.04 + j5.93
2.20 + j6.70
2.30 + j6.90
2.30 + j7.00
1.60 + j5.00
1.33 + j3.90
1.29 + j3.54
0.98 + j1.45
0.29 + j1.47
7.00 + j0.70
5.39 + j2.62
4.89 + j2.95
4.90 + j2.90
4.10 + j2.50
4.40 + j3.60
3.90 + j1.50
3.50 + j2.50
2.12 + j2.68
1.82 + j2.05
1.79 + j1.80
81.36
88
98
108
144
175
230
352
500
1. Simulated
data.
Z
=
T
e
st circuit impedance as measured from
gate to gate, balanced configuration.
source
Z
load
=
T
e
st circuit impedance as measured from
drain to drain, balanced configuration.
Device
Under
Test
Output
Matching
Network
Input
Matching
Network
+
—
50
50
—
+
load
Z
Z
source
Figure 12. Source and Load Impedances Optimized for IRL, Power and Efficiency — Push
–
-Pull
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
8
PACKAGE DIMENSIONS
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
9
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
10
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
11
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
12
PRODUCT DOCUMENTATION
Refer to the following documents to aid your design process.
Application Notes
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
EB212: Using Data Sheet Impedances for RF LDMOS Devices
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
1
Dec. 2013
Aug. 2014
Initial Release of Data Sheet
Application circuit table added and band of operation updated to 1.8–600 MHz to reflect performance of
device, p. 1
MMRF1306HR5 MMRF1306HSR5
RF Device Data
Freescale Semiconductor, Inc.
13
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e
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E
2013–2014 Freescale Semiconductor, Inc.
Document Number: MMRF1306H
Rev. 1, 8/2014
Mouser Electronics
Authorized Distributor
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