NXP-Semicon-NTP52101G0JTZ

NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

Rev. 3.3 — 3 July 2020  

Product data sheet  

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1 General

 

description  

Designed as an MCU replacement in various gaming and lighting applications, this NFC  

tag adds connectivity and increases flexibility while saving energy and lowering the bill of  

materials.  

NXP’s NTAG 5 switch lets designers eliminate the MCU in selected gaming and lighting  

applications and other cost sensitive designs, for added functionality, connectivity,  

and efficiency at a lower cost. Operating at 13.56 MHz, it is an NFC Forum-compliant  

(customer development board is NFC Forum certified – Certification ID: 58626)  

contactless tag that can be read by any NFC-enabled device at close range and by  

an ISO/IEC 15693-enabled industrial reader over a longer range. Easy configuration  

supports a range of control functions, and the integrated originality check lets the user  

verify an end product’s authenticity.  

PWM  

EEPROM  

GPIO  

energy harvesting  

data  

event detection  

energy  

energy  

aaa-034219  

Figure 1.ꢀNTAG 5 switch overview  

In some lighting and gaming applications, NTAG 5 switch enables simple and cost-  

effective designs without a microcontroller. It implements multiplexed pins, offering  

general-purpose I/O (GPIO) and pulse width modulation (PWM) as well as NFC field  

detection. The characteristics of the PWM or GPIO signal can be configured through the  

NFC interface. These features can be used to switch on/off and control motor speed or  

LED brightness.  

Support for ISO/IEC 15693 lets the NTAG 5 switch communicate securely in two ways —  

with powerful industrial readers, at a range of up to 60 cm and with NFC-enabled devices  

within proximity range. This duality makes it possible for the device to be calibrated and  

parameterized automatically while in the factory and then, when put to use in the field,  

safely communicate with contactless devices such as NFCenabled smartphones.  

The tag’s 512 bytes of memory can be divided into three areas, and each area can use  

a different protection level, varying from no protection to 32-/64-bit, password-protected  

read/write access. Different parties in the value chain can have their own dedicated  

memory areas for storing access data.  

NXP Semiconductors  

NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

The NTAG 5 switch comes with pre-programmed proof-of-origin functionality to verify  

authenticity. The elliptic curve cryptography (ECC) based originality signature can be  

locked or reprogrammed by the customer.  

The NTAG 5 is a powerhouse, harvesting the energy from an NFC Reader, it can operate  

without a battery. Better yet, with its configurable output voltage, it can power a circuit, a  

sensor network and even charge a super capacitor wireless.  

NTP5210  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

2 Features

 

and benefits  

•

Reading distance with long-range reader > 60 cm (> 25 inches)  

•

Flexible operation with PWM/GPIO interface  

•

Flexible split between three open and/or protected memory areas  

•

Ensured authenticity of product through value chain  

•

Interoperable data exchange according to NFC Forum standards  

•

Energy-efficient design with reduced bill of material  

•

Interoperable and high performance NFC interface  

–

and NFC Forum

compliant  

–

64-bit Unique IDentifier  

•

Reliable and robust memory  

–

512 bytes (4096 bits) user EEPROM on top of configuration memory  

–

40 years data retention  

–

Write endurance of 1 000 000 cycles  

•

Configurable contact interface  

–

One configurable event detection pin  

–

Two GPIOs  

–

Two Pulse Width Modulation (PWM) channels as multiplexed GPIOs and/or ED pin  

–

1.62 V to 5.5 V supply voltage  

•

Scalable security for access and data protection  

–

Disable NFC interface temporarily  

–

NFC PRIVACY mode  

–

Read-only protection as defined in NFC Forum Type 5 Tag Specification  

–

Full, read-only, or no memory access based on 32-bit password  

–

Optional 64-bit password protection  

–

ECC-based reprogrammable originality signature  

•

Low-power budget application support  

–

Energy harvesting with configurable output voltage up to 30 mW  

–

Low-power standby current typically <6 µA  

–

Hard power down current typically <0.25 µA  

•

Very robust architecture  

–

-40 °C to 105 °C for EEPROM read and register access  

–

-40 °C to 85 °C for EEPROM write access  

•

Extensive product support package  

–

Feature specific application notes  

–

Development board including software and source code  

–

Hands-on training  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

3 Applications  

•

Use cases  

–

Calibration  

–

Trimming  

–

Authenticity check and data protection  

–

Late “in the box” configuration  

–

LED driver configuration  

–

NFC charging  

•

Applications  

–

Lighting  

–

Smart home  

–

Hearable and Wearable  

–

Consumer  

–

Industrial  

–

Gaming  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

4 Ordering

 

information  

Table 1.ꢀOrdering information  

Package  

Orderable part  

number  

Name  

Description  

Version  

NTP52101G0JHKZ  

NTP52101G0JTTZ  

XQFN16  

NTAG 5 switch with GPIOs, PWM and 512 bytes user  

EEPROM plastic,  

SOT1161-2  

extremely thin quad flat package; no leads; 16 terminals  

TSSOP16 NTAG

 

5 switch with GPIOs, PWM and 512 bytes user  

EEPROM  

SOT403-1  

plastic, thin shrink small outline package; 16 leads; 0.65 mm  

pitch;  

5 mm x 4.4 mm x 1.1 mm body  

NTP52101G0JTZ  

SO8  

NTAG 5 switch with GPIOs, PWM and 512 bytes user  

EEPROM plastic,  

SOT96-1  

small outline package; 8 leads; 1.27 mm pitch;  

4.9 mm x 3.9 mm x 1.75 mm body  

NTP52101G0FUAV  

Wafer  

NTAG 5 switch; 8 inch wafer, 150 µm thickness, on film  

frame carrier, electronic fail die marking according to SECS-  

II format)  

–

REMARK:

Wafer specification addendum is available after exchange of a non-disclosure  

agreement (NDA)  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

5 Marking  

Table 2.ꢀMarking codes  

Type number  

Marking code  

Line A  

G11  

Line B  

DBSN|ASID  

DBID|ASID  

DBSN|ASID  

Line C  

DYWW  

Line D  

NTP52101G0JHK  

NTP52101G0JTT  

NTP52101G0JT  

–

NP52101  

NP52101  

ZnDYY  

WW  

–

nDYWW  

Used abbreviations:  

ASID: Assembly Sequence ID  

D: RHF-2006 indicator  

DBID: Diffusion Batch ID  

DBSN: Diffusion Batch Sequence Number  

n: Assembly Centre Code  

WW: week  

Y or YY: year  

Z: Diffusion Centre Code  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

6 Block

 

diagram  

V

*

V

GND  

HPD*  

OUT  

CC  

RF INTERFACE  

PMU  

MEMORY  

ENERGY  

HARVESTING  

RX  

EEPROM  

SECURITY  

GPIO  

PWM  

TX  

ORIG. SIG.  

PWD AUTH.  

SESSION  

REGISTERS  

LA  

LB  

GPIO  

PWM  

DIGI

T

A

L CONTROL UNIT  

ED  

PWM  

RF CONTROLLER  

CLOCK  

MEMORY  

CONTROLLER  

LOW POWER  

FIELD DETECTION  

ED, GPIO AND PWM  

CONTROLLER  

COMMAND  

INTERPRETER  

aaa-034222  

* HPD and V

OUT

are not available for SO8 package  

Figure 2.ꢀBlock diagram NTAG 5 switch  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

7 Pinning

 

information  

1

2

3

4

12  

11  

10  

9

aaa-034213  

Transparent top view  

Figure 3.ꢀPin configuration for XQFN16 package  

Table 3.ꢀPin description for XQFN16  

Pin  

1

Symbol  

GND  

Description  

When unused  

connect to GND  

connect to GND  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

connect to GND  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

Ground  

2

GND  

Ground  

3

N.C.  

not connected  

4

N.C.  

not connected  

5

N.C.  

not connected  

6

GPIO1/PWM1  

GPIO0/PWM0  

ED/PWM0  

V

CC  

Multiplexed GPIO1 and PWM1  

Multiplexed GPIO0 and PWM0  

Multiplexed event detection and PWM0  

External power supply  

Hard power down  

Ground  

7

8

9

10  

11  

12  

13  

14  

15  

16  

HPD  

GND  

V

OUT  

Energy harvesting voltage output  

not connected  

N.C.  

LB  

Antenna connection  

Antenna connection  

not connected  

LA  

N.C.  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

1

2

3

4

5

6

7

8

16  

15  

14  

13  

12  

11  

10  

9

aaa-034214  

Figure 4.ꢀPin configuration for TSSOP16 package  

Table 4.ꢀPin description for TSSOP16  

Pin  

1

Symbol  

LA  

Description  

When unused  

keep floating  

keep floating  

connect to GND  

connect to GND  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

keep floating  

connect to GND  

keep floating  

keep floating  

keep floating  

Antenna connection  

not connected  

2

N.C.  

3

GND  

Ground  

4

GND  

Ground  

5

N.C.  

not connected  

6

N.C.  

not connected  

7

N.C.  

not connected  

8

GPIO1/PWM1  

GPIO0/PWM0  

ED/PWM0  

V

CC  

Multiplexed GPIO1 and PWM1  

Multiplexed GPIO0 and PWM0  

Multiplexed event detection and PWM0  

External power supply  

Hard power down  

Ground  

9

10  

11  

12  

13  

14  

15  

16  

HPD  

GND  

V

OUT  

Energy harvesting voltage output  

not connected  

N.C.  

LB  

Antenna connection  

1

2

3

4

8

7

6

5

aaa-034220  

Figure 5.ꢀPin configuration for SO8 package  

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

Table 5.ꢀPin description for SO8  

Pin  

1

Symbol  

Description  

When unused  

GND  

LA  

Ground  

connect to GND  

2

Antenna connection  

keep floating  

keep floating  

connect to GND  

keep floating  

keep floating  

keep floating  

keep floating  

3

LB  

Antenna connection  

4

GND  

Ground  

5

GPIO1/PWM1  

GPIO0/PWM0  

ED/PWM0  

V

CC  

Multiplexed GPIO1 and PWM1  

Multiplexed GPIO0 and PWM0  

Multiplexed event detection and PWM0  

External power supply  

6

7

8

NTP5210  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

8 Functional

 

description  

8.1 Memory

 

Organization  

8.1.1 General  

The entire memory is divided into three different parts:  

•

User memory  

–

This part of the memory is intended to be used to store user data. It is organized in  

blocks of 4 bytes each (see

).  

–

According to NFC Forum Type 5 Tag Specification, EEPROM block 0 contains the  

Capability Container directly followed by the NDEF Message TLV. If NTAG 5 switch  

is used in a proprietary way, any user data may be stored in the user memory. Direct  

read/write access with the standard READ BLOCK and WRITE BLOCK commands  

(see

) to this part of the memory is possible depending on the related  

security and write protection conditions.  

–

16-bit counter  

The last block of the EEPROM memory contains the 16-bit counter and the counter  

protection flag (see

).  

•

Configuration area  

–

Within this part of the memory all configuration options are stored (see

).  

This memory area can only be accessed with the READ CONFIG (see  

) or WRITE CONFIG (see

) commands.  

–

The configuration area contains required security-related information, such as access  

passwords with related privileges, headers, customer ID (CID), originality signature  

and many more which will be loaded at power-on reset.  

–

Access to configuration blocks may be blocked at all or password protected with  

related configuration bits.  

–

All session registers are accessible in the configuration area as long as not locked  

by LOCK_SESSION_REG. These configuration items can be changed on the fly and  

have immediate effect, but get lost after power-on reset.  

WARNING: The content of bytes and bits defined as RFU SHALL NOT be changed.  

8.1.2 User

 

memory  

According to NFC Forum Type 5 Tag Specification, the user accessible EEPROM  

memory is divided into blocks. A block is the smallest access unit. For NTAG 5 switch,  

each block consists of 4 bytes (1 block = 32 bits). Bit 0 in each byte represents the least  

significant bit (lsb) and bit 7 the most significant bit (msb), respectively.  

The last block contains the 16-bit counter (see

).  

NTAG 5 switch offers 512 bytes (4096 bits) of user memory.  

Table 6.ꢀUser memory organization  

Block Address  

Description  

Byte 0  

(LSB)  

Byte 3  

(MSB)  

Byte 1  

Byte 2  

NFC  

00h  

01h  

Capability Container  

User Memory  

or user memory  

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NTP5210  

NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

Block Address  

Description  

Byte 0  

(LSB)  

Byte 3  

(MSB)  

Byte 1  

Byte 2  

NFC  

:

7Eh  

7Fh  

C0  

C1  

00h  

PROT  

Counter  

User data at delivery contains an NFC Forum-compliant capability container and an  

illustrated in below table. The counter block is initialized with all 00h. Content of the rest  

of the user memory is undefined and contains random (rnd) data at delivery.  

Table 7.ꢀMemory content at delivery  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

00h  

01h  

02h  

03h  

04h  

05h  

06h  

…  

E1h  

03h  

0Ch  

78h  

6Fh  

66h  

rnd  

40h  

10h  

55h  

70h  

6Dh  

63h  

rnd  

20h  

D1h  

01h  

2Eh  

2Fh  

FEh  

rnd  

09h  

01h  

6Eh  

63h  

6Eh  

00h  

rnd  

rnd  

rnd  

rnd  

rnd  

7Fh  

00h  

00h  

00h  

00h  

8.1.2.1 16-bit

 

counter  

Last Block of the user memory contains the 16-bit counter. The block can be accessed  

with the standard read and write commands but special data format is required.  

The standard protection conditions for the user memory are not valid for the counter  

block.  

Counter block can only be accessed from NFC perspective.  

The 16-bit counter can be  

•

preset to initial start value protected with the write password  

•

read  

•

increased by one, optionally protected with the read password  

The counter can be read with an (EXTENDED) READ SINGLE BLOCK to the last block  

or (EXTENDED) READ MULTIPLE BLOCK command including the last block. The 4 byte  

data of the counter block provide the following information in

.  

Table 8.ꢀCOUNTER BLOCK data structure  

Byte  

Name  

Value  

Description  

0

1

C0 (LSB)  

C1 (MSB)  

00h – FFh  

00h – FFh  

Counter value  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

Byte  

Name  

Value  

00h  

Description  

2

–

RFU  

00h  

Incrementing of the counter value is not protected  

3

PROT  

01h  

Incrementing of the counter value is protected with the read password  

The counter can be preset to a start value with an (EXTENDED) WRITE SINGLE BLOCK  

command to counter block. The counter can only be preset to a start value after a SET  

PASSWORD command with the write password.  

The PROT byte (data byte 3) value defines if the protection to increment the counter  

is enabled or disabled. If the protection is enabled, the read password is required to  

increment the counter value.  

The data for the (EXTENDED) WRITE SINGLE BLOCK command to preset the counter  

is defined in

.  

Remark:

A Preset counter value of 0x0001 is not possible, a (EXTENDED) WRITE  

SINGLE BLOCK command with that value will only increment the counter.  

Table 9.ꢀPreset counter data structure  

Byte  

Name  

Value  

Description  

0

C0  

00h, 02h –  

FFh (LSB)  

Counter value  

1

C1  

00h – FFh  

(MSB)  

2

3

–

00h  

00h  

01h  

RFU  

PROT  

Disable the protection to increment the counter  

Enable the protection to increment the counter with read password  

To increment the counter by one with a (EXTENDED) WRITE SINGLE BLOCK  

command to counter block. If the protection to increment the counter is enabled, a SET  

PASSWORD command with the read password is required before.  

The data for the (EXTENDED) WRITE SINGLE BLOCK command to increment the  

counter is defined in

.  

Remark:

The counter can only be incremented with the C0 and C1 values defined in  

. Other values than that preset the counter if a SET PASSWORD command with  

the write password or leads to an error message.  

Table 10.ꢀIncrement counter data structure  

Byte  

Name  

Value  

Description  

0

1

2

3

C0  

C1  

–

01h (LSB)  

00h (MSB)  

00h  

Value to increment the counter  

RFU  

RFU  

–

00h  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

8.1.3 Configuration

 

memory  

The configuration memory contains the security and configuration information. Access  

to this memory area is only possible with WRITE CONFIG (see

) and  

READ CONFIG (see

) commands depending on the initialization status.  

Writing to blocks with only RFU bytes is not possible and results in error code 0Fh.  

Reading complete RFU blocks results in receiving all bytes 00h.  

Changing RFU bytes and bits is not allowed and may result in unintended behavior.  

Different features can be configured with CONFIG bits. Similar to all other configuration  

options, the effect does not take place in the current session. The effect takes place after  

POR. If immediate change is expected, related session register bytes or bits need to be  

used (see

).  

To which section each block belongs is defined in first column (Sec.). Sections might be  

locked by setting related bit to 1b (see

).  

Table 11.ꢀConfiguration Memory organization  

Block Address  

Sec.  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

NFC  

00h  

…  

0

0

0

32 byte Originality  

Signature  

ORIGINALITY_SIGNATURE  

RFU  

(see

)  

07h  

Configuration Header  

(see

)  

0

0

08h  

09h  

CH  

Customer ID (see  

)  

CID  

RFU  

N/A  

N/A  

0Ah  

0Bh  

RFU  

RFU  

NFC Global Crypto  

Header (see  

)  

0

0

0

0Ch  

0Dh  

0Eh  

RFU  

RFU  

NFC_GCH  

RFU  

RFU  

RFU  

NFC Crypto  

Configuration Header  

(see

)  

NFC_CCH  

NFC Authentication  

Limit Counter (see  

)  

NFC_AUTH_LIMIT  

N/A  

N/A  

N/A  

0Fh  

…  

RFU  

1Fh  

Read Password (see  

)  

0

20h  

21h  

NFC_PWD_0  

NFC_PWD_1  

Write Password (see  

)  

0

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

Block Address  

Sec.  

NFC  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

Privacy Password  

(see

)  

0

0

0

22h  

23h  

24h  

NFC_PWD_2  

Destroy Password  

(see

)  

NFC_PWD_3  

NFC_PWD_4  

EAS/AFI Password  

(see

)  

Restricted AREA_1  

Read Password (see  

)  

0

0

25h  

26h  

NFC_PWD_5  

NFC_PWD_6  

Restricted AREA_1  

Write Password (see  

)  

N/A  

N/A  

N/A  

27h  

…  

RFU  

36h  

Feature Configuration  

(see

)  

2

37h  

38h  

CONFIG  

RFU  

N/A  

PWM and GPIO  

Configuration (see  

)  

3

3

39h  

3Ah  

PWM_GPIO_CONFIG  

RFU  

PWM1 Configuration  

(see

)  

PWM0_ON_OFF  

PWM1 Configuration  

(see

)  

3

3Bh  

3Ch  

PWM1_ON_OFF  

RFU  

N/A  

Energy Harvesting  

(see

)  

and Event  

3

N/A  

3

3Dh  

3Eh  

3Fh  

40h  

EH_CONF  

RFU  

ED_CONF  

RFU  

Detection Pin (see  

)  

Configuration  

RFU  

Configuration  

Protection (see  

)  

CONF_  

PROT  

RFU  

PP_AREA_1  

AREA_1 Protection  

Pointer (see  

)  

N/A  

RFU  

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Block Address  

Sec.  

NFC  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

N/A  

N/A  

…  

54h  

Application Family  

Identifier (see  

)  

4

55h  

AFI  

RFU  

RFU  

DSFID (see  

)  

4

4

56h  

57h  

DSFID  

EAS ID (see  

)  

EAS_ID  

RFU  

RFU  

NFC Protection  

Pointer (see  

)  

and NFC Protection  

Pointer Conditions  

(see

)  

4

58h  

PP_AREA_0H NFC_PPC  

N/A  

N/A  

N/A  

5

59h  

…  

RFU  

69h  

6Ah  

…  

NFC Lock block  

configuration (see  

)  

5

NFC_LOCK_BLOCK  

RFU  

5

71h  

72h  

…  

N/A  

N/A  

N/A  

8

RFU  

RFU  

91h  

92h  

NFC_  

SECTION_  

LOCK  

NFC section lock  

bytes (see

)  

RFU  

8

93h  

N/A  

N/A  

N/A  

94h  

…  

9Fh  

8.1.3.1 Originality

 

Signature  

The Originality signature (see

) is stored in first 8 blocks (block 00h to  

block 07h) of configuration memory and may be verified by the NFC device using the  

corresponding ECC public key. As the NXP originality signature is on default not locked,  

it may be re-programmed by the customer. If the originality check is not needed, it may  

even be used as additional 32 byte user EEPROM.  

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Table 12.ꢀ32 Byte Originality Signature  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

00h  

01h  

02h  

03h  

04h  

05h  

06h  

07h  

SIG0 (LSB)  

SIG4  

SIG1  

SIG5  

SIG2  

SIG6  

SIG3  

SIG7  

SIG8  

SIG9  

SIG10  

SIG14  

SIG18  

SIG22  

SIG26  

SIG30  

SIG11  

SIG12  

SIG16  

SIG20  

SIG24  

SIG28  

SIG13  

SIG17  

SIG21  

SIG25  

SIG29  

SIG15  

SIG19  

SIG23  

SIG27  

SIG31 (MSB)  

8.1.3.2 Configuration

 

Header  

The Configuration Header (CH) byte defines the access conditions of both, Customer ID  

and Originality Signature.  

Table 13.ꢀConfiguration Header (CH) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

08h  

CH  

RFU  

Configuration Header byte can be read with READ CONFIG command (see  

) and written with WRITE CONFIG command (see

).  

Once locked (set to E7h), CH byte cannot be updated anymore and Originality Signature  

and Customer ID gets locked permanently.  

Table 14.ꢀConfiguration Header Codes  

Value  

81h  

Mode  

Writeable (default)  

Locked  

Write Access  

Yes  

No  

E7h  

All others  

Invalid  

No  

8.1.3.3 Customer

 

ID (CID)  

The Customer ID at delivery is C000h and can be reprogrammed and locked. It might be  

used to identify the product.  

The two most significant bits (b7 and b6 of CID (MSB)) are always equal to 11b. Only  

CID[13-0] may be written by customer. Note, that other values of the two most significant  

bits are RFU.  

When the CID is written with WRITE CONFIG command, the 2 most significant bits are  

always set to 11b. The input CID in WRITE CONFIG command (see

) is  

bit wise ORed with C000h.  

Example: When setting CID to 10AAh, resulting customer-specific CID is D0AAh.  

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Table 15.ꢀCustomer ID (CID) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

09h  

CID (LSB)  

CID (MSB)  

RFU  

The CID can be permanently locked by setting the Configuration Header to Locked state  

(see

) using WRITE CONFIG command. Note, that Originality Signature gets  

locked, too.  

8.1.3.4 NFC

 

Global Crypto Header  

The NFC Global Crypto Header (NFC_GCH) defines the status and access of the  

•

NFC passwords  

As long as not locked by the RF section lock, the NFC Global Crypto Header can be  

written with WRITE CONFIG command (see

). The programming of  

NFC Global Crypto Header can be done in only one direction from lower state to higher  

and it is irreversible.  

Once locked (as per table below), GCH cannot be updated anymore.  

Table 16.ꢀNFC Global Crypto Header (GCH) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

0Ch  

RFU  

NFC_GCH  

RFU  

Table 17.ꢀGlobal Crypto Header Configuration  

Value  

Status  

Description  

81h  

Writable (default)  

The NFC passwords can be read and written with the READ CONFIG  

and WRITE CONFIG commands.  

E7h  

Locked  

Invalid  

The NFC passwords cannot be read and written with the READ  

CONFIG and WRITE CONFIG commands.  

all others  

NOTE: LOCK PASSWORD command is needed to lock NFC passwords permanently  

(see

).  

8.1.3.5 NFC

 

Crypto Configuration Header  

The value of the NFC Crypto Configuration Header (NFC_CCH) locks the NFC  

Authentication Limit to the defined value and can only be changed after authentication.  

NFC_CCH can be written by using the WRITE CONFIGURATION command (see  

).  

Table 18.ꢀCrypto Configuration Header (CCH) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

0Dh  

RFU  

NFC_CCH  

RFU  

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Table 19.ꢀCrypto Configuration Header Values  

Value  

Mode  

Write Access  

81h  

E7h  

Unlocked (default)  

Locked  

Authentication limit can be modified.  

Authentication limit is locked and can only be modified  

after authenticating with the write password. In 64-bit  

password mode both, the read and write password are  

required, depending on the used security level.  

All others

 

Invalid  

8.1.3.6 NFC

 

Authentication Limit Counter  

NTAG 5 switch implements the NFC Authentication Limit in counting negative  

Password Authentication attempts with the SET PASSWORD command, except for the  

Privacy password. The counter will be reset automatically to zero after a successful  

authentication.  

Table 20.ꢀNFC Authentication Limit Counter (NFC_AUTH_LIMIT) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

NFC_AUTH_  

LIMIT (LSB)  

NFC_AUTH_  

LIMIT (MSB)  

0Eh  

RFU  

Byte 0 of Block 0Eh is LSB and Byte 1 is MSB of the NFC Authentication Limit counter  

value.  

The Authentication limit is enabled with the most significant bit of Byte 1 is set to 1b. The  

remaining 15 bits of NFC_AUTH_LIMIT are defining the preset value.  

T Counter can be written with a WRITE CONFIG command (see

) if  

•

the Crypto Config Header is not set to “Locked” and NFC Global Crypto Header is not  

set to “Locked”, or  

•

a valid SET_PASSWORD command with the write password has been executed  

before. In 64-bit password mode, both read and write passwords are required.  

Examples:  

•

8000h enables and presets the authentication limit to 0, which means the maximum  

number of authentications (32767) before a preset is required again  

•

F000h enables and presets the authentication limit to 28672  

If the NFC authentication limit counter reaches FFFFh, then SET_PASSWORD  

command is permanently locked. No further authentication is possible.  

Remark:

The absolute maximum authentication limit value is FFFEh before a is required,  

otherwise the authentication is irreversibly locked (no longer available).  

8.1.3.7 Passwords  

The passwords are stored in the configuration memory.  

Default password bytes of Privacy and Destroy password are all 0Fh, Read, Write and  

EAS/AFI password bytes have a default value of all 00h.  

The usage of passwords, read and write access to passwords depends upon NFC Global  

Crypto Header settings.  

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Table 21.ꢀPlain Password location  

Block Address  

Byte 0  

NFC  

Byte 1  

Byte 2  

Byte 3  

Description  

NFC_PWD0_  

NFC_PWD0_  

3 (MSB)  

Read Password  

Write Password  

20h  

21h  

22h  

23h  

24h  

25h  

26h  

0 (LSB)  

NFC_PWD0_1  

NFC_PWD1_1  

NFC_PWD2_1  

NFC_PWD3_1  

NFC_PWD4_1  

NFC_PWD5_1  

NFC_PWD6_1  

NFC_PWD0_2  

NFC_PWD1_2  

NFC_PWD2_2  

NFC_PWD3_2  

NFC_PWD4_2  

NFC_PWD5_2  

NFC_PWD6_2  

NFC_PWD1_  

0 (LSB)  

NFC_PWD1_  

3 (MSB)  

NFC_PWD2_  

0 (LSB)  

NFC_PWD2_  

3 (MSB)  

Privacy Password  

Destroy Password  

EAS/AFI Password  

NFC_PWD3_  

0 (LSB)  

NFC_PWD3_  

3 (MSB)  

NFC_PWD4_  

0 (LSB)  

NFC_PWD4_  

3 (MSB)  

NFC_PWD5_  

0 (LSB)  

NFC_PWD5_  

3 (MSB)  

AREA_1 Read  

Password  

NFC_PWD6_  

0 (LSB)  

NFC_PWD6_  

3 (MSB)  

AREA_1 Write  

Password  

8.1.3.8 Configuration  

Different features can be configured with CONFIG bits. The effect does not take place  

in the current session. The effect takes place after POR. All config bits can be read and  

written.  

Table 22.ꢀConfiguration Bytes Location (CONFIG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

37h  

CONFIG_0  

CONFIG_1  

CONFIG_2  

RFU  

On POR, all CONFIG bits are copied to CONFIG_REG (see

).  

Table 23.ꢀConfiguration Definition (CONFIG_0)  

Bit  

7

Name  

RFU  

Value  

0b  

Description  

6 to 4  

RFU  

0b  

00b  

01b  

3

2

1

0

RFU  

EH_MODE  

Energy harvesting optimized for low field strength  

(default)  

10b  

11b  

0b  

1b  

0b  

1b  

Energy harvesting optimized for high field strength  

NFC Write access to all session register (default)  

No NFC write access to session registers A3h to A7h  

Normal Operation Mode (Default)  

LOCK_SESSION_REG  

AUTO_STANDBY_MODE_EN  

IC enters standby mode after boot if there is no RF field  

present automatically.  

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Table 24.ꢀConfiguration Definition (CONFIG_1)  

Bit  

7

Name  

RFU  

Value  

0b  

Description  

6

RFU  

0b  

00b  

01b  

10b  

11b  

RFU  

5

RFU  

HOST_IF  

RFU  

GPIO/PWM (default)  

4

All host interface functionality disabled and pads are in  

3-state mode  

3 to 0  

0000b  

Table 25.ꢀConfiguration Definition (CONFIG_2)  

Bit  

Name  

Value  

00b  

01b  

10b  

11b  

00b  

01b  

10b  

11b  

0b  

Description  

Receiver disabled  

7

Plain input with weak pull-up  

Plain input  

GPIO1_IN  

6

5

4

3

2

1

0

Plain input with weak pull-down (Default)  

Receiver disabled (Default)  

Plain input with weak pull-up  

Plain input  

GPIO0_IN  

Plain input with weak pull-down (Default)  

Extended commands are disabled (Default)  

Extended commands are supported  

Lock block commands are disabled  

Lock block commands are supported (Default)  

Low Speed GPIO  

EXTENDED_COMMANDS_  

SUPPORTED  

1b  

0b  

LOCK_BLOCK_  

COMMAND_SUPPORTED  

1b  

0b  

GPIO1_SLEW_RATE  

GPIO0_SLEW_RATE  

1b  

High Speed GPIO (Default)  

Low Speed GPIO  

0b  

1b  

High Speed GPIO (Default)  

8.1.3.9 Pulse

 

Width Modulation and GPIO configuration  

These configuration bytes define the various configuration bits for GPIO/PWM use case  

(see

). All features can be configured from NFC perspective. For details  

refer to

and

.  

Table 26.ꢀPWM and GPIO Configuration Location (PWM_GPIO_CONFIG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

PWM_GPIO_  

CONFIG_0  

PWM_GPIO_  

CONFIG_1  

RFU  

39h  

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Table 27.ꢀPWM and GPIO Configuration Definition (PWM_GPIO_CONFIG_0)  

Bit  

Name  

Value  

0b  

Description  

Output status on pad is LOW (default)  

Output status on pad is HIGH  

Output status on pad is LOW (default)  

Output status on pad is HIGH  

7

GPIO1_OUT_STATUS  

1b  

0b  

6

5 to 4  

3

GPIO0_OUT_STATUS  

1b  

RFU  

00b  

0b  

Output (Default)  

Input  

GPIO1  

1b  

0b  

Output (Default)  

Input  

2

1

0

GPIO0  

1b  

0b  

GPIO (Default)  

PWM  

GPIO1_PWM1  

GPIO0_PWM0  

1b  

0b  

GPIO (Default)  

PWM  

1b  

Table 28.ꢀPWM and GPIO Configuration Definition (PWM_GPIO_CONFIG_1 and PWM_GPIO_CONFIG_1_REG)  

Bit  

7

Name  

Value  

Description  

Pre-scalar configuration for PWM1 channel  

(default 00b)  

PWM1_PRESCALE  

PWM0_PRESCALE  

00b  

6

5

Pre-scalar configuration for PWM0 channel  

(default 00b)  

00b  

4

00b  

01b  

10b  

11b  

00b  

01b  

10b  

11b  

6-bit resolution (default)  

8-bit resolution  

3

2

1

0

PWM1_RESOLUTION_CONF  

PWM0_RESOLUTION_CONF  

10-bit resolution  

12-bit resolution  

6-bit resolution (default)  

8-bit resolution  

10-bit resolution  

12-bit resolution  

8.1.3.10 Pulse

 

Width Modulation duty cycle settings  

Details can be found in PWM Mode section (see

).  

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Table 29.ꢀPulse Width Modulation Duty Cycle Configuration Location (PWMx_ON and PWMx_OFF)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

3Ah  

3Bh  

PWM0_ON (LSB)  

PWM1_ON (LSB)  

PWM0_ON (MSB)  

PWM1_ON (MSB)  

PWM0_OFF (LSB)  

PWM1_OFF (LSB)  

PWM0_OFF (MSB)  

PWM1_OFF (MSB)  

Table 30.ꢀPulse Width Modulation Duty Cycle Session Register Location (PWMx_ON and PWMx_OFF)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

A4h  

A5h  

PWM0_ON_  

REG (LSB)  

PWM0_ON_  

REG (MSB)  

PWM0_OFF_  

REG (MSB)  

PWM0_OFF_REG (LSB)  

PWM1_OFF_REG (LSB)  

PWM1_ON_  

REG (LSB)  

PWM1_ON_  

REG (MSB)  

PWM1_OFF_  

REG (MSB)  

Table 31.ꢀPulse Width Modulatin ON time Configuration Definition (PWMx_ON and PWMx_ON_REG)  

Bit  

Name  

Default  

Value  

Description  

7 to 4  

3 to 0  

7 to 0  

RFU  

all 0b  

all 0b  

all 0b  

PWMx_ON (MSB)  

PWMx_ON (LSB)  

coded time PWM channel x output will be asserted HIGH  

Table 32.ꢀPulse Width Modulation OFF time Configuration Definition (PWMx_OFF and PWMx_OFF_REG)  

Bit  

Name  

Default  

Value  

Description  

7 to 4  

3 to 0  

7 to 0  

RFU  

all 0b  

all 0b  

all 0b  

PWMx_OFF (MSB)  

PWMx_OFF (LSB)  

coded time PWM channel x output will be asserted LOW  

PWM on and off times are coded by using maximum 12 bits. To code for example,  

PWM0_ON as 0123h, PWM0_ON (LSB) is set to 23h, and PWM0_ON (MSB) is set to  

01h.  

8.1.3.11 Energy

 

harvesting settings  

Energy harvesting configuration controls the behavior of the energy harvesting  

output pin. If DISABLE_POWER_CHECK is 0b and energy harvesting is enabled  

with EH_ENABLE is 1b, only when the applied field strength is sufficient to generate  

configured minimum output load current (EH_IOUT_SEL) and voltage (EH_VOUT_SEL),  

the energy harvesting output is enabled.  

If energy harvesting will be enabled during the session with register bits,  

EH_IOUT_SEL and EH_VOUT_SEL define the needed output power. However,  

DISABLE_POWER_CHECK and EH_ENABLE bits need to be set to 0b in this case.  

Details can be found in energy harvesting section (see

).  

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Table 33.ꢀEnergy harvesting Configuration Location (EH_CONFIG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

3Dh  

EH_CONFIG  

RFU  

ED_CONFIG  

RFU  

Table 34.ꢀEnergy harvesting Configuration Value Definition (EH_CONFIG)  

Bit  

7

Name  

Value  

Description  

RFU  

6

000b  

001b  

010b  

011b  

100b  

101b  

110b  

111b  

0b  

>0.4 mA (Default)  

>0.6 mA  

>1.4 mA  

5

4

>2.7 mA  

EH_VOUT_I_SEL  

>4.0 mA  

>6.5 mA  

>9.0 mA  

>12.5 mA  

Only if sufficient power can be harvested, VOUT  

will be enabled (default)  

DISABLE_  

POWER_CHECK  

3

1b  

Power level will not be checked, VOUT will be  

enabled immediately after startup  

2

1

0

00b  

01b  

10b  

11b  

0b  

1.8 V (Default)  

2.4 V  

EH_VOUT_V_SEL  

EH_ENABLE  

3 V  

RFU  

Energy harvesting disabled (default)  

Energy harvesting enabled  

1b  

8.1.3.12 Event

 

detection pin configuration settings  

Event detection and field detection functionality define the behavior of the active low ED  

pin depending on various events. As this pin is an open-drain active low implementation,  

ED pin state ON means that signal is LOW and OFF means that signal is HIGH. More  

details can be found in ED section (see

).  

Table 35.ꢀEvent Detection Configuration Location (ED_CONFIG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

3Dh  

EH_CONFIG  

RFU  

ED_CONFIG  

RFU  

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Table 36.ꢀEvent Detection Configuration Register Location (ED_CONFIG_REG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

A8h  

ED_COFIG_REG  

RFU  

Table 37.ꢀEvent Detection Definition (ED_CONFIG and ED_CONFIG_REG)  

Bit  

Name  

Value  

ED pin  

state  

Description  

7 to 4  

3 to 0  

RFU  

0000b  

0000b  

N/A  

OFF  

ON  

Disable ED  

Event detection pin disabled (default)  

NFC field present  

NFC Field detect  

0001b  

0010b  

0011b  

0100b  

0101b  

0110b  

0111b  

1000b  

OFF  

ON  

NFC field absent  

Pulse width modulation signal during OFF period  

Pulse width modulation signal during On period  

PWM  

RFU  

RFU  

RFU  

OFF  

ON  

OFF  

ON  

OFF  

ON  

OFF  

ON  

Length byte(block 1, byte 1) is not ZERO  

Length byte (block 1, byte1) is ZERO  

IC is NOT in standby mode  

NDEF Message TLV  

Length  

OFF  

ON  

Stand-by mode  

OFF  

ON  

IC is in standby mode  

Start of programming cycle during WRITE command  

Start of response to WRITE command or NFC off  

Start of read cycle during READ command  

WRITE command  

indication  

OFF  

ON  

READ command  

indication  

1001b  

1010b  

•

End of read access, or  

•

NFC off  

OFF  

ON  

Start of (any) command  

Start of command  

indication  

•

End of response to command, or  

•

NFC off  

OFF  

ON  

OFF  

ON  

RFU  

RFU  

1011b  

1100b  

OFF  

ON  

1101b written to ED_CONFIG  

Software Interrupt  

1101b  

Event needs to be cleared by setting b0 of ED_  

RESET_REG to 1b  

OFF  

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Bit  

Name  

Value  

ED pin  

state  

Description  

RFU  

RFU  

1110b  

1111b  

N/A  

N/A  

Table 38.ꢀEvent Detection Clear Register Location (ED_INTR_CLEAR_REG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

ED_INTR_  

CLEAR_REG  

RFU  

ABh  

Table 39.ꢀEvent Detection Clear Register (ED_INTR_CLEAR_REG)  

Bit  

7 to 1  

0

Name  

Value  

all 0b  

1b  

Description  

RFU  

ED_INTR_CLEAR  

write 1b to release ED pin  

ED pin is cleared i.e. released when writing 01h to the ED clear register. The bit gets  

automatically cleared after clearing the ED pin.  

8.1.3.13 configuration

 

protection  

Access to blocks 37h to 54h of configuration area can be restricted with CONFIG_PROT  

byte.  

Table 40.ꢀConfiguration Byte location  

Block Address  

Byte 0  

NFC  

Byte 3  

Byte 1  

Byte 2  

3Fh  

RFU  

CONF_PROT  

PP_AREA_1 (LSB)  

PP_AREA_1 (MSB)  

Table 41.ꢀConfiguration Protection (CONF_PROT)  

Bit  

Name  

Value  

all 0b  

0b  

Description  

7 to 2  

RFU  

Configuration area is not write protected (Default)  

Configuration area is write protected  

1

0

NFC_CONFIG_W  

NFC_CONFIG_R  

1b  

0b  

Configuration area is not read protected (Default)  

Configuration area is read protected  

1b  

8.1.3.14 Restricted

 

AREA_1 pointer  

The AREA_1 Pointer (PP_AREA_1) can be configured by directly writing PP_AREA_1  

byte to configuration memory using WRITE CONFIG command (see

).  

The default value is FFFFh.  

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Table 42.ꢀRestricted AREA_1 Pointer location  

Block Address  

Byte 0  

NFC  

Byte 3  

Byte 1  

Byte 2  

3Fh  

RFU  

CONF_PROT  

PP_AREA_1 (LSB)  

PP_AREA_1 (MSB)  

In below example, NFC protection pointer (PP_AREA_0H) is set to 50h and PP_AREA_1  

is set to 0060h, e.g. PP_AREA_1 (LSB) is 60h and PP_AREA_1 (MSB) is 00h.  

Table 43.ꢀMemory organization example  

Block  

0000h  

0001h  

0002h  

…  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

AREA_0-L  

…  

…  

…  

…  

…  

…  

…  

…  

004Fh  

0050h  

0051h  

…  

AREA_0-H  

005Fh  

0060h  

0061h  

…  

AREA_1  

Counter  

…  

…  

…  

…  

007Eh  

007Fh  

C0  

C1  

00h  

PROT  

8.1.3.15 Application

 

Family Identifier  

The Application Family Identifier (AFI) represents the type of application targeted by the  

device and is used to extract from all the ICs present only the ICs meeting the required  

application criteria.  

AFI can be configured using WRITE AFI command (see

) or directly  

writing AFI byte to configuration memory using WRITE CONFIG command (see  

).  

Default value of AFI is 00h.  

Table 44.ꢀApplication Family Identifier (AFI) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

55h  

AFI  

RFU  

8.1.3.16 Data

 

Storage Format Identifier  

The Data Storage Format Identifier may indicate how the data is structured in the VICC  

memory. If not used, this byte shall be set to 00h, which is the default value.  

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The Data Storage Format Identifier (DSFID) can be configured using WRITE DSFID  

command (see

) or directly writing DSFID byte to configuration memory  

using WRITE CONFIG command (see

).  

Table 45.ꢀData Storage Format Identifier (DSFID) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

56h  

DSFID  

RFU  

8.1.3.17 Electronic

 

Article Surveillance ID  

The Electronic Article Surveillance ID (EAS ID) can be configured using WRITE EAS  

ID (see

) command or directly writing EAS_ID byte to configuration  

memory using WRITE CONFIG command (see

).  

Default value of EAS_ID is 0000h.  

Table 46.ꢀElectronic Article Surveillance ID (EASID) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

57h  

EAS_ID (LSB)  

EAS_ID (MSB)  

RFU  

8.1.3.18 NFC

 

protection pointer  

The NFC protection pointer (PP_AREA_0H) can be configured using PROTECT PAGE  

command (see

) or directly writing PP_AREA_0H byte to configuration  

memory using WRITE CONFIG command (see

).  

Default value is FFh.  

Table 47.ꢀNFC Protection Pointer (NFC PP) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

58h  

PP_AREA_0H  

NFC_PPC  

RFU  

RFU  

In below example, NFC protection pointer is set to 50h. PP_AREA_1 is out side of the  

EEPROM area in this example.  

Table 48.ꢀMemory organization example  

Block  

0000h  

0001h  

0002h  

…  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

AREA_0-L  

…  

…  

…  

…  

…  

…  

…  

…  

004Fh  

0050h  

0051h  

…  

AREA_0-H  

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Block  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

Description  

007Eh  

007Fh  

C0  

C1  

00h  

PROT  

Counter  

8.1.3.19 NFC

 

Protection Pointer Conditions  

The NFC Protection Pointer Conditions (NFC PPC) can be configured using PROTECT  

PAGE command (see

) or directly writing NFC_PPC byte to  

configuration memory using WRITE CONFIG command (see

) as  

defined in table below.  

Table 49.ꢀNFC Protection Pointer Conditions (NFC_PPC) location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

58h  

PP_AREA_0H  

NFC_PPC  

RFU  

RFU  

Table 50.ꢀNFC Protection Pointer Configuration (NFC_PPC)  

Bit  

7

Name  

RFU  

Value Description  

0b  

0b  

6

RFU  

0b  

1b  

0b  

1b  

0b  

0b  

0b  

1b  

0b  

1b  

AREA_0-H is not write protected (Default)  

AREA_0-H is write protected  

5

4

Write AREA_0_H  

Read AREA_0_H  

AREA_0-H is not read protected (Default)  

AREA_0-H is read protected  

3

2

RFU  

RFU  

Write AREA_0_L  

AREA_0-L is not write protected (Default)  

AREA_0-L is write protected  

1

0

Read AREA_0_L  

AREA_0-L is not read protected (Default)  

AREA_0-L is read protected  

8.1.3.20 NFC

 

lock bytes  

User blocks can be blocked from writing by the NFC interface. These bits are one time  

programmable. Once written to 1b, they cannot be changed back to 0b. Each bit locks  

one block of user memory area (e.g., bit 0 of byte 0 locks block 0).These bytes can be  

written by NFC. The access to these bytes for the particular interface can be restricted by  

configuring the device SECTION_LOCK (see

).  

Table 51.ꢀNFC Lock Block Configuration location  

Block Address  

Byte 0  

NFC  

Byte 1  

Byte 2  

Byte 3  

6Ah  

…  

NFC_LOCK_BL00  

…  

NFC_LOCK_BL01  

…  

RFU  

RFU  

RFU  

RFU  

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Block Address  

NFC  

Byte 0  

NFC_LOCK_BL14  

Byte 1  

Byte 2  

Byte 3  

71h  

NFC_LOCK_BL15  

RFU  

RFU  

8.1.3.21 Device

 

configuration section lock bytes  

Lock bits are provided to lock different sections of the configuration area. 16 bits are  

provided to define access conditions for different sections of the configuration area.  

First column in the configuration memory table (see

) defines the affiliated blocks  

of each section.  

Table 52.ꢀDevice configuration section lock bytes location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

92h  

93h  

NFC_LOCK_0  

NFC_LOCK_1  

RFU  

RFU  

These section lock configurations are provided to allow customer to initialize NTAG  

5 switch during customer configuration from NFC interface. After the configuration is  

done, it is recommended to write the appropriate lock conditions and lock the device  

configuration bytes.  

These lock bytes take the highest priority above all locks. Different section access  

conditions have to be chosen appropriately, so that the other interface does not change  

and corrupt the other interface security configuration.  

If NFC_LOCK_0 bits are set to 1b, then the lock bytes cannot be updated and gets  

locked permanently.  

Table 53.ꢀNFC configuration section lock byte 0 definition (NFC_SECTION_LOCK_0)  

Bit  

Name  

Value  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

Description  

Section 7 is writable  

Section 7 is not writable  

Section 6 is writable  

Section 6 is not writable  

Section 5 is writable  

Section 5 is not writable  

Section 4 is writable  

Section 4 is not writable  

Section 3 is writable  

Section 3 is not writable  

Section 2 is writable  

Section 2 is not writable  

Section 1 is writable  

Section 1 is not writable  

Section 0 is writable  

7

Section 7  

6

5

4

3

2

Section 6  

Section 5  

Section 4  

Section 3  

Section 2  

1

0

Section 1  

Section 0  

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Bit  

Name  

Value  

Description  

1b  

Section 0 is not writable  

Table 54.ꢀNFC configuration section lock Byte 1 definition (NFC_SECTION_LOCK_1)  

Bit  

Name  

Value  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

Description  

Section 8 is writable  

7

Section 8  

Section 8 is not writeable  

Section 6 is readable  

Section 6 is not readable  

Section 5 is readable  

Section 5 is not readable  

Section 4 is readable  

Section 4 is not readable  

Section 3 is readable  

Section 3 is not readable  

Section 2 is readable  

Section 2 is not readable  

Section 1 is readable  

Section 1 is not readable  

Section 0 is readable  

Section 0 is not readable  

6

5

4

3

2

1

0

Section 6  

Section 5  

Section 4  

Section 3  

Section 2  

Section 1  

Section 0  

Note: Section 8 (Device configuration lock bytes) is always readable.  

In case of not readable and/or not writeable, IC responds with an error from NFC  

perspective, when trying to access locked sections.  

8.1.4 Session

 

registers  

After POR, the content of the configuration settings (see

) is loaded  

into the session register. The values of session registers can be changed during a  

session. Change to session registers take effect immediately, but only for the current  

communication session. After POR, the session registers values will again contain the  

configuration register values as before.  

To change the default behavior, changes to the related configuration bytes are needed,  

but the related effect will only be visible after the next POR.  

Session registers starting from block A3h until the end may be write protected with  

LOCK_REGISTER bit.  

Most of the parameters are defined in the configuration memory section.  

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Table 55.ꢀSession Register Location  

Block Address  

Byte 0  

NFC  

Remark  

Byte 1  

Byte 2  

Byte 3  

Status  

STATUS_REG  

RFU  

RFU  

Register (see  

)  

A0h  

Configuration (see  

)  

CONFIG_REG  

RFU  

A1h  

A2h  

PWM and GPIO  

Configuration(see  

)  

A3h  

A4h  

PWM_GPIO_CONFIG_REG  

PWM1  

Configuration (see  

)  

PWM0_ON_OFF_REG  

PWM1  

A5h  

A6h  

A7h  

PWM1_ON_OFF_REG  

Configuration (see  

)  

RFU  

Energy Harvesting  

Configuration (see  

)  

EH_CONFIG_REG  

ED_CONFIG_REG  

RFU  

Event detection  

functionality (see  

)  

A8h  

A9h  

AAh  

RFU  

RFU  

Reset  

Register (see  

)  

RESET_  

GEN_REG  

RFU  

Clear Event  

Detection (see  

)  

ED_INTR_  

CLEAR_REG  

ABh  

RFU  

ACh  

ADh  

AEh  

AFh  

RFU  

RFU  

RFU  

RFU  

8.1.4.1 Status

 

register  

Different status of NTAG 5 switch can be known by reading status register. The status  

register can be read by READ_CONFG.  

Some of the registers may be cleared. Setting status bits to 1b is not possible at all.  

Table 56.ꢀStatus Register Location  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

A0h  

STATUS0_REG  

STATUS1_REG  

RFU  

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Table 57.ꢀ Status 0 Register  

Access  

Bit  

Name  

Value Description  

NFC  

0b  

1b  

EEPROM is not busy  

7

EEPROM_WR_BUSY  

R

EEPROM is busy (programming cycle  

ongoing)  

0b  

1b  

all data written successfully  

6

EEPROM_WR_ERROR  

R/W  

EEPROM write error happened. This bit  

needs to be cleared.  

5 to 2  

1

RFU  

R

R

0000b  

0b  

VCC supply not present  

VCC supply available  

No NFC field present  

NFC field present  

VCC_SUPPLY_OK  

1b  

0b  

0

NFC_FIELD_OK  

R

1b  

Table 58.ꢀ Status 1 Register  

Bit Name  

Access  

Value  

Description  

NFC  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

000b  

VCC boot not done  

VCC boot done  

7

6

5

4

3

VCC_BOOT_OK  

NFC_BOOT_OK  

RFU  

R

NFC boot not done  

NFC boot done  

R

R

R

GPIO_1 input is LOW  

GPIO_1 input is HIGH  

GPIO_0 input is LOW  

GPIO_0 input is HIGH  

GPIO1_IN_STATUS  

GPIO0_IN_STATUS  

RFU  

R

R

2 to 0  

8.1.4.2 Configuration

 

register  

On POR all CONFIG bits (see

) are copied to CONFIG_REG. Some  

of these features may be changed with CONFIG_REG bits during a session. These  

features are valid at once. Most of them are just read only from NFC.  

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Table 59.ꢀConfiguration Register Location (CONFIG_REG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

A1h  

CONFIG_0_REG  

RFU  

CONFIG_2_REG  

RFU  

Table 60.ꢀConfiguration Definition (CONFIG_0_REG)  

Access  

NFC  

Bit  

Name  

Value Description  

7

6

5

4

3

2

1

RFU  

RFU  

RFU  

RFU  

RFU  

RFU  

RFU  

R

R

R

R

R

R

R

0b  

0b  

0b  

0b  

0b  

0b  

0b  

0b  

1b  

Normal Operation Mode  

0

AUTO_STANDBY_MODE_EN  

R

IC enters standby mode after boot if there  

is no RF field present automatically.  

Table 61.ꢀConfiguration Definition (CONFIG_2_REG)  

Bit  

Name  

Access  

NFC acc.  

Value Description  

00b  

01b  

10b  

11b  

00b  

01b  

10b  

11b  

0b  

Receiver disabled  

7

6

5

4

3

2

1

0

Plain input with weak pull-up  

Plain input  

GPIO1_IN  

R

R

Plain input with weak pull-down  

Receiver disabled  

Plain input with weak pull-up  

Plain input  

GPIO0_IN  

Plain input with weak pull-down  

Extended commands are disabled  

Extended commands are supported  

Lock block commands are disabled  

Lock block commands are supported  

Low-Speed GPIO  

EXTENDED_COMMANDS_  

SUPPORTED  

R

R

R

R

1b  

0b  

LOCK_BLOCK_COMMAND_  

SUPPORTED  

1b  

0b  

GPIO1_SLEW_RATE  

GPIO0_SLEW_RATE  

1b  

High-Speed GPIO  

0b  

Low-Speed GPIO  

1b  

High-Speed GPIO  

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8.1.4.3 Pulse

 

Width Modulation and GPIO configuration register  

These session register bytes define the various configurations for GPIO/PWM use case  

(see

). IN_STATUS bits are read only, all others maybe changed during a  

session. For details refer to

and

.  

Table 62.ꢀPWM and GPIO Configuration Register Location (PWM_GPIO_CONFIG_REG)  

Block Address  

NFC  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

PWM_GPIO_  

CONFIG_0_REG  

PWM_CONFIG_  

1_REG  

RFU  

A3h  

Table 63.ꢀPWM and GPIO Configuration Register Definition (PWM_GPIO_CONFIG_0_REG)  

Bit  

Name  

Access  

NFC acc.  

Value Description  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

0b  

1b  

Output status on pad is LOW  

7

6

5

4

3

2

1

0

GPIO1_OUT_STATUS  

GPIO0_OUT_STATUS  

GPIO1_IN_STATUS  

GPIO0_IN_STATUS  

GPIO1  

R/W  

R/W  

R

Output status on pad is HIGH  

Output status on pad is LOW  

Output status on pad is HIGH  

Input status  

Input status  

R

Output  

Input  

R/W  

R/W  

R/W  

R/W  

Output  

Input  

GPIO0  

GPIO  

PWM  

GPIO  

PWM  

GPIO1_PWM1  

GPIO0_PWM0  

Table 64.ꢀPWM and GPIO Configuration Register Definition (PWM_GPIO_CONFIG_1_REG)  

Bit  

Name  

Access  

Value Description  

NFC  

Acc.  

R/W  

R/W  

7

6

5

PWM1_PRESCALE  

PWM0_PRESCALE  

00b  

00b  

Pre-scalar configuration for PWM1 channel  

Pre-scalar configuration for PWM0 channel  

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Bit  

Name  

Access  

NFC  

Value Description  

Acc.  

4

3

00b  

01b  

10b  

11b  

00b  

01b  

10b  

11b  

6-bit resolution  

8-bit resolution  

10-bit resolution  

12-bit resolution  

6-bit resolution  

8-bit resolution  

10-bit resolution  

12-bit resolution  

PWM1_RESOLUTION_CONF  

PWM0_RESOLUTION_CONF  

R/W  

2

1

0

R/W  

8.1.4.4 Pulse

 

Width Modulation duty cycle register  

The PWM duty cycle maybe changed during one session from NFC perspective (see  

).  

8.1.4.5 Energy

 

harvesting register  

Energy harvesting registers may be used to enable energy harvesting during one  

NFC session. In this case, EH_ENABLE bit of EH_CONFIG byte in block 3Dh is set  

to 0b. Required EH_VOUT_I_SEL and EH_VOUT_V_SEL need to be set in that  

EH_CONFIG byte. Desired energy harvesting mode (EH_MODE) needs to be configured  

in CONFIG_0 byte of block 37h. In case of energy harvesting is enabled already during  

boot (EH_ENABLE bit of EH_CONFIG is 1b), or energy harvesting is not used at all, this  

register byte gives no information.  

Setting EH_TRIGGER to 1b is needed to trigger power detection.  

Polling for bit EH_LOAD_OK should be used to check, if sufficient energy is available.  

Only if EH_LOAD_OK = 1b, energy harvesting may be enabled via session registers by  

writing 09h to this byte.  

Details can be found in energy harvesting section (see

).  

Table 65.ꢀEnergy Harvesting Configuration Register Location (EH_CONFIG_REG)  

Block Address  

Byte 0  

Byte 1  

Byte 2  

Byte 3  

NFC  

A7h  

EH_COFIG_REG  

RFU  

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Table 66.ꢀEnergy Harvesting Register Value Definition EH_CONFIG_REG)  

Access  

Bit  

Name  

Value Description  

NFC  

Acc.  

0b  

1b  

Field is not sufficient to provied configured  

power on V

OUT

. Do not enable energy  

harvesting.  

7

EH_LOAD_OK  

R

Minimum desired energy available.  

V

OUT

may be enabled. As soon as  

EH_ENABLE is set to 1b, this bit gets  

cleared automatically.  

6 to 4  

RFU  

R

0b  

1b  

When reading, this byte this bit is RFU and  

the value is undefined and may be 0b or  

1b.  

3

EH_TRIGGER  

R/W  

When writing to this byte, this bit needs to  

be set to 1b always  

2 to 1  

0

RFU  

R

0b  

1b  

Energy Harvesting disabled (default)  

Energy Harvesting enabled  

EH_ENABLE  

R/W  

8.1.4.6 Event

 

detection register  

Event detection and field detection functionality define the behavior of the ED pin  

depending on various events. Indicated event may be changed during one session. More  

details can be found in ED section (see

).  

8.1.4.7 System

 

reset generation  

System reset can be generated by writing to RESET_GEN_REG register using WRITE  

CONFIG command (see

). Writing E7h will trigger the system reset. This  

byte gets automatically reset after the system reset.  

Table 67.ꢀRESET_GEN_REG location  

Block Address  

Byte 0  

NFC  

Byte 1  

Byte 2  

Byte 3  

AAh  

RESET_GEN_REG  

RFU  

8.1.4.8 Clear

 

event detection register  

Event detection pin is cleared i.e. released when writing 01h to the Clear Event Detection  

Register. The bit gets cleared after releasing the ED pin automatically. Other values are  

RFU.  

Table 68.ꢀED_INTR_CLEAR_REG location  

Block Address  

Byte 0  

NFC  

Byte 1  

Byte 2  

Byte 3  

ED_INTR_  

ABh  

CLEAR_REG  

RFU  

NTP5210  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

8.2 NFC

 

interface  

The definition of the NFC interface is according to the

and

. The details of passive communication mode are described in

.  

8.2.1 Passive

 

communication mode  

Main uses cases for passive communication mode are Smart Metering, Home  

automation and in the box configuration. With antenna sizes of Class 4 or bigger, energy  

harvesting on the one side and long-distance read/write access to the EEPROM is  

possible in a very efficient way.  

8.2.2 State

 

diagram and state transitions  

The state diagram illustrates the different states and state transitions of NTAG 5 switch.  

POWER-OFF  

out of field  

in field  

READY  

QUIET  

SELECTED  

aaa-035475  

Figure 6.ꢀState Machine and State Transitions  

8.2.2.1 POWER-OFF

 

state  

8.2.2.1.1 State

 

transitions from and to POWER-OFF state  

If NFC field is switched off or below, H

MIN

NTAG 5 switch goes to POWER-OFF state.  

POWER-OFF state will be left to READY state no later than 1 ms after NTAG 5 switch is  

powered by an NFC field greater than H

MIN  

.

NOTE: When loading default data to mirrored SRAM, start-up time, dependent on the  

pre-loaded bytes, might be greater than 1 ms.  

8.2.2.2 READY

 

state  

8.2.2.2.1 Transitions

 

between READY and SELECTED state  

Transition from READY to SELECTED state is done when  

•

receiving a SELECT command with a matching UID  

NTP5210  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

8.2.2.2.2 Transitions

 

between READY and QUIET state  

Transition from READY to QUIET state is done when  

•

receiving a STAY QUIET command with a matching UID  

•

receiving a (FAST) INVENTORY READ command (extended mode) with Quiet_Flag  

set  

8.2.2.2.3 Commands

 

which stay in READY state  

NTAG 5 switch stays in READY state when  

•

receiving any other command where Select_Flag is not set  

8.2.2.3 SELECTED

 

state  

8.2.2.3.1 Transitions

 

between SELECTED and READY state  

Transition from SELECTED to READY state is done by  

•

receiving a RESET TO READY command where Select_Flag is set  

•

receiving a SELECT command with a different UID  

8.2.2.3.2 Transitions

 

between SELECTED and QUIET state  

Transition from SELECTED to QUIET state is done when  

•

receiving a STAY QUIET command with a matching UID  

8.2.2.3.3 Commands

 

which stay in SELECTED state  

NTAG 5 switch stays in SELECTED state when  

•

receiving any other command where Select_Flag is set  

8.2.2.4 QUIET

 

state  

8.2.2.4.1 Transitions

 

between QUIET and READY state  

Transition from QUIET to READY state is done by  

•

receiving a RESET_TO_READY command  

8.2.2.4.2 Transitions

 

between QUIET and SELECTED state  

Transition from QUIET to SELECTED state is done by  

•

receiving a SELECT command with a matching UID  

8.2.2.4.3 Commands

 

which stay in QUIET state  

NTAG 5 switch stays in QUIET state when  

•

receiving any other command where Addressed_Flag is set AND Inventory_Flag is not  

set  

8.2.3 Command

 

set  

ISO/IEC 15693 mandatory commands are  

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NTAG 5 switch – NFC Forum-compliant PWM and GPIO bridge  

•

INVENTORY  

•

STAY QUIET  

NFC Forum Type 5 Tag mandatory commands are  

•

READ SINGLE BLOCK  

•

WRITE SINGLE BLOCK  

•

LOCK SINGLE BLOCK  

On top of those, all optional commands of ISO/IEC 15693 are implemented. Several  

customer-specific commands are implemented to, e.g., improve overall transaction time.  

These custom commands all use NXP manufacturer code 04h.  

A complete list of all supported commands is given in below table.  

Table 69.ꢀNFC command set supported by NTAG 5 switch  

Code ISO/IEC

 

15693 NFC

 

Forum T5T  

Command name  

01h  

02h  

Mandatory  

Mandatory  

Mandatory  

Mandatory  

INVENTORY (see

and

)  

STAY QUIET (see

) and

–  

SLPV_REQ)  

20h  

21h  

22h  

23h  

Optional  

Optional  

Optional  

Optional  

Mandatory  

READ SINGLE BLOCK (see

and

–  

READ_SINGLE_BLOCK_REQ)  

Mandatory in READ/WRITE  

state  

WRITE SINGLE BLOCK (see

and

–  

WRITE_SINGLE_BLOCK_REQ)  

Optional  

LOCK BLOCK (see

and

–  

LOCK_SINGLE_BLOCK_REQ)  

Optional  

READ MULTIPLE BLOCKS (

and

–  

READ_MULTIPLE_BLOCK_REQ)  

25h  

26h  

27h  

28h  

29h  

2Ah  

2Bh  

2Ch  

Optional  

Optional  

Optional  

Optional  

Optional  

Optional  

Optional  

Optional  

Optional  

SELECT (see

and

– SELECT_REQ)  

RESET TO READY (see

)  

WRITE AFI (see

)  

Not defined  

Not defined  

Not defined  

Not defined  

Not defined  

Not defined  

Not defined  

LOCK AFI (see

)  

WRITE DSFID (see

)  

LOCK DSFID (see

)  

GET SYSTEM INFORMATION (see

)  

GET MULTIPLE BLOCK SECURITY STATUS (see

)  

2Dh  

3Bh  

Optional  

Optional  

Not defined  

Not defined  

FAST READ MULTIPLE BLOCKS (see

)  

EXTENDED GET SYSTEM INFORMATION (see

)  

3Ch  

3Dh  

Optional  

Optional