NXP-Semicon-OM966302HNQL

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OM9663

High performance NFC reader solution

Rev. 3.0 — 9 December 2013

Product data sheet

COMPANY PUBLIC

1. Introduction

This document describes the functionality and electrical specifications of the contactless

reader/writer IC OM9663.

2. General

description

The OM9663 is a highly integrated transceiver IC for contactless communication at

13.56 MHz.

The OM9663 transceiver IC supports the following operating modes

•

Read/write mode supporting ISO/IEC 14443A/MIFARE

•

Read/write mode supporting ISO/IEC 14443B

•

Read/write mode supporting JIS X 6319-4 (comparable with FeliCa

(see

Section 21.5

) scheme)

•

Passive initiator mode according to ISO/IEC 18092

•

Read/write mode supporting ISO/IEC 15693

•

Read/write mode supporting ICODE EPC UID/ EPC OTP

•

Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

The OM9663’s internal transmitter is able to drive a reader/writer antenna designed to

communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional

active circuitry. The digital module manages the complete ISO/IEC 14443A framing and

error detection functionality (parity and CRC).

The OM9663 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,

MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The OM9663

supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.

The OM9663 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer communication

scheme except anticollision. The anticollision needs to be implemented in the firmware of

the host controller as well as in the upper layers.

The OM9663 is able to demodulate and decode FeliCa coded signals.The FeliCa receiver

part provides the demodulation and decoding circuitry for FeliCa coded signals. The

OM9663 handles the FeliCa framing and error detection such as CRC. The OM9663

supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.

1. In

the following the word FeliCa is used for JIS X 6319-4

OM9663

NXP Semiconductors

High performance NFC reader solution

The OM9663 is supporting the P2P passive initiator mode in accordance with

ISO/IEC 18092.

The OM9663 supports the vicinity protocol according to ISO/IEC15693, EPC UID and

ISO/IEC 18000-3 mode 3/ EPC Class-1 H

The following host interfaces are supported:

•

Serial Peripheral Interface (SPI)

•

Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)

•

C-bus interface (two versions are implemented: I2C and I2CL)

The OM9663 supports the connection of a secure access module (SAM). A dedicated

separate I2C interface is implemented for a connection of the SAM. The SAM can be used

for high secure key storage and acts as a very performant crypto coprocessor. A

dedicated SAM is available for connection to the OM9663.

3. Features

and benefits



High RF output power frontend IC for transfer speed up to 848 kbit/s



Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B and FeliCa



P2P passive initiator mode in accordance with ISO/IEC 18092



Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC

Class-1 HF



Supports MIFARE Classic encryption in read/write mode



Low-Power Card Detection



Compliance to “EMV contactless protocol specification V2.0.1” on RF level can be

achieved



Antenna connection with minimum number of external components



Supported host interfaces:



SPI up to 10 Mbit/s



C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus



RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin

voltage supply



Separate I

C-bus interface for connection of a secure access module (SAM)



FIFO buffer with size of 512 byte for highest transaction performance



Flexible and efficient power saving modes including hard power down, standby and

low-power card detection



Cost saving by integrated PLL to derive system CPU clock from 27.12 MHz RF quartz

crystal



3 V to 5.5 V power supply



Up to 8 free programmable input/output pins



Typical operating distance in read/write mode for communication to a

ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and

tuning

OM9663

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Product data sheet

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High performance NFC reader solution

4. Quick

reference data

Table 1.

Symbol

Quick reference data

Parameter

Conditions

Min

Typ

Max

5.5

Unit

supply voltage

[1]

[2]

DD(TVDD)

DD(PVDD)

TVDD supply voltage

PVDD supply voltage

power-down current

supply current

PDOWN pin pulled HIGH

no supply voltage applied

–



–

100

+25

[3][4]

DD(TVDD)

amb

TVDD supply current

ambient temperature

storage temperature

–

200

+85



stg

+100



[1] VDD(PVDD)

must always be the same or lower voltage than VDD.

[2] I

is the sum of all supply currents

[3] I

DD(TVDD)

depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2.

[4] Typical

value: Assumes the usage of a complementary driver configuration and an antenna matched to 40



between pins TX1, TX2 at

13.56 MHz.

5. Ordering

information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

OM966301HN/TRAYB

[1]

OM966301HN/TRAYM

[2]

HVQFN32

plastic thermal enhanced very thin quad flat package; no

SOT617-1

leads; MSL2, 32 terminals + 1 central ground; body 5



0.85 mm

OM966302HN/TRAYB

[1]

OM966302HN/TRAYBM

[2]

OM966302HN/T/R

[3]

plastic thermal enhanced very thin quad flat package; no

SOT617-1

leads; MSL1, 32 terminals + 1 central ground; body 5



0.85 mm

[1] Delivered

in one tray

[2] Delivered

in five trays

[3] Delivered

on reel with 6000 pieces

OM9663

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6. Block

diagram

The analog interface handles the modulation and demodulation of the antenna signals for

the contactless interface.

The contactless UART manages the protocol dependency of the contactless interface

settings managed by the host.

The FIFO buffer ensures fast and convenient data transfer between host and the

contactless UAR

The register bank contains the settings for the analog and digital functionality.

ANALOG

INTERFACE

CON

ACTLESS

UART

ANTENNA

FIFO

BUFFER

SERIAL UART

SPI

I C-BUS

HOST

001aaj627

Fig 1.

Simplified block diagram of the OM9663

7. Pinning

information

terminal 1

index area

TDO

TDI

SDA

SCL

TMS

CLKOUT

PDOWN

XTAL2

XTAL1

TVDD

TX1

TCK

33 VSS

SIGIN

SIGOUT

DVDD

VDD

001aam004

Transparent top view

(1) Pin

33 VSS – heatsink connection

Fig 2.

Pinning configuration HVQFN32 (SOT617-1)

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7.1 Pin

description

Table 3.

Pin description

Symbol Type

Description

TDO

test data output for boundary scan interface

test data input boundary scan interface

test mode select boundary scan interface

test clock boundary scan interface

Contactless communication interface output.

Contactless communication interface input.

digital power supply buffer

[1]

TDI

TMS

TCK

SIGIN

SIGOUT

DVDD

VDD

PWR

power supply

AVDD

AUX1

AUX2

RXP

PWR

analog power supply buffer

[1]

auxiliary outputs: Pin is used for analog test signal

receiver input pin for the received RF signal.

internal receiver reference voltage

[1]

RXN

VMID

TX2

PWR

transmitter 2: delivers the modulated 13.56 MHz carrier

transmitter ground, supplies the output stage of TX1, TX2

transmitter 1: delivers the modulated 13.56 MHz carrier

transmitter voltage supply

TVSS

TX1

PWR

TVDD

XTAL1

PWR

crystal oscillator input: Input to the inverting amplifier of the oscillator. This is pin is also the

input for an externally generated clock (fosc = 27,12 MHz)

XTAL2

PDOWN

CLKOUT

SCL

crystal oscillator output: output of the inverting amplifier of the oscillator

Power Down

clock output

Serial Clock line

SDA

I/O

PWR

Serial Data Line

PVDD

IFSEL0

IFSEL1

IF0

pad power supply

host interface selection 0

host interface selection 1

I/O

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

interface pin, multifunction pin: Can be assigned to host interface SPI, I

C, I

C-L

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I

C, I

C-L

interrupt request: output to signal an interrupt event

ground and heatsink connection

IF1

IF2

IF3

IRQ

VSS

PWR

[1] This

pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.

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8. Functional

description

SAM interface

SDA

SCL

I C,

FIFO

512 Bytes

EEPROM

8 kByte

LOGICAL

SPI

host interfaces

RESET

LOGIC

IFSEL1

IFSEL0

PDOWN

I C

IF0

IF1

IF2

IF3

REGISTERS

RS232

SPI

STATEMACHINES

ANALOGUE FRONT-END

VDD

VSS

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

VOLTAGE

REGULATOR

3/5 V =>

1.8 V

PVDD

TVDD

TVSS

AVDD

DVDD

TCK

TDI

TMS

TDO

BOUNDARY

SCAN

DVDD

AVDD

POR

ADC

RNG

PLL

TIMER4

TIMER0..3

(WAKE-UP

TIMER)

CODEC

DECOD

LFO

CLKOUT

CL-

COPRO

AUX1

AUX2

SIGIN/

SIGOUT

CONTROL

INTERRUPT

CONTROLLER

CRC

SIGPRO

OSC

RXP

VMID RXN

TX2

TX1

XTAL2

XTAL1

IRQ

SIGIN SIGOUT

001aam005

Fig 3.

Detailed block diagram of the OM9663

OM9663

NXP Semiconductors

High performance NFC reader solution

8.1 Interrupt

controller

The interrupt controller handles the enabling/disabling of interrupt requests. All of the

interrupts can be configured by firmware. Additionally, the firmware has possibilities to

trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0

and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En

and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt

controller registers is implemented.

The OM9663 indicates certain events by setting bit IRQ in the register Status1Reg and

additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the

host using its interrupt handling capabilities. This allows the implementation of efficient

host software.

The following table shows the available interrupt bits, the corresponding source and the

condition for its activation. The interrupt bit TimernIrq in register IRQ1 indicates an

interrupt set by the timer unit. The setting is done if the timer underflows.

The TxIrq bit in register IRq0 indicates that the transmission is finished. If the state

changes from sending data to transmitting the end of the frame pattern, the transmitter

unit sets the interrupt bit automatically.

The bit RxIrq in register IRQ0 indicates an interrupt when the end of the received data is

detected.

The bit IdleIrq in register IRQ0 is set if a command finishes and the content of the

command register changes to idle.

The waterlevel defines both – minimum and maximum warning levels – counting from top

and from bottom of the FIFO by a single value.

The bit HiAlertIrq in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that

means the FIFO data number has reached the top level as configured by the bit

WaterLevel.

The bit LoAlertIrq in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that

means the FIFO data number has reached the bottom level as configured by the bit

WaterLevel.

The bit ErrIrq in register IRQ0 indicates an error detected by the contactless UART during

receive. This is indicated by any bit set to logic 1 in register Error.

The bit LPCDIrq in register IRQ0 indicates a card detected.

The bit RxSOFIrq in register IRQ0 indicates a detection of a SOF or a subcarrier by the

contactless UART during receiving.

The bit GlobalIRq in register IRQ1 indicates an interrupt occurring at any other interrupt

source when enabled.

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Table 4.

Interrupt sources

Interrupt bit

Timer0Irq

Timer1Irq

Timer2Irq

Timer3Irq

TxIrq

Interrupt source

Timer Unit

Is set automatically, when

the timer register T0 CounterVal underflows

the timer register T1 CounterVal underflows

the timer register T2 CounterVal underflows

the timer register T3 CounterVal underflows

a transmitted data stream ends

Timer Unit

Transmitter

RxIrq

Receiver

a received data stream ends

IdleIrq

Command Register

FIFO-buffer pointer

a command execution finishes

HiAlertIrq

the FIFO data number has reached the top level as

configured by the bit WaterLevel

LoAlertIrq

FIFO-buffer pointer

the FIFO data number has reached the bottom level as

configured by the bit WaterLevel

ErrIrq

contactless UART

LPCD

a communication error had been detected

LPCDIrq

a card was detected when in low-power card detection

mode

RxSOFIrq

GlobalIrq

Receiver

detection of a SOF or a subcarrier

all interrupt sources

will be set if another interrupt request source is set

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8.2 Timer

module

Timer module overview

The OM9663 implements five timers. Four timers -Timer0 to Timer3 – have an input clock

that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from

the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each timer

implements a counter register which is 16 bit wide. A reload value for the counter is

defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo. The

fifth timer Timer4 is intended to be used as a wakeup timer and is connected to the

internal LFO (Low Frequency Oscillator) as input clock source.

The TControl register allows the global start and stop of each of the four timers Timer0 to

Timer3. Additionally, this register indicates if one of the timers is running or stopped. Each

of the five timers implements an individual configuration register set defining timer reload

value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,

T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.

T0Control).

The external host may use these timers to manage timing relevant tasks. The timer unit

may be used in one of the following configurations:

•

Time-out counter

•

Watch-dog counter

•

Stop watch

•

Programmable one-shot timer

•

Periodical trigger

The timer unit can be used to measure the time interval between two events or to indicate

that a specific event has occurred after an elapsed time. The timer register content is

modified by the timer unit, which can be used to generate an interrupt to allow an host to

react on this event.

The counter value of the timer is available in the registers T(x)CounterValHi,

T(x)CounterValLo. The content of these registers is decremented at each timer clock.

If the counter value has reached a value of 0000h and the interrupts are enabled for this

specific timer, an interrupt will be generated as soon as the next clock is received.

If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit

Timer(x)Irq can be set and reset by the host controller. Depending on the configuration,

the timer will stop counting at 0000h or restart with the value loaded from registers

T(x)ReloadHi, T(x)ReloadLo.

The counting of the timer is indicated by bit TControl.T(x)Running.

The timer can be started by setting bits TControl.T(x)Running and

TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and

clearing TControl.T(x)Running.

Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful

if dedicated protocol requirements need to be fulfilled.

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8.2.1 Timer

modes

8.2.1.1 Time-Out-

and Watch-Dog-Counter

Having configured the timer by setting

and starting the counting

of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit

decrements the

T(x)CounterValue

the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received

from the card), the timer unit stops (no interrupt is generated).

If no stop event occurs, the timer unit continues to decrement the counter registers until

the content is zero and generates a timer interrupt request at the next clock cycle. This

allows to indicate to a host that the event did not occur during the configured time interval.

8.2.1.2 Wake-up

timer

The wake-up Timer4 allows to wakeup the system from standby after a predefined time.

The system can be configured in such a way that it is entering the standby mode again in

case no card had been detected.

This functionality can be used to implement a low-power card detection (LPCD). For the

low-power card detection it is recommended to set T4Control.T4AutoWakeUp and

T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system in

standby. The internal low frequency oscillator (LFO) is then used as input clock for this

Timer4. If a card is detected the host-communication can be started. If bit

T4Control.T4AutoWakeUp is not set, the OM9663 will not enter the standby mode again

in case no card is detected but stays fully powered.

8.2.1.3 Stop

watch

The elapsed time between a configured start- and stop event may be measured by the

OM9663 timer unit. By setting the registers

T(x)ReloadValueHi, T(x)reloadValueLo

the

timer starts to decrement as soon as activated. If the configured stop event occurs, the

timers stops decrementing. The elapsed time between start and stop event can then be

calculated by the host dependent on the timer interval TTimer:







Treload



Timer



Timer

value

(1)

If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,

the performed time measurement according to the formula above is not correct.

8.2.1.4 Programmable

one-shot timer

The host configures the interrupt and the timer, starts the timer and waits for the interrupt

event on pin IRQ. After the configured time the interrupt request will be raised.

8.2.1.5 Periodical

trigger

If the bit

T(x)Control.T(x)AutoRestart is set and the interrupt is activated

, an interrupt

request will be indicated periodically after every elapsed timer period

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8.3 Contactless

interface unit

The contactless interface unit of the OM9663 supports the following read/write operating

modes:

•

ISO/IEC14443A/MIFARE

•

ISO/IEC14443B

•

FeliCA

•

ISO/IEC15693/ICODE

•

ICODE EPC UID

•

ISO/IEC 18000-3 mode 3/ EPC Class-1 HF

BATTERY/POWER SUPPLY

READER IC

ISO/IEC 14443 A CARD

MICROCONTROLLER

reader/writer

001aal996

Fig 4.

Read/write mode

A typical system using the OM9663 is using a microcontroller to implement the higher

levels of the contactless communication protocol and a power supply (battery or external

supply).

8.3.1 ISO/IEC14443A/MIFARE

functionality

The physical level of the communication is shown in

Figure 5

(1)

ISO/IEC 14443 A

ISO/IEC 14443 A CARD

READER

(2)

001aam268

(1) Reader

to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s

(2) Card

to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed

106 kbit/s to 848 kbit/s

Fig 5.

ISO/IEC 14443 A/MIFARE read/write mode communication diagram

The physical parameters are described in

ble 5

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Table 5.

Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication

direction

Signal type

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

Reader to card (send

reader side

100 % ASK

100% ASK

data from the OM9663

modulation

to a card)

fc = 13.56 MHz

bit encoding

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

modified Miller

encoding

bit rate [kbit/s]

fc / 128

fc / 64

fc / 32

fc / 16

Card to reader

(OM9663 receives data

modulation

card side

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

from a card)

subcarrier

fc / 16

frequency

bit encoding

Manchester

encoding

BPSK

The OM9663 connection to a host is required to manage the complete

ISO/IEC 14443 A/MIFARE protocol.

Figure 6

shows the data coding and framing

according to ISO/IEC 14443A /MIFARE.

ISO/IEC 14443 A framing at 106 kBd

start

8-bit data

odd

parity

start bit is 1

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd

start

even

parity

8-bit data

odd

parity

odd

parity

start bit is 0

burst of 32

subcarrier clocks

even parity at the

end of the frame

001aak585

Fig 6.

Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A

part 3 and handles parity generation internally according to the transfer speed.

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8.3.2 ISO/IEC14443B

functionality

The physical level of the communication is shown in

Figure 7

(1)

ISO/IEC 14443 B

ISO/IEC 14443 B CARD

READER

(2)

001aal997

(1) Reader

to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s

(2) Card

to reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s

to 848 kbit/s

Fig 7.

ISO/IEC 14443 A/MIFARE read/write mode communication diagram

The physical parameters are described in

ble 6

Table 6.

Communication overview for ISO/IEC 14443 B reader/writer

Communication

direction

Signal type

Transfer speed

106 kbit/s

212 kbit/s

424 kbit/s

848 kbit/s

Reader to card (send

reader side

10 % ASK

data from the OM9663

modulation

to a card)

fc =

13.56 MHz

bit encoding

NRZ

bit rate [kbit/s]

128 / fc

64 / fc

32 / fc

16 / fc

Card to reader

(OM9663 receives data

modulation

card side

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

subcarrier load

modulation

from a card)

subcarrier

fc / 16

fc /

frequency

bit encoding

BPSK

The OM9663 connected to a host is required to manage the complete ISO/IEC 14443 B

protocol. The following

Figure 8 “SOF and EOF according to ISO/IEC 14443 B”

shows the

ISO/IEC 14443B SOF and EO

Start of Frame (SOF)

sequence

9.44 μs

UNMODULATED (SUB)

”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0”

”1” ”1”

DATA

CARRIER

End of Frame (EOF)

sequence

9.44 μs

UNMODULATED (SUB)

CARRIER

LAST CHARACTER

”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0” ”0”

001aam270

Fig 8.

SOF and EOF according to ISO/IEC 14443 B

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8.3.3 FeliCa

functionality

The FeliCa mode is the general reader/writer to card communication scheme according to

the FeliCa specification. The communication on a physical level is shown in

Figure 9

1. PCD to PICC 8-30 % ASK

Manchester Coded,

FeliCa CARD

(PICC)

FeliCa READER

(PCD)

baudrate 212 to 424 kbaud

2. PICC to PCD, >12 % Loadmodulation

Manchester Coded,

baudrate 212 to 424 kbaud

001aam271

Fig 9.

FeliCa read/write communication diagram

The physical parameters are described in

ble 7

Table 7.

Communication overview for FeliCa reader/writer

Communication

direction

Signal type

Transfer speed FeliCa

FeliCa higher transfer

speeds

212 kbit/s

424 kbit/s

Reader to card (send

reader side

8 % to 30 % ASK

data from the OM9663 to

modulation

a card)

fc = 13.56 MHz

bit encoding

Manchester encoding

fc/64

Manchester encoding

fc/32

bit rate

Card to reader (OM9663

card side load

30/H^1.2

receives data from a

card)

modulation

(H = field strength [A/m])

bit encoding

Manchester encoding

The OM9663 needs to be connected to a dedicated host to be able to support the

complete FeliCa protocol.

8.3.3.1 FeliCa

framing and coding

Table 8.

FeliCa framing and coding

Preamble (Hex.)

Sync

Len n-Data

CRC

(Hex.)

nable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)

and 2 bytes sync bytes (B2h, 4Dh) are sent to synchronize the receiver.

The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.

The CRC calculation is done according to the FeliCa definitions with the MSB first.

ransmit data on the RF interface, the host controller has to send the Len- and data-

bytes to the OM9663’s FIFO-buffer. The preamble and the sync bytes are generated by

the OM9663 automatically and must not be written to the FIFO by the host controller. The

OM9663 performs internally the CRC calculation and adds the result to the data frame.

8.3.4 ISO/IEC15693

functionality

The physical parameters are described in

ble 9

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Table 9.

Communication overview for ISO/IEC 15693 reader/writer reader to label

Communication

direction

Signal type

Transfer speed

fc / 8192 kbit/s

fc / 512 kbit/s

Reader to label (send

reader side

data from the OM9663

modulation

10 % to 30 % ASK or

100 % ASK

10 % to 30 % ASK 90 %

to 100 % ASK

to a card)

bit encoding

1/256

1/4

data rate

1,66 kbit/s

26,48kbit/s

Table 10.

Communication overview for ISO/IEC 15693 reader/writer label to reader

Communication Signal

type Transfer

speed

direction

6.62 (6.67) kbit/s

13.24

26.48

(26.69) kbit/s

52.96 kbit/s

kbit/s

[1]

Label to reader

(OM9663

receives data

from a card)

fc = 13.56 MHz

card side

modulation

not supported

single (dual)

single

subcarrier

load

modulation

ASK

subcarrier

load

modulation

ASK

bit length

(



–

37.76 (37.46)

18.88

ncoding –

Manchester

coding

Manchester

coding

subcarrier

frequency

[MHz]

–

fc / 32

(fc / 28)

[1] Fast

inventory (page) read command only (ICODE proprietary command).

pulse

modulated

~9.44

~18.88

carrier

0 1 2 3 4

2 2 2 2

5 5 5 5

2 3 4 5

~4,833 ms

001aam272

Fig 10.

Data coding according to ISO/IEC 15693. standard mode reader to label

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8.3.5 EPC-UID/UID-OTP

functionality

The physical parameters are described in

ble 11

Table 11.

Communication overview for EPC/UID

Communication

direction

Signal type

Transfer speed

26.48 kbit/s

52.96 kbit/s

Reader to card (send

data from the OM9663

to a card)

reader side modulation

10 % to 30 % ASK

bit encoding

RTZ

bit length

37.76



Card to reader

(OM9663 receives

data from a card)

card side modulation

single subcarrier load

modulation

bit length

18.88



bit encoding

Manchester coding

Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientific

and medical) Band Class 1 Radio Frequency Identification

g Interface Specification

(Candidate Recommendation, Version 1.0.0).

8.3.6 ISO/IEC

18000-3 mode 3/ EPC Class-1 HF functionality

The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For a

detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1

HF standard.

8.3.7 ISO/IEC

18092 mode

The OM9663 supports Passive Initiator Communication mode at the transfer speeds

106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.

•

Passive communication mode means that the target answers to an initiator command

in a load modulation scheme. The initiator is active in terms of generating the RF field.

•

Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092

communication.

•

rget: responds to initiator command either in a load modulation scheme in Passive

communication mode or using a self generated and self modulated RF field for Active

Communication mode.

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8.3.7.1 Passive

communication mode

Passive communication mode means that the target answers to an initiator command in a

load modulation scheme. The initiator is active meaning generating the RF field.

1. initiator starts communication

at selected transfer speed

host

NFC INITIATOR

NFC TARGET

2. targets answers using

load modulated data

at the

same transfer speed

powered to

powered for

generate RF field

digital processing

001aan217

Fig 11.

Passive communication mode

Table 12.

Communication overview for Passive communication mode

Communication

direction

106 kbit/s

212 kbit/s

424 kbit/s

Initiator



target

According to

According to FeliCa, 8 % to 30 % ASK

Manchester Coded

ISO/IEC 14443A

100 % ASK, Modified

Miller Coded

rget



initiator

According to

According to FeliCa, > 12 % ASK

ISO/IEC 14443A subcarrier

Manchester Coded

load modulation,

Manchester Coded

The contactless UART of OM9663 and a dedicated host controller are required to handle

the ISO/IEC 18092 passive initiator protocol.

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8.3.7.2 ISO/IEC

18092 framing and coding

The ISO/IEC 18092 framing and coding in Passive communication mode is defined in the

ISO/IEC 18092 standard.

Table 13.

Framing and coding overview

Transfer speed

106 kbit/s

Framing and Coding

According to the ISO/IEC 14443A/MIFARE scheme

According to the FeliCa scheme

212 kbit/s

424 kbit/s

8.3.7.3 ISO/IEC

18092 protocol support

The ISO/IEC 18092 protocol is not described in this document. For a detailed explanation

of the protocol, refer to the ISO/IEC 18092 standard.

8.3.8 EPC

Class-1 HF and ICODE

8.3.8.1 Data

encoding ICODE

The ICODE protocols have mainly three different methods of data encoding:

•

“1” out of “4” coding scheme

•

“1” out of “256” coding scheme

•

“Return to Zero” (RZ) coding scheme

Data encoding for all three coding schemes is done by the ICODE generator.

The supported EPC Class-1 HF modes are:

•

2 pulse for 424 kbit subcarrier

•

4 pulse for 424 kbit subcarrier

•

2 pulse for 848 kbit subcarrier

•

4 pulse for 848 kbit subcarrier

8.4 Host

interfaces

8.4.1 Host

interface configuration

The OM9663 supports direct interfacing of various hosts as the SPI, I

C, I

CL and serial

UART interface type. The OM9663 resets its interface and checks the current host

interface type automatically having performed a power-up or resuming from power down.

The OM9663 identifies the host interface by the means of the logic levels on the control

pins after the Cold Reset Phase. This is done by a combination of fixed pin

connections.The following table shows the possible configurations defined by

IFSEL1,IFSEL0:

Table 14.

Connection scheme for detecting the different interface types

Pin Symbol

UART

–

SPI

C-L

ADR1

SCL

IF0

IF1

IF2

MOSI

SCK

MISO

ADR1

SCL

ADR2

SDA

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Table 14.

Connection scheme for detecting the different interface types

Pin Symbol

IF3

UART

SPI

NSS

SDA

C-L

ADR2

IFSEL0

IFSEL1

8.4.2 SPI

interface

8.4.2.1 General

READER IC

SCK

IF1

IF0

IF2

IF3

MOSI

MISO

NSS

001aal998

Fig 12.

Connection to host with SPI

The OM9663 acts as a slave during the SPI communication. The SPI clock SCK has to be

generated by the master. Data communication from the master to the slave uses the Line

MOSI. Line MISO is used to send data back from the OM9663 to the master.

A serial peripheral interface (SPI compatible) is supported to enable high speed

communication to a host. The implemented SPI compatible interface is according to a

standard SPI interface. The SPI compatible interface can handle data speed of up to 10

Mbit/s. In the communication with a host OM9663 acts as a slave receiving data from the

external host for register settings and to send and receive data relevant for the

communication on the RF interface.

On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line

shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling

edge. The same is valid for the MISO line. Data is provided by the OM9663 on the falling

edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.

8.4.2.2 Read

data

ead out data from the OM9663 by using the SPI compatible interface the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Table 15.

Byte Order for MOSI and MISO

byte 0

byte 1

byte 2

byte 3 to n-1

byte n

byte n+1

00h

MOSI address

address 1

data 0

address 2

data 1

……..

address n

data n



MISO

data n

Remark:

The Most Significant Bit (MSB) has to be sent first.

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8.4.2.3 Write

data

rite data to the OM9663 using the SPI interface the following byte order has to be

used. It is possible to write more than one byte by sending a single address byte

(see.8.5.2.4).

The first send byte defines both, the mode itself and the address byte.

Table 16.

Byte Order for MOSI and MISO

byte 0

address 0

byte 1

data 0

byte 2

data 1

3 to n-1

……..

byte n

data n



byte n + 1

data n

MOSI

MISO

……..

Remark:

The Most Significant Bit (MSB) has to be sent first.

8.4.2.4 Address

byte

The address byte has to fulfil the following format:

The LSB bit of the first byte defines the used mode.

ead data from the OM9663 the

LSB bit is set to logic 1.

rite data to the OM9663 the LSB bit has to be cleared. The

bits 6 to 0 define the address byte.

NOTE: When writing the sequence [address byte][data1][data2][data3]…, [data1] is written

to address [address byte], [data2] is written to address [address byte + 1] and [data3] is

written to [address byte + 2].

Exception: This auto increment of the address byte is not performed if data is written to

the FIFO address

Table 17.

Address byte 0 register; address MOSI

address 6

address 5

address 4

address 3

address 2

address 1

address 0

1 (read)

0 (write)

MSB

LSB

8.4.2.5 Timing

Specification SPI

The timing condition for SPI interface is as follows:

Table 18.

Timing conditions SPI

Symbol

SCKL

Parameter

Min

–

Typ

Max

Unit

SCK LOW time

–

SCKH

SCK HIGH time

–

h(SCKH-D)

su(D-SCKH)

h(SCKL-Q)

(SCKL-NSSH)

NSSH

SCK HIGH to data input hold time

data input to SCK HIGH set-up time

SCK LOW to data output hold time

SCK LOW to NSS HIGH time

NSS HIGH time

–

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SCKL

NSSH

SCKL

SCKH

SCK

h(SCKL-Q)

h(SCKH-D)

h(SCKL-Q)

su(D-SCKH)

MOSI

MISO

MSB

LSB

MSB

LSB

(SCKL-NSSH)

NSS

001aaj641

Fig 13.

Connection to host with SPI

Remark:

end more bytes in one data stream the NSS signal must be LOW during the

send process.

end more than one data stream the NSS signal must be HIGH between

each data stream.

8.4.3 RS232

interface

8.4.3.1 Selection

of the transfer speeds

The internal UART interface is compatible to a RS232 serial interface.

ble 20 “Selectable transfer speeds”

describes examples for different transfer speeds

and relevant register settings. The resulting transfer speed error is less than 1.5 % for all

described transfer speeds. The default transfer speed is 115.2 kbit/s.

hange the transfer speed, the host controller has to write a value for the new transfer

speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set

the transfer speed in the SerialSpeedReg.

ble 19 “Settings of BR_T0 and BR_T1”

describes the settings of BR_T0 and BR_T1.

Table 19.

Settings of BR_T0 and BR_T1

BR_T0

factor BR_T0

range BR_T1

1 to 32

33 to 64

Table 20.

Selectable transfer speeds

Transfer speed (kbit/s)

Serial SpeedReg

Transfer speed accuracy (%)

(Hex.)

7.2



0.25

0.32

9.6

14.4

19.2



0.25

0.32

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Table 20.

Selectable transfer speeds

Transfer speed (kbit/s)

Serial SpeedReg

Transfer speed accuracy (%)

(Hex.)

38.4

0.32

57.6



0.25



0.25



0.06



0.25



0.25

1.45

115.2

128

230.4

460.8

921.6

1228.8

0.32

The selectable transfer speeds as shown are calculated according to the following

formulas:

if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)

if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2

(BR_T0



Remark:

Transfer speeds above 1228.8 kBits/s are not supported.

8.4.3.2 Framing

Table 21.

UART framing

Bit

Length

1 bit

Value

Start bit (Sa)

Data bits

8 bit

Data

Stop bit (So)

1 bit

Remark:

For data and address bytes the LSB bit has to be sent first. No parity bit is used

during transmission.

Read data:

ead out data using the UART interface the flow described below has to be

used. The first send byte defines both the mode itself and the address.The Trigger on pin

IF3 has to be set, otherwise no read of data is possible.

Table 22.

Byte Order to Read Data

Mode

byte 0

address

–

byte 1

–

data 0

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ADDRESS

A6 RD/ So

NWR

DATA

001aam298

Fig 14.

Timing Diagram for UART Read Data

Write data:

rite data to the OM9663 using the UART interface the following sequence has to be

used.

The first send byte defines both, the mode itself and the address.

Table 23.

Byte Order to Write Data

Mode

byte 0

byte 1

address 0

data 0

address 0

ADDRESS

DATA

A6 RD/ So

NWR

ADDRESS

A6 RD/ So

NWR

001aam299

Fig 15.

Timing diagram for UART write data

Remark:

Data can be sent before address is received.

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8.4.4 I

C-bus interface

8.4.4.1 General

An Inter IC (I

C) bus interface is supported to enable a low cost, low pin count serial bus

interface to the host. The implemented I

C interface is mainly implemented according the

NXP Semiconductors I

C interface specification, rev. 3.0, June 2007. The OM9663 can

act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode

plus.

The following features defined by the NXP Semiconductors I

C interface specification,

rev. 3.0, June 2007 are not supported:

•

The OM9663 I2C interface does not stretch the clock

•

The OM9663 I2C interface does not support the general call. This means that the

OM9663 does not support a software reset

•

The OM9663 does not support the I2C device ID

•

The implemented interface can only act in slave mode. Therefore no clock generation

and access arbitration is implemented in the OM9663.

•

High speed mode is not supported by the OM9663

PULL-UP

NETWORK

PULL-UP

NETWORK

READER IC

MICROCONTROLLER

SDA

SCL

001aam000

Fig 16.

C-bus interface

SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.

Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the

C-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in

the fast mode+.

If the I

C interface is selected, a spike suppression according to the I

C interface

specification on SCL and SDA is automatically activated.

For timing requirements refer to

ble 249 “I

C-bus timing in fast mode and fast mode

plus”

8.4.4.2 I

C Data validity

Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state

or LOW state of the data line shall only change when the clock signal on SCL is LOW.

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SDA

SCL

change

data line stable;

data valid

of data

allowed

001aam300

Fig 17.

Bit transfer on the I

C-bus.

8.4.4.3 I

C START and STOP conditions

andle the data transfer on the I

C-bus, unique START (S) and STOP (P) conditions

are defined.

A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is

HIGH.

A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is

HIGH.

The master always generates the START and STOP conditions. The bus is considered to

be busy after the START condition. The bus is considered to be free again a certain time

after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In

this respect, the START (S) and repeated START (Sr) conditions are functionally identical.

Therefore, the S symbol will be used as a generic term to represent both the START and

repeated START (Sr) conditions.

SDA

SCL

SDA

SCL

RT condition

STOP condition

001aam301

Fig 18.

START and STOP conditions

8.4.4.4 I

C byte format

Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB

first, see

Figure 18 “START and STOP conditions”

. The number of transmitted bytes

during one data transfer is unrestricted but shall fulfil the read/write cycle format.

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8.4.4.5 I

C Acknowledge

An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock

pulse is generated by the master. The transmitter of data, either master or slave, releases

the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the

SDA line during the acknowledge clock pulse so that it remains stable LOW during the

HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer, or a

repeated START (Sr) condition to start a new transfer.

A master-receiver shall indicate the end of data to the slave- transmitter by not generating

an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter

shall release the data line to allow the master to generate a STOP (P) or repeated START

(Sr) condition.

DATA

UTPUT

BY TRANSMITTER

not acknowledge

DATA

UTPUT

BY RECEIVERER

acknowledge

SCL FROM

MASTER

clock pulse for

acknowledgement

condition

001aam302

Fig 19.

Acknowledge on the I

C- bus

MSB

acknowledgement

signal from slave

acknowledgement

signal from receiver

byte complete,

interrupt within slave

clock line held low while

interrupts are serviced

3 – 8

ACK

001aam303

Fig 20.

Data transfer on the I

C- bus

8.4.4.6 I

C 7-bit addressing

During the I

C-bus addressing procedure, the first byte after the START condition is used

to determine which slave will be selected by the master.

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Alternatively the I

C address can be configured in the EEPROM. Several address

numbers are reserved for this purpose. During device configuration, the designer has to

ensure, that no collision with these reserved addresses in the system is possible. Check

the corresponding I

C specification for a complete list of reserved addresses.

For all OM9663 devices the upper 5 bits of the device bus address are reserved by NXP

and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address can be

freely configured by the customer in order to prevent collisions with other I

C devices by

using the interface pins (refer to

ble 14

) or the value of the I

C address EEPROM

ble 35

MSB

LSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R/W

slave address

001aam304

Fig 21.

First byte following the START procedure

8.4.4.7 I

C-register write access

rite data from the host controller via I

C to a specific register of the OM9663 the

following frame format shall be used.

The first byte of a frame indicates the device address according to the I

C rules. The

second byte indicates the register address followed by up to n-data bytes. In case the

address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register

address. This enables for example a fast FIFO access. For any other address, the

address pointer is incremented automatically and data is written to the locations [address],

[address+1], [address+2]… [address+(n-1)]

The read/write bit shall be set to logic 0.

8.4.4.8 I

C-register read access

ead out data from a specific register address of the OM9663 the host controller shall

use the procedure:

First a write access to the specific register address has to be performed as indicated in the

following frame:

The first byte of a frame indicates the device address according to the I

C rules. The

second byte indicates the register address. No data bytes are added.

The read/write bit shall be logic 0.

Having performed this write access, the read access starts. The host sends the device

address of the OM9663. As an answer to this device address the OM9663 responds with

the content of the addressed register. In one frame n-data bytes could be read using the

same register address. The address pointing to the register is incremented automatically

(exception: FIFO register address is not incremented automatically). This enables a fast

transfer of register content. The address pointer is incremented automatically and data is

read from the locations [address], [address+1], [address+2]… [address+(n-1)]

In order to support a fast FIFO data transfer, the address pointer is not incremented

automatically in case the address is pointing to the FIFO.

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The read/write bit shall be set to logic 1.

Write Cycle

(W)

I2C slave address

A7-A0

CLRC663 register

address A6-A0

DATA

[7..0]

Ack

[0..n]

Ack

Read Cycle

Ack

(W)

I2C slave address

A7-A0

CLRC663 register

address A6-A0

Ack

Optional, if the previous access was on the same register address

0..n

(R)

I2C slave address

A7-A0

DATA

[7..0]

Ack

[0..n]

Ack

sent by master

sent by slave

DATA

[7..0]

Nack

001aam305

Fig 22.

8.4.4.9 I

CL-bus interface

The OM9663 provides an interface option according to of a logical handling of an I

interface. This logical interface fulfills the I

C specification, but the rise/fall timings will not

be according the I

C standard. Standard I/O pads are used for communication and the

communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast

mode protocol of I

C. The address is 01010xxb, where the last two bits of the address can

be defined by the application. The definition of this bits can be done by two options. With a

pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM.

Refer to the EEPROM configuration in

Section 8.7

Table 24.

Timing parameter I

Parameter

SCL

Min

Max

Unit

MHz

–

HD;STA

LOW

100

–

HIGH

–

SU;SDA

HD;DAT

SU;DAT

SU;STO

BUF

–

200

–

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The pull-up resistor is not required for the I

CL interface. Instead, a on chip buskeeper is

implemented in the OM9663 for SDA of the I

CL interface. This protocol is intended to be

used for a point to point connection of devices over a short distance and does not support

a bus capability.The driver of the pin must force the line to the desired logic voltage.

avoid that two drivers are pushing the line at the same time following regulations must be

fulfilled:

SCL: As there is no clock stretching, the SCL is always under control of the Master.

SDA: The SDA line is shared between master and slave. Therefore the master and the

slave must have the control over the own driver enable line of the SDA pin. The following

rules must be followed:

•

In the idle phase the SDA line is driven high by the master

•

In the time between start and stop condition the SDA line is driven by master or slave

when SCL is low. If SCL is high the SDA line is not driven by any device

•

eep the value on the SDA line a on chip buskeeper structure is implemented for

the line

8.4.5 SAM

interface I

8.4.5.1 SAM

functionality

The OM9663 implements a dedicated I2C interface to integrate a MIFARE SAM (Secure

Access Module) in a very convenient way into applications (e.g. a proximity reader).

The SAM can be connected to the microcontroller to operate like a cryptographic

co-processor. For any cryptographic task, the microcontroller requests a operation from

the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface

to the connected reader IC.

The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient

way to reduce the protocol overhead. In this system configuration, the SAM is integrated

between the microprocessor and the reader IC, connected by one interface to the reader

IC and by another interface to the microcontroller. In this application the microcontroller

accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using an

I2C interface. As the SAM is directly communicating with reader IC, the communication

overhead is reduced. In this configuration, a performance boost of up to 40% can be

achieved for a transaction time.

The MIFARE SAM supports applications using MIFARE cards. For multi application

purposes an architecture connecting the microcontroller additionally directly to the reader

IC is recommended. This is possible by connecting the OM9663 on one interface (SAM

Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/T1AR1070) and by

connecting the microcontroller to the S2C or SPI interface.

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T=1

I2C

SAM

AV2.6

READER

μC

I2C

Reader

aaa-002963

Fig 23.

I2C interface enables convenient MIFARE SAM integration

8.4.5.2 SAM

connection

The OM9663 provides an interface to connect a SAM dedicated to the OM9663. Both

interface options of the OM9663, I

C or I

CL can be used for this purpose. The interface

option of the SAM itself is configured by a host command sent from the host to the SAM.

The I

CL interface is intended to be used as connection between two IC’s over a short

distance. The protocol fulfills the I

C specification, but does support a single device

connected to the bus only.

8.4.6 Boundary

scan interface

The OM9663 provides a boundary scan interface according to the IEEE 1149.1. This

interface allows to test interconnections without using physical test probes. This is done

by test cells, assigned to each pin, which override the functionality of this pin.

e able to program the test cells, the following commands are supported:

Table 25.

Boundary scan command

Value

Command

Parameter in

Parameter out

(decimal)

bypass

–

preload

data (24)

–

sample

–

data (24)

ID code (default)

USER code

Clamp

–

data (32)

–

data (32)

–

HIGH Z

–

extest

data (24)

interface on/off

interface (1)

address (7)

address (7) – data (8)

–

data (8)

–

The Standard IEEE 1149.1 describes the four basic blocks necessary to use this interface:

st Access Port (TAP), TAP controller, TAP instruction register, TAP data register;

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8.4.6.1 Interface

signals

The boundary scan interface implements a four line interface between the chip and the

environment. There are three Inputs:

st Clock (TCK);

st Mode Select (TMS);

Data Input (TDI) and one output

st Data Output (TDO). TCK and TMS are broadcast

signals, TDI to TDO generate a serial line called Scan path.

Advantage of this technique is that independent of the numbers of boundary scan devices

the complete path can be handled with four signal lines.

The signals TCK, TMS are directly connected with the boundary scan controller. Because

these signals are responsible for the mode of the chip, all boundary scan devices in one

scan path will be in the same boundary scan mode.

8.4.6.2 Test

Clock (TCK)

The TCK pin is the input clock for the module. If this clock is provided, the test logic is able

to operate independent of any other system clocks. In addition, it ensures that multiple

boundary scan controllers that are daisy-chained together can synchronously

communicate serial test data between components. During normal operation, TCK is

driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for

extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan

controller does not change and data in the Instruction and Data Registers is not lost.

The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking

occurs if the pin is not driven from an external source.

8.4.6.3 Test

Mode Select (TMS)

The TMS pin selects the next state of the boundary scan controller. TMS is sampled on

the rising edge of TCK. Depending on the current boundary scan state and the sampled

value of TMS, the next state is entered. Because the TMS pin is sampled on the rising

edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the

falling edge of TCK.

Holding TMS high for five consecutive TCK cycles drives the boundary scan controller

state machine to the

st-Logic-Reset state. When the boundary scan controller enters

the

st-Logic-Reset state, the Instruction Register (IR) resets to the default instruction,

IDCODE. Therefore, this sequence can be used as a reset mechanism.

The internal pull-up resistor on the TMS pin is enabled.

8.4.6.4 Test

Data Input (TDI)

The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI

is sampled on the rising edge of TCK and, depending on the current TAP state and the

current instruction, presents this data to the proper shift register chain. Because the TDI

pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on

TDI to change on the falling edge of TCK.

The internal pull-up resistor on the TDI pin is enabled.

8.4.6.5 Test

Data Output (TDO)

The TDO pin provides an output stream of serial information from the IR chain or the DR

chains. The value of TDO depends on the current TAP state, the current instruction, and

the data in the chain being accessed. In order to save power when the port is not being

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used, the TDO pin is placed in an inactive drive state when not actively shifting out data.

Because TDO can be connected to the TDI of another controller in a daisy-chain

configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the

falling edge of TCK.

8.4.6.6 Data

According to the IEEE1149.1 standard there are two types of data register defined:

bypass and boundary scan

The bypass register enable the possibility to bypass a device when part of the scan

path.Serial data is allowed to be transferred through a device from the TDI pin to the TDO

pin without affecting the operation of the device.

The boundary scan register is the scan-chain of the boundary cells. The size of this

8.4.6.7 Boundary

scan cell

The boundary scan cell opens the possibility to control a hardware pin independent of its

normal use case. Basically the cell can only do one of the following: control, output and

input.

IC1

IC2

Boundary scan cell

TDI

TDO

TDI

TDO

TCK

TMS

TCK

TMS

001aam306

Fig 24.

Boundary scan cell path structure

8.4.6.8 Boundary

scan path

This chapter shows the boundary scan path of the OM9663.

Table 26.

Boundary scan path of the OM9663

Number (decimal)

Cell

Port

Function

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

–

Control

Bidir

CLKOUT

–

Control

Bidir

SCL2

–

Control

Bidir

SDA2

–

Control

Bidir

IFSEL0

–

Control

Bidir

IFSEL1

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Table 26.

Boundary scan path of the OM9663

Number (decimal)

Cell

Port

Function

Control

Bidir

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

BC_1

BC_4

BC_1

BC_8

BC_1

BC_8

BC_1

BC_8

–

IF0

–

Control

Bidir

IF1

–

Control

Bidir

IF2

Output2

Bidir

IF3

–

Control

Bidir

IRQ

–

Control

Bidir

SIGIN

–

Control

Bidir

SIGOUT

Refer to the OM9663 BSDL file.

8.4.6.9 Boundary

Scan Description Language (BSDL)

All of the boundary scan devices have a unique boundary structure which is necessary to

know for operating the device. Important components of this language are:

•

available test bus signal

•

compliance pins

•

command register

•

data register

•

boundary scan structure (number and types of the cells, their function and the

connection to the pins.)

The OM9663 is using the cell BC_8 for the IO-Lines. The I

C Pin is using a BC_4 cell. For

all pad enable lines the cell BC1 is used.

The manufacturer’s identification is 02Bh.

•

attribute IDCODEISTER of OM9663: entity is “0001” and — version

•

“0011110010000010b” and — part number (3C82h)

•

“00000010101b” and — manufacturer (02Bh)

•

“1b”;

— mandatory

The user code data is coded as followed:

•

product ID (3 bytes)

•

version

These four bytes are stored as the first four bytes in the EEPROM.

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8.4.6.10 Non-IEEE1149.1

commands

Interface on/off:

With this command the host/SAM interface can be deactivated and the

Read and Write command of the boundary scan interface is activated. (Data = 1). With

Update-DR the value is taken over.

At Capture-DR the actual address is read and stored in the DR.

Shifting the DR is shifting in a new address. With Update-DR this address is taken over

into the actual address.

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8.5 Buffer

8.5.1 Overview

An 512



8-bit FIFO buffer is implemented in the OM9663. It buffers the input and output

data stream between the host and the internal state machine of the OM9663. Thus, it is

possible to handle data streams with lengths of up to 512 bytes without taking timing

constraints into account. The FIFO can also be limited to a size of 255 byte. In this case all

the parameters (FIFO length, Watermark…) require a single byte only for definition. In

case of a 512 byte FIFO length the definition of this values requires 2 bytes.

8.5.2 Accessing

the FIFO buffer

When the



-Controller starts a command, the OM9663 may, while the command is in

progress, access the FIFO-buffer according to that command. Physically only one

FIFO-buffer is implemented, which can be used in input and output direction. Therefore

the



-Controller has to take care, not to access the FIFO buffer in a way that corrupts the

FIFO data.

8.5.3 Controlling

the FIFO buffer

Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be

reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits

are set to logic 0, the actually stored bytes are not accessible any more and the FIFO

buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)

again.

8.5.4 Status

Information about the FIFO buffer

The host may obtain the following data about the FIFO-buffers status:

•

Number of bytes already stored in the FIFO-buffer. Writing increments, reading

decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl

•

Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according

to the value of the water level in register WaterLevel (Register 02h bit [2], Register

03h bit[7:0])

•

Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl

according to the value of the water level in register WaterLevel (Register 02h bit [2],

•

FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was

already full: ErrIrq in register Irq0.

WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and

LoAlert (counting from the FIFO bottom). The OM9663 can generate an interrupt signal if:

•

LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert

in the register FIFOControl changes to 1.

•

HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert

in the register FIFOControl changes to 1.

The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register WaterLevel)

or less can be stored in the FIFO-buffer. It is generated according to the following

equation:

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HiAlert



FiFoSize

–

FiFoLength

 

WaterLevel

(2)

The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less

are actually stored in the FIFO-buffer. It is generated according to the following equation:

LoAlert

FIFOLength



WaterLevel

(3)

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8.6 Analog

interface and contactless UART

8.6.1 General

The integrated contactless UART supports the external host online with framing and error

checking of the protocol requirements up to 848 kbit/s. An external circuit can be

connected to the communication interface pins SIGIN and SIGOUT to modulate and

demodulate the data.

The contactless UART handles the protocol requirements for the communication schemes

in co-operation with the host. The protocol handling itself generates bit- and byte-oriented

framing and handles error detection like Parity and CRC according to the different

contactless communication schemes.

The size, the tuning of the antenna, and the supply voltage of the output drivers have an

impact on the achievable field strength. The operating distance between reader and card

depends additionally on the type of card used.

8.6.2 TX

transmitter

The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an

envelope signal for energy and data transmission. It can be used to drive an antenna

directly, using a few passive components for matching and filtering, see

Section 14

“Application information”

. The signal on TX1 and TX2 can be configured by the register

DrvMode, see

Section 9.8.1 “TxMode”

The modulation index can be set by the TxAmp.

Following figure shows the general relations during modulation

influenced by set_clk_mode

envelope

TX ASK100

TX ASK10

(1)

(2)

time

1: Defined by set_cw_amplitude.

2: Defined by set_residual_carrier.

001aan355

Fig 25.

General dependences of modulation

Note: When changing the continuous carrier amplitude, the residual carrier amplitude also

changes, while the modulation index remains the same.

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The registers

Section 9.8

and

Section 9.10

control the data rate, the framing during

transmission and the setting of the antenna driver to support the requirements at the

different specified modes and transfer speeds.

Table 27.

Settings for TX1 and TX2

TxClkMode

(binary)

Tx1 and TX2 output

Remarks

000

001

010

110

High impedance

–

output pulled to 0 in any case

output pulled to 1 in any case

RF high side push

open drain, only high side (push) MOS supplied

with clock, clock parity defined by invtx; low side

MOS is off

101

111

RF low side pull

open drain, only low side (pull) MOS supplied

with clock, clock parity defined by invtx; high

side MOS is off

13.56 MHz clock derived

from 27.12 MHz quartz

divided by 2

push/pull Operation, clock polarity defined by

invtx; setting for 10% modulation

Table 28.

Setting residual carrier and modulation index by TXamp.set_residual_carrier

set_residual_carrier (decimal)

residual carrier [%]

modulation index [%]

0.5

1.0

2.0

3.1

4.7

5.8

7.0

7.5

8.1

8.7

9.3

9.9

10.5

11.1

11.7

12.4

13.0

13.6

14.3

14.9

16.3

17.6

19.0

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Table 28.

Setting residual carrier

…continued

and modulation index by

set_residual_carrier (decimal)

residual carrier [%]

modulation index [%]

21.2

25.0

29.0

33.3

37.9

42.9

48.1

53.8

60.0

Note: At VDD(TVDD) <5 V and residual carrier settings <50%, the accuracy of the

modulation index may be low in dependency of the antenna tuning impedance

8.6.2.1 Overshoot

protection

The OM9663 provides an overshoot protection for 100% ASK to avoid overshoots during

a PCD communication. Therefore two timers overshoot_t1 and overshoot_t2 can be used.

During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is

provided to the output driver. Followed by an amplitude denoted by set_residual_carrier

bits with the duration of overshoot_t2.

7.0

(V)

5.0

3.0

1.0

-1.0

2.50

3.03

3.56

4.10

time (ꢀs)

001aan356

Fig 26.

Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d.

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7.0

5.0

3.0

1.0

(V)

-1.0

time (ꢀs)

001aan357

Fig 27.

Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d

8.6.2.2 Bit

generator

The default coding of a data stream is done by using the Bit-Generator. It is activated

when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator

encodes the data stream byte-wise and can apply the following encoding steps to each

data byte.

1. Add

a start-bit of specified type at beginning of every byte

2. Add

a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6,

only full bits are supported

3. Add

a parity-bit of a specified type

4. TxFirstBits

(skips a given number of bits at the beginning of the first byte in a frame)

5. TxLastBits

(skips a given number of bits at the end of the last byte in a frame)

6. Encrypt

data-bit (MIFARE encryption)

TxFirstBits and TxLastBits can be used at the same time. If only a single data byte is sent,

it must be ensured that the range of TxFirstBits and TxLastBits do not overlap. It is not

possible to skip more than 8 bit of a single byte! ( (8 – TxFirstBits) + (8 – TxLastBits) ) < 8

By default, data bytes are always treated LSB first.

ake use of a MSB first coding, the

TxMSBFirst in the register CLCON1 needs to be set.

8.6.3 Receiver

circuitry

8.6.3.1 General

The OM9663 features a versatile quadrature receiver architecture with fully differential

signal input at RXP and RXN. It can be configured to achieve optimum performance for

reception of various 13.56 MHz based protocols.

For all processing units various adjustments can be made to obtain optimum

performance.

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8.6.3.2 Block

diagram

Figure 28

shows the block diagram of the receiver circuitry. The receiving process

includes several steps. First the quadrature demodulation of the carrier signal of

13.56 MHz is done. Several tuning steps in this circuit are possible.

fully/quasi-differential

rcv_hpcf<1:0>

rcv_gain<1:0>

rx_p

rx_n

mix_out_i_p

out_i_p

out_i_n

mixer

DATA

mix_out_i_n

2-stage BBA

clk_27 MHz

2-stage BBA

I-clks

rx_p

rx_n

13.56 MHz

I/O CLOCK

GENERATION

TIMING

GENERATION

ADC

clk_27 MHz

Adc_data_ready

DATA

Q-clks

rx_p

rx_n

mix_out_q_p

mix_out_q_n

out_q_p

out_q_n

mixer

rcv_gain<1:0>

rcv_hpcf<1:0>

fully/quasi-differential

001aan358

Fig 28.

Block diagram of receiver circuitry

The receiver can also be operated in a single ended mode. In this case the

Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP and

RXN need to be connected together and will provide a single ended signal to the receiver

circuitry.

When using the receiver in a single ended mode the receiver sensitivity is decreased and

the achievable reading distance might be reduced, compared to the fully differential mode.

Table 29.

Configuration for single or differential receiver

Mode

rcv_rx_single

pins RXP and RXN

Fully differential

provide differential signal from

differential antenna by separate

rx-coupling branches

Quasi differential

connect RXP and RXN together

and provide single ended signal

from antenna by a single

rx-coupling branch

The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase

shift of 90



between them. Both resulting baseband signals are amplified, filtered, digitized

and forwarded to a correlation circuitry.

The typical application is intended to implement the Fully differential mode and will deliver

maximum reader/writer distance. The Quasi differential mode can be used together with

dedicated antenna topologies that allow a reduction of matching components at the cost

of overall reading performance.

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During low power card detection the DC levels at the I- and Q-channel mixer outputs are

evaluated. This requires that mixers are directly connected to the ADC. This can be

configured by setting the bit Rx_ADCmode in register Rcv (38h).

8.6.4 Active

antenna concept

Two main blocks are implemented in the OM9663. A digital circuitry, comprising state

machines, coder and decoder logic and an analog circuitry with the modulator and

antenna drivers, receiver and amplification circuitry. For example, the interface between

these two blocks can be configured in the way, that the interfacing signals may be routed

to the pins SIGIN and SIGOU

he most important use of this topology is the active

antenna concept where the digital and the analog blocks are separated. This opens the

possibility to connect e.g. an additional digital block of another OM9663 device with a

single analog antenna front-end.

SIGIN

SIGOUT

SIGIN

READER IC

(DIGITAL)

READER IC

(ANTENNA)

SIGOUT

001aam307

Fig 29.

Block diagram of the active Antenna concept

The

ble 30

and

ble 31

describe the necessary register configuration for the use case

active antenna concept.

Table 30.

Value (binary)

Description

SigOut.SigOutSel

Rcv.SigInSel

0100

TxEnvelope

Receive over SigIn (ISO/IEC14443A)

Receive over SigIn (Generic Code)

DrvCon.TxSel

Low (idle)

Table 31.

Value (binary)

Description

SigOut.SigOutSel

0110

0111

Generic Code (Manchester)

Manchester with Subcarrier (ISO/IEC14443A)

Rcv.SigInSel

Internal

DrvCon.TxSel

RxCtrl.RxMultiple

External (SigIn)

RxMultiple on

The interface between these two blocks can be configured in the way, that the interfacing

signals may be routed to the pins SIGIN and SIGOUT (see

Figure 30 “Overview

SIGIN/SIGOUT Signal Routing”

This topology supports, that some parts of the analog part of the OM9663 may be

connected to the digital part of another device.

The switch SigOutSel in registerSigOut can be used to measure signals. This is especially

important during the design In phase or for test purposes to check the transmitted and

received data.

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However, the most important use of SIGIN/SIGOUT pins is the active antenna concept.

An external active antenna circuit can be connected to the digital circuit of the OM9663.

SigOutSel has to be configured in that way that the signal of the internal Miller Coder is

sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive Manchester

signal with sub-carrier from SIGIN pin (SigInSel = 1).

It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate

filter and matching circuit) and at the same time an active antenna to the pins SIGOUT

and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a

single host processor.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

SIGOUT

tri-state 0,

No_nodulation

TX envelope

SIGIN

TX2

TX1

TX bit stream

MODULATOR

DRIVER

CODER

LOW

HIGH

TX envelope

TX active

S3C signal

RX envelope

RX active

SIGOUTSel[4:0]

TxCon.TxSel

[1:0]

RFU

DIGITAL MODULE

RX bit stream

ANALOG MODULE

RX bit signal

SUBCARRIER

DEMODULATOR

tri-state

internal analog block

SIGIN over envelope

SIGIN generic

DECODER

RXN

RXP

DEMODULATOR

Sigpro_in_sel

[1:0]

SIGIN

001aam001

Fig 30.

Overview SIGIN/SIGOUT Signal Routing

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8.6.5 Symbol

generator

The symbol generator is used to create various protocol symbols. These can be e.g. SOF

or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol

symbols like the CS symbol as used by the ICODE EPC protocol.

Symbols are defined by means of the symbol definition registers and the mode registers.

Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a

maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either logic

“0” or logic “1”. The Symbol2 and Symbol3 are limited to 8 bit pattern length and do not

support a burst.

The definition of symbol patterns is done by writing the bit sequence of the pattern to the

appropriate register. The last bit of the pattern to be sent is located at the LSB of the

TxSym32Len) the definition of the symbol pattern is completed. All other bits at

bit-position higher than the symbol length in the definition register are ignored. (Example:

length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern, bit5

is sent first)

Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0,

Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3

can be sent after data packets. Each symbol is defined by a set of registers. Symbols are

configured by a pair of registers. Symbol0 and Symbol1 share the same configuration and

Symbol2 and Symbol3 share the same configuration. The configuration includes setting of

bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the

envelope type.

8.7 Memory

8.7.1 Memory

overview

The OM9663 implements three different memories: EEPROM, FIFO and Registers.

At startup, the initialization of the registers which define the behavior of the IC is

performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and

section2, register reset) into the registers. The behavior of the OM9663 can be changed

by executing the command LoadProtocol, which copies a selected default protocol from

the EEPROM (read only EEPROM section4, register Set Protocol area) into the registers.

The read/write EEPROM section2 can be used to store any user data or predefined

“LoadRegister” into the internal registers.

The FIFO is used as Input/Out buffer and is able to improve the performance of a system

with limited interface speed.

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8.7.2 EEPROM

memory organization

The OM9663 has implemented a EEPROM non-volatile memory with a size of 8 kB.The

EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be programmed at

a time. Defined purposes had been assigned to specific memory areas of the EEPROM,

which are called Sections. Five sections 0..4 with different purpose do exist.

Table 32.

EEPROM memory organization

Section

Page

Byte

addresses

Access

rights

Memory content

00 to 31

product information and configuration

32 to 63

r/w

product configuration

1 to 2

64 to 191

3 to 95

192 to 6143

6144 to 7167

7168 to 8191

free

96 to 111

112 to 128

MIFARE key

The following figure show the structure of the EEPROM:

Section 0:

Section 1:

Production and config

Section 2:

Free

Section 3:

MIFARE key area (MKA)

RSP-Area for TX

Section 4_TX:

Section 4_RX:

RSP-Area for RX

001aan359

Fig 31.

Sector arrangement of the EEPROM

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8.7.2.1 Product

information and configuration – Page 0

The first EEPROM page includes production data as well as configuration information.

Table 33.

Production area (Page 0)

Address

(Hex.)

ProductID

Version

Unique Identifier

Manufacturer

Data

ManufacturerData

ProductID

Identifier for this OM9663 product, only address 01h shall be evaluated for

identifying the Product OM9663, address 00h and 02h shall be ignored by software.

Table 34.

Product ID overview of OM9663 family

Address 01h

OM9663

Product ID

01h

MFRC631

MFRC630

SLRC610

C0h

80h

20h

Version

: This register indicates the version of the EEPROM initialization data during

production. (Identification of the Hardware version is available in the register 7Fh, not in

the EEPROM Version address. The hardware information in register 7Fh is hardwired and

therefore independent from any EEPROM configuration.)

Unique identifier:

Unique identifier for this device

Manufacturer Data:

This data is programmed during production. The content is not

intended to be used by any application and might be not the same for different devices.

Therefore this content needs to be considered to be undefined.

Table 35.

Configuration area (Page 0)

Address

(Hex.)

C_Address

Interface I

C SAM_Address

DefaultProtRx DefaultProtTx

–

TxCRCPreset

RxCRCPreset

–

C-Address:

Two possibilities exist to define the address of the I

C interface. This can be

done either by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the

interface pins IF0, IF2) or by writing value into the I

C address area. The selection, which

of this 2-information pin configuration or EEPROM content – is used as I

C-address is

done at EEPROM address 21h (Interface, bit4)

Interface:

This section describes the interface byte configuration.

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Table 36.

Interface byte

Bit

C_HSP

–

I2C_Address

r/w

Boundary Scan

r/w

Host

access rights

r/w

RFU

r/w

Table 37.

Interface bits

Bit

Symbol

C_HSP

Description

when cleared, the high speed mode is used

when set, the high speed+ mode is used (default)

6, 5

RFU

C_Address

–

when cleared, the pins are used (default)

when set, the EEPROM is used

Boundary

Scan

when cleared, the boundary scan interface is ON (default)

when set, the boundary scan is OFF

2 to 0

Host

000b – RS232

001b – I

010b – SPI

011b – I

1xxb – pin selection

C_SAM_Address:

The I

C SAM Address is always defined by the EEPROM content.

The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes)

and for the RX registers (8 bytes).

Table 38.

Tx and Rx arrangements in the register set protocol area

Section

Section 4 TX

Section 4 Rx

Tx0

Tx4

RX0

RX8

Tx1

TX2

Tx3

Tx5

TX6

TX7

RX6

RX14

RX1

RX9

RX2

RX10

RX3

RX4

RX12

RX5

RX7

RX11

RX13

RX15

TxCrcPreset:

The data bits are send by the analog module and are automatically

extended by a CRC.

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8.7.3 EEPROM

initialization content LoadProtocol

The OM9663 EEPROM is initialized at production with values which are used to reset

certain registers of the OM9663

to default settings

by copying the EEprom content to the

registers. Only registers or bits with “read/write” or “dynamic” access rights are initialized

with this default values copied from the EEProm.

Note that the addresses used for copying reset values from EEprom to registers are

dependent on the configured protocol and can be changed by the user.

Table 39.

Address 0

(8)

1 (9)

2 (A)

3 (B)

Version

4 (C)

5 (D)

6 (E)

7 (F)

Function

Product ID

Unique Serial Number

see table 34

Function

Unique Serial Number

Factory trim

value

Function TrimLFO

10 XX

Factory trim values

Function Factory

trim values

18….

Factory trim values

XX XX

….38

The register reset values are configuration parameters used after startup of the IC. They

can be changed to modify the default behavior of the device. In addition to this register

reset values, is the possibility to load settings for various user implemented protocols.The

load protocol command is used for this purpose.

Table 40.

Address 0

(8)

Command

1 (9)

HostCtrl

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

IRQ0

7 (F)

IRQ1

FiFoControl WaterLevel

FiFoLength FiFoData

IRQ0En

IRQ1En

Error

Status

RxBitCtrl

RxColl

TControl

T0Control

T0ReloadHi T0ReloadLo

T0Counter

ValHi

T0Counter

ValLo

T1Control

T1ReloadHi T1ReloadLo

T1Counter

ValHi

T1Counter

ValLo

T2Control

T2ReloadHi T2ReloadLo

T2Counter

ValHi

T2Counter

ValLo

T3Control

T3ReloadHi

T3ReloadLo T3Counter

ValHi

T3Counter

ValHi

T4Control

T4ReloadHi T4ReloadLo

T4Counter

ValHi

T4Counter

ValLo

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Table 40.

…continued

Address 0

(8)

DrvMode

1 (9)

2 (A)

3 (B)

4 (C)

5 (D)

6 (E)

7 (F)

TxAmp

DrvCon

Txl

TxCRC

Preset

RxCRC

Preset

TxDataNum TxModWith

TxSym10

BurstLen

TxWaitCtrl

TxWaitLo

FrameCon

RxSofD

RxCtrl

RxWait

RxThres

hold

Rcv

RxAna

RFU

SerialSpeed LFO_trimm

PLL_Ctrl

PLL_Div

LPCD_QMi

LPCD_

QMax

LPCD_IMin LPCD

_result_I

LPCD

_result_Q

PadEn

PadOut

PadIn

SigOut

TxBitMod

RFU

TxDataCon TxDataMod TxSymFreq TxSym0H

04 50 40 00

TySym0L

TxSym1H

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8.8 Clock

generation

8.8.1 Crystal

oscillator

The clock applied to the OM9663 acts as time basis for generation of the carrier sent out

at TX and for the quadrature mixer I and Q clock generation as well as for the coder and

decoder of the synchronous system. Therefore stability of the clock frequency is an

important factor for proper performance.

btain highest performance, clock jitter has to

be as small as possible. This is best achieved by using the internal oscillator buffer with

the recommended circuitry.

READER IC

XTAL1 XTAL2

27.12 MHz

001aam308

Fig 32.

Quartz connection

Table 41.

Crystal requirements recommendations

Symbol

xtal

Parameter

Conditions

Min

–

Typ

27.12

–

max

–

Unit

MHz

ppm

crystal frequency



xtal

relative crystal



250

+250

frequency variation

ESR

equivalent series

resistance

–

100



load capacitance

–

xtal

crystal power

dissipation

100



8.8.2 IntegerN

PLL clock line

The OM9663 is able to provide a clock with configurable frequency at CLKOUT from

1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a

microcontroller which avoids the need of a second crystal oscillator in the reader system.

Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator.

Two dividers are determining the output frequency. First a feedback integer-N divider

configures the VCO frequency to be N



fin/2 (control signal pll_set_divfb). As supported

Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be



fin / 2 (312 MHz), 27



fin / 2 (366 MHz) and 28



fin / 2 (380 MHz).

The VCO frequency is divided by a factor which is defined by the output divider

(pll_set_divout).

ble 42 “Divider values for selected frequencies using the integerN PLL”

shows the accuracy achieved for various frequencies (integer multiples of 1 MHz and

some typical RS232 frequencies) and the divider ratios to be used. The register bit

ClkOutEn enables the clock at CLKOUT pin.

The following formula can be used to calculate the output frequency:

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out

= 13.56 MHz



PLLDiv_FB /PLLDiv_Out

Table 42.

Divider values for selected frequencies using the integerN PLL

Frequency [MHz]

PLLDiv_FB

1.8432 3.6864

PLLDiv_Out

206

103

0.01

accuracy [%]

0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01

8.8.3 Low

Frequency Oscillator (LFO)

The Low-Frequency (LFO) is implemented to drive a wake-up counter (WUC). This wakes

up the system in regular time intervals and eases the design of a reader that is regularly

polling for card presence or implements a low-power card detection.

The LFO is trimmed during production to run at 16 Khz. Unless a high accuracy of the

LFO is required by the application and the device is operated in an environment with

changing ambient temperatures, trimming of the LFO is not required. For a typical

application making use of the LFO for wake up from power down, the trim value set during

production can be used. Optional trimming to achieve a higher accuracy of the 16 Khz

LFO clock is supported by a digital state machine which compares LFO-clock to a

reference clock. As reference clockfrequency the 13.56 MHz crystal clock is available.

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8.9 Power

management

8.9.1 Supply

concept

The OM9663 is supplied by V

(Supply Voltage), PVDD (Pad Supply) and TVDD

(Transmitter Power Supply). These three voltages are independent from each other.

onnect the OM9663 to a Microcontroller supplied by 3.3 V, PVDD and V

shall be at

a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at

TVDD will result in a higher field strength.

Independent of the voltage it is recommended to buffer these supplies with blocking

capacitances close to the terminals of the package. V

and PVDD are recommended to

be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2

capacitors, 100 nF parallel to 1.0



AVDD and DVDD are not supply input pins. They are output pins and shall be connected

to blocking capacitors 470 nF each.

8.9.2 Power

reduction mode

8.9.2.1 Power-down

A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal

1.8 V voltage regulators for the analog and digital core supply as well as the oscillator. All

digital input buffers are separated from the input pads and clamped internally (except pin

PDOWN itself). The output pins are switched to high impedance.

eave the power-down mode the level at the pin PDOWN as to be set to LOW. This will

start the internal start-up sequence.

8.9.2.2 Standby

mode

The standby mode is entered immediately after setting the bit PowerDown in the register

Command. All internal current sinks are switched off except the LFO. Voltage references

and voltage regulators will be set into stand-by mode.

In opposition to the power-down mode, the digital input buffers are not separated by the

input pads and keep their functionality. The digital output pins do not change their state.

During standby mode, all registers values, the FIFO’s content and the configuration itself

will keep its current content.

eave the standby mode the bit PowerDown in the register Command is cleared. This

will trigger the internal start-up sequence. The reader IC is in full operation mode again

when the internal start-up sequence is finalized (the typical duration is 15 us).

Alternatively, a value of 55h can be sent to the OM9663 using the RS232 interface to

leave the standby mode. Then read accesses shall be performed at address 00h until the

device returns the content of this address. The return of the content of address 00h

indicates that the device is ready to receive further commands and the internal start-up

sequence is finalized.

8.9.2.3 Modem

off mode

When the ModemOff bit in the register Control is set the antenna transmitter and the

receiver are switched off.

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eave the modem off mode clears the ModemOff bit in the register Control.

8.9.3 Low-Power

Card Detection (LPCD)

The low-power card detection is an energy saving mode when the OM9663 is not fully

powered permanently.

The LPCD works in two phases. First the standby phase is controlled by the wake-up

counter (WUC), which defines the duration of the standby of the OM9663. Second phase

is the detection-phase. In this phase the values of the I and Q channel are detected and

stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time period can be

handled with Timer3. The value is compared with the min/max values in the registers

(LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the limits, a LPCDIrq

is raised.

After the command LPCD the standby of the OM9663 is activated, if selected. The

wake-up Timer4 can activate the system after a given time. For the LPCD it is

recommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go to

standby. If a card is detected the timer stops and the communication can be started. If

T4AutoWakeUp is not set, the IC will not enter Standby mode in case no card is detected.

8.9.4 Reset

and start-up time

A 10



s constant high level at the PDOWN pin starts the internal reset procedure.

The following figure shows the internal voltage regulator:

PVDD

AVDD

DVDD

1.8 V

GLITCH

FILTER

INTERNAL VOLTAGE

REGULATOR

PDown

1.8 V

001aan360

Fig 33.

Internal PDown to voltage regulator logic

When the OM9663 has finished the reset phase and the oscillator has entered a stable

working condition the IC is ready to be used.

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8.10 Command

set

8.10.1 General

The behavior is determined by a state machine capable to perform a certain set of

commands. By writing the according command-code to register Command the command

is executed.

Arguments and/or data necessary to process a command, are exchanged via the FIFO

buffer.

•

A data transmission of the TxEncoder can be started by a command. When started,

the communication is executed as defined in the TxFrameCon register. Therefore a

communication frame can consist of a start-symbol, a data-stream, and followed by

an end-symbol.

•

Each command that needs a certain number of arguments will start processing only

when it has received the correct number of arguments via the FIFO buffer.

•

The FIFO buffer is not cleared automatically at command start. Therefore, it is

recommended to write the command arguments and/or the data bytes into the FIFO

buffer and start the command afterwards.

•

Each command may be interrupted by the host by writing a new command code into

8.10.2 Command

set overview

Table 43.

Command set

Command

Idle

No.

00h

01h

02h

Parameter (bytes)

Short description

–

no action, cancels current command execution

low-power card detection

LPCD

LoadKey

(keybyte1),(keybyte2), (keybyte3),

(keybyte4), (keybyte5),(keybyte6);

reads a MIFARE key (size of 6 bytes) from FIFO buffer

ant puts it into Key buffer

MFAuthent

AckReq

03h

60h or 61h, (block address), (card

serial number byte0),(card serial

number byte1), (card serial number

byte2),(card serial number byte3);

performs the MIFARE standard authentication in

MIFARE read/write mode only

04h

–

performs a query, an Ack and a Req-Rn for ISO/IEC

18000-3 mode 3/ EPC Class-1 HF

Receive

05h

06h

07h

–

activates the receive circuit

Transmit

Transceive

transmits data from the FIFO buffer

transmits data from the FIFO buffer and automatically

activates the receiver after transmission finished

WriteE2

08h

09h

0Ah

addressL, addressH, data;

gets one byte from FIFO buffer and writes it to the

internal EEPROM, valid address range are the

addresses of the MIFARE Key area

WriteE2Page

ReadE2

(page Address), data0, [data1

..data63];

gets up to 64 bytes (one EEPROM page) from the FIFO

buffer and writes it to the EEPROM, valid page address

range are the pages of the MIFARE Key Area

addressL, address H, length;

reads data from the EEPROM and copies it into the

FIFO buffer, valid address range are the addresses of

the MIFARE Key area

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Table 43.

Command set

…continued

Command

No.

Parameter (bytes)

Short description

LoadReg

0Ch

(EEPROM addressL), (EEPROM

addressH), RegAdr, (number of

reads data from the internal EEPROM and initializes the

OM9663 registers. EEPROM address needs to be

within EEPROM sector 2

LoadProtocol

0Dh

(Protocol umber RX), (Protocol number

reads data from the internal EEPROM and initializes the

TX);

OM9663 registers needed for a Protocol change

copies a key of the EEPROM into the key buffer

stores a MIFARE key (size of 6 bytes) into the EEPROM

LoadKeyE2

StoreKeyE2

0Eh

0Fh

KeyNr;

KeyNr, byte1,byte2, byte3, byte4,

byte5,byte6;

ReadRNR

Soft Reset

1Ch

1Fh

–

Copies bytes from the Random Number generator into

the FIFO until the FiFo is full

–

resets the OM9663

8.10.3 Command

functionality

8.10.3.1 Idle

command

Command (00h);

This command indicates that the OM9663 is in idle mode. This command is also used to

terminate the actual command.

8.10.3.2 LPCD

command

Command (01h);

This command performs a low-power card detection and or an automatic trimming of the

LFO. The values of the sampled I and Q channel are stored in the register map. The value

is compared with the min/max values in the register. If it exceeds the limits, an LPCD_Irq

will be raised. After the command the standby is activated if selected.

8.10.3.3 Load

key command

Command (02h), Parameter1 (key byte1),…, Parameter6 (key byte6);

Loads a MIFARE Key (6 bytes) for Authentication from the FIFO into the crypto unit.

Abort condition: Less than 6 bytes written to the FIFO.

8.10.3.4 MFAuthent

command

Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2

(block address), Parameter3 (card serial number byte0), Parameter4 (card serial number

byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3);

This command handles the MIFARE authentication in Reader/Writer mode to enable a

secure communication to any MIFARE classic card.

When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is

an access to the FIFO, the bit WrErr in the Error register is set.

This command terminates automatically when the MIFARE card is authenticated and the

bit MFCrypto1On is set to logic 1.

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This command does not terminate automatically, when the card does not answer,

therefore the timer should be initialized to automatic mode. In this case, beside the bit

IdleIRq the bit TimerIRq can be used as termination criteria. During authentication

processing the bits RxIRq and TxIRq are blocked. The Crypto1On shows if the

authentication was successful.

The following data shall be written to the FIFO before the command can be activated:

•

Authentication command code (60h, 61h)

•

Block address

•

Card serial number byte 0

•

Card serial number byte 1

•

Card serial number byte 2

•

Card serial number byte 3

In total, 6 bytes are written to the FIFO.

Remark:

When the MFAuthent command is active, any FIFO access is blocked. If there is

an attempt to access to the FIFO during MFAuthent being active, the bit WrErr in the Error

This MFAuthent command terminates automatically when the MIFARE card is

authenticated and the bit MFCrypto1On in the Status register is set to logic 1.

This MFAuthent command does not terminate automatically when the card does not

answer, therefore the timer should be initialized to automatic mode. In this case, beside

the bit IdleIrq, the bit TimerIrq can be used as termination criteria. During authentication

processing the bit RxIrq and bit TxIrq are blocked. The Crypto1On bit is only valid after

termination of the authentication command (either after processing the protocol or after

writing IDLE to the command register).

In case there is an error during authentication, the bit ProtocolErr in the Error register is

set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0.

8.10.3.5 AckReq

command

Command (04h);

Performs a Query (Full command must be written into the FIFO); a Ack and a ReqRn

command. All answers to the command will be written into the FIFO. The error flag is

copied after the answer into the FIFO.

This command terminates automatically when finished and the active command is idle.

8.10.3.6 Receive

command

Command (05h);

The OM9663 activates the receiver path, waits for any data stream to be received,

according to its register settings, which shall be set before starting this command

according the used protocol and antenna configuration. The correct settings have to be

chosen before starting this command.

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This command terminates automatically when the received data stream ends. This is

indicated either by the end of frame pattern or by the length byte depending on the

selected framing and speed.

Remark:

If the bit RxMultiple in the RxModeReg register is set to logic 1, the Receive

command does not terminate automatically. It has to be terminated by activating any other

command in the CommandReg register (see

Section 9.17.6 “RxMod”

8.10.3.7 Transmit

command

Command (06h);

The content of the FIFO is transmitted immediately after starting the command. Before

transmitting the FIFO content all relevant register have to be set to transmit data.

This command terminates automatically when the FIFO gets empty. It can be terminated

by any other command written to the command register.

8.10.3.8 Transceive

command

Command (07h);

This command transmits data from the FIFO and receives data from the RF field at once.

The first action is transmitting and after a transmission the command is changed to

receive a data stream.

Each transmission process starts by writing the command into CommandReg.

Remark:

If the bit RxMultiple in register RxModeReg is set to logic 1, this command will

never leave the receiving state, because the receiving will not be cancelled automatically.

8.10.3.9 WriteE2

command

Command (08h), Parameter1 (addressL), Parameter2 (addressH), Parameter3 (data);

This command writes one byte into the EEPROM. If the FIFO contains no data, the

command will wait until the data is available.

Abort condition: insufficient parameter in FIFO; Address-parameter outside of range.

8.10.3.10 WriteE2PAGE

command

Command (09h), Parameter1 (page address), Parameter2 (data0), Parameter3…65

[data1 ..data63];

This command writes up to 64 bytes into the EEPROM.

Abort condition: Insufficient parameters in FIFO; Page address parameter outside of

range.

8.10.3.11 ReadE2

command

Command (0Ah), Parameter1 (addressL), Parameter2 (addressH), Parameter3 (length);

Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the

address 1FFFh, the read operation continues from address 0000h.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

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8.10.3.12 LoadReg

command

Command (0Ch), Parameter1 (EEPROM addressL),Parameter2 (EEPROM addressH),

Parameter3 (RegAdr), Parameter4 (number);

Read a defined number of bytes from the EEPROM and copies the value into the Register

set, beginning at the given address RegAdr.

Abort condition: Insufficient parameter in FIFO; Address parameter outside of range.

8.10.3.13 LoadProtocol

command

Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX);

Reads out the EEPROM Register Set Protocol Area and overwrites the content of the Rx-

and Tx- related registers. These registers are important for a Protocol selection.

Abort condition: Insufficient parameter in FIFO

Table 44.

Predefined protocol overview RX

[1]

Protocol

Number

(decimal)

Protocol

Receiver speed

[kbits/s]

Receiver Coding

ISO/IEC14443 A

ISO/IEC14443 B

FeliCa

106

212

424

848

106

212

424

848

212

424

Manchester SubC

BPSK

Manchester

SSC

FeliCa

ISO/IEC15693

EPC/UID

SSC

DSC

SSC

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

2/424

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

4/424

2/848

4/848

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

[1] For

more protocol details please refer to

Section 8 “Functional description”

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Table 45.

Predefined protocol overview TX

[1]

Protocol

Number

Protocol

Transmitter speed

Transmitter Coding

[kbits/s]

(decimal)

ISO/IEC14443 A

ISO/IEC14443 B

FeliCa

106

212

424

848

106

212

424

848

212

424

Miller

NRZ

Manchester

1/4

FeliCa

ISO/IEC15693

EPC/UID

1/4

1,66

1/256

Unitray

ri, ASK, PIE

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

ri, ASK, PIE

RFU

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

ISO/IEC 18000-3 mode 3/

EPC Class-1 HF

[1] For

more protocol details please refer to

Section 8 “Functional description”

8.10.3.14 LoadKeyE2

command

Command (0Eh), Parameter1 (key number);

Loads a MIFARE key for authentication from the EEPROM into the crypto 1 unit.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA.

8.10.3.15 StoreKeyE2

command

Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2),

Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7

(keybyte6);

Stores MIFARE Keys into the EEPROM. The key number parameter indicates the first key

(n) in the MKA that will be written. If more than one MIFARE Key is available in the FIFO

then the next key (n+1) will be written until the FIFO is empty. If an incomplete key (less

than 6 bytes) is written into the FIFO, this key will be ignored and will remain in the FIFO.

Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA;

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8.10.3.16 GetRNR

command

Command (1Ch);

This command is reading Random Numbers from the random number generator of the

OM9663. The Random Numbers are copied to the FIFO until the FIFO is full.

8.10.3.17 SoftReset

command

Command (1Fh);

This command is performing a soft reset. Triggered by this command all the default values

for the register setting will be read from the EEPROM and copied into the register set.

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9. OM9663

registers

9.1 Register

bit behavior

Depending on the functionality of a register, the access conditions to the register can vary.

In principle, bits with same behavior are grouped in common registers. The access

conditions are described in

ble 46

Table 46.

Behavior of register bits and their designation

Abbreviation Behavior

Description

r/w

read and write

These bits can be written and read via the host interface. Since

they are used only for control purposes, the content is not

influenced by the state machines but can be read by internal state

machines.

dynamic

These bits can be written and read via the host interface. They

can also be written automatically by internal state machines, for

example Command register changes its value automatically after

the execution of the command.

read only

These register bits indicates hold values which are determined by

internal states only.

write only

–

Reading these register bits always returns zero.

RFU

These bits are reserved for future use and must not be changed.

In case of a required write access, it is recommended to write a

logic 0.

Table 47.

OM9663 registers overview

Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

Command

HostCtrl

Function

Starts and stops command execution

Host control register

FIFOControl

WaterLevel

FIFOLength

FIFOData

IRQ0

Control register of the FIFO

Level of the FIFO underflow and overflow warning

Length of the FIFO

Data In/Out exchange register of FIFO buffer

Interrupt register 0

IRQ1

Interrupt register 1

IRQ0En

Interrupt enable register 0

IRQ1En

Interrupt enable register 1

Error

Error bits showing the error status of the last command execution

Contains status of the communication

Control register for anticollision adjustments for bit oriented protocols

Collision position register

Status

RxBitCtrl

RxColl

TControl

Control of Timer 0..3

T0Control

T0ReloadHi

T0ReloadLo

T0CounterValHi

T0CounterValLo

Control of Timer0

High register of the reload value of Timer0

Low register of the reload value of Timer0

Counter value high register of Timer0

Counter value low register of Timer0

12h

13h

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Table 47.

OM9663 registers overview

…continued

Address

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

T1Control

Function

Control of Timer1

T1ReloadHi

T1ReloadLo

T1CounterValHi

T1CounterValLo

T2Control

High register of the reload value of Timer1

Low register of the reload value of Timer1

Counter value high register of Timer1

Counter value low register of Timer1

Control of Timer2

T2ReloadHi

T2ReloadLo

T2CounterValHi

T2CounterValLo

T3Control

High byte of the reload value of Timer2

Low byte of the reload value of Timer2

Counter value high byte of Timer2

Counter value low byte of Timer2

Control of Timer3

T3ReloadHi

T3ReloadLo

T3CounterValHi

T3CounterValLo

T4Control

High byte of the reload value of Timer3

Low byte of the reload value of Timer3

Counter value high byte of Timer3

Counter value low byte of Timer3

Control of Timer4

T4ReloadHi

T4ReloadLo

T4CounterValHi

T4CounterValLo

DrvMod

High byte of the reload value of Timer4

Low byte of the reload value of Timer4

Counter value high byte of Timer4

Counter value low byte of Timer4

Driver mode register

TxAmp

Transmitter amplifier register

Driver configuration register

DrvCon

Txl

Transmitter register

TxCrcPreset

RxCrcPreset

TxDataNum

TxModWidth

TxSym10BurstLen

TXWaitCtrl

TxWaitLo

Transmitter CRC control register, preset value

Receiver CRC control register, preset value

Transmitter data number register

Transmitter modulation width register

Transmitter symbol 1 + symbol 0 burst length register

Transmitter wait control

Transmitter wait low

FrameCon

RxSofD

Transmitter frame control

Receiver start of frame detection

Receiver control register

RxCtrl

RxWait

Receiver wait register

RxThreshold

Rcv

Receiver threshold register

Receiver register

RxAna

Receiver analog register

RFU

–

SerialSpeed

LFO_Trimm

Serial speed register

Low-power oscillator trimming register

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Table 47.

OM9663 registers overview

…continued

Address

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

7Fh

PLL_Ctrl

Function

IntegerN PLL control register, for microcontroller clock output adjustment

Low-power card detection Q channel minimum threshold

Low-power card detection Q channel maximum threshold

Low-power card detection I channel minimum threshold

Low-power card detection I channel result register

Low-power card detection Q channel result register

PIN enable register

PLL_DivOut

LPCD_QMin

LPCD_QMax

LPCD_IMin

LPCD_I_Result

LPCD_Q_Result

PadEn

PadOut

PIN out register

PadIn

PIN in register

SigOut

Enables and controls the SIGOUT Pin

Transmitter bit mode register

TxBitMod

RFU

–

TxDataCon

TxDataMod

TxSymFreq

TxSym0H

TxSym0L

Transmitter data configuration register

Transmitter data modulation register

Transmitter symbol frequency

Transmitter symbol 0 high register

Transmitter symbol 0 low register

TxSym1H

TxSym1L

Transmitter symbol 1 high register

Transmitter symbol 1 low register

TxSym2

Transmitter symbol 2 register

TxSym3

Transmitter symbol 3 register

TxSym10Len

TxSym32Len

TxSym10BurstCtrl

TxSym10Mod

TxSym32Mod

RxBitMod

RxEofSym

RxSyncValH

RxSyncValL

RxSyncMod

RxMod

Transmitter symbol 1 + symbol 0 length register

Transmitter symbol 3 + symbol 2 length register

Transmitter symbol 1 + symbol 0 burst control register

Transmitter symbol 1 + symbol 0 modulation register

Transmitter symbol 3 + symbol 2 modulation register

Receiver bit modulation register

Receiver end of frame symbol register

Receiver synchronisation value high register

Receiver synchronisation value low register

Receiver synchronisation mode register

Receiver modulation register

RxCorr

Receiver correlation register

FabCal

Calibration register of the receiver, calibration performed at production

Version and subversion register

Version

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9.2 Command

configuration

9.2.1 Command

Starts and stops command execution.

Table 48.

Command register (address 00h)

Bit

Symbol Standby

Modem

Off

RFU

Command

Access

rights

r/w

–

Table 49.

Command bits

Bit

Symbol

Standby

ModemOff

RFU

Description

Set to 1, the IC is entering power-down mode.

Set to logic 1, the receiver and the transmitter circuit is powering down.

–

4 to 0

Command

Defines the actual command for the OM9663.

9.3 SAM

configuration register

9.3.1 HostCtrl

Via the HostCtrl Register the interface access right can be controlled

Table 50.

HostCtrl register (address 01h);

Bit

RegEn

RFU

–

SAMInterface

r/w

SAMInterface

r/w

RFU

–

RFU

–

Symbol

BusHost

r/w

BusSAM

r/w

Access

rights

Table 51.

HostCtrl bits

Bit

Symbol

Description

RegEn

If this bit is set to logic 1, the register can be changed at the next

BusHost

BusSAM

RFU

Set to logic 1, the bus control enables the host interface. This bit

cannot be set together with BusSAM. This bit can only be set if the bit

RegEn is previously set.

Set to logic 1, the bus control enables the SAM interface. This bit

cannot be set together with BusHost. This bit can only be set if the bit

RegEn is previously set.

–

3 to 2

SAMInterface 0h:Interface

switched off

1h:Interface SPI active

2h:Interface I

CL active

3h:Interface I

1 to 0

RFU

–

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9.4 FIFO

configuration register

9.4.1 FIFOControl

FIFOControl defines

the characteristics of the FIFO

Table 52.

FIFOControl register (address 02h);

Bit

HiAlert

LoAlert

FIFOFlush

RFU

–

WaterLevel

r/w

Symbol

FIFOSize

r/w

FIFOLength

Access

rights

Table 53.

FIFOControl bits

Bit

Symbol

Description

FIFOSize

Set to logic 1, FIFO size is 255 bytes;

Set to logic 0, FIFO size is 512 bytes.

It is recommended to change the FIFO size only, when the FIFO

content had been cleared.

HiAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following equation:

HiAlert = (FIFOSize – FIFOLength) <= WaterLevel

LoAlert

Set to logic 1, when the number of bytes stored in the FIFO buffer

fulfils the following conditions:

LoAlert =1 if FIFOLength <= WaterLevel

FIFOFlush

Set to logic 1 empties the FIFO buffer. Reading this bit will always

return 0

RFU

–

WaterLevel

Defines the bit 8 (MSB) for the waterlevel (extension of WaterLevel).

This bit is only evaluated in the 512-bit FIFO mode. Bits 7..0 are

defined in WaterLevel.

1 to 0

FIFOLength

Defines the bit9 (MSB) and bit8 for the FIFO length (extension of

FIFOLength). These two bits are only evaluated in the 512-bit FIFO

mode, The bits 7..0 are defined in FIFOLength.

9.4.2 WaterLevel

Defines the level for FIFO under- and overflow warning levels.This register is extended by

1 bit in FIFOControl in case the 512-bit FIFO mode is activated by setting bit

FIFOControl.FIFOSize.

Table 54.

WaterLevel register (address 03h);

Bit

Symbol

WaterLevel

r/w

Access

rights

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Table 55.

WaterLevel bits

Bit

Symbol

Description

7 to 0

WaterLevel

Sets a level to indicate a FIFO-buffer state which can be read from bits

HighAlert and LowAlert in the FifoControl. In 512-bit FIFO mode, the

functionality can be used to avoid a FIFO buffer overflow or underflow:

The bit HiAlert bit in FIFO Control is read logic 1, if the number of bytes

in the FIFO-buffer is equal or less than the number defined by

WaterLevel.

The bit LoAlert bit in FIFO control is read logic 1, if the number of bytes

in the FIFO buffer is equal or less than the number defined by

WaterLevel.

Note: For the calculation of HiAlert and LoAlert see register description

of these bits (

Section 9.4.1 “FIFOControl”

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9.4.3 FIFOLength

Number of bytes in the FIFO buffer. In 512-bit modem this register is extended by

FIFOControl.FifoLength.

Table 56.

FIFOLength register (address 04h); reset value: 00h

Bit

Symbol

FIFOLength

Access

rights

Table 57.

FIFOLength bits

Bit

Symbol

Description

7 to 0

FIFOLength Indicates

the number of bytes in the FIFO buffer. In 512-bit modem this

decrements the number of bytes in the FIFO.

9.4.4 FIFOData

In- and output of FIFO buffer. Contrary to any read/write access to other addresses,

reading or writing to the FIFO address does not increment the address pointer. Resulting

in an efficient data transfer from and to the FIFO buffer. Writing to the FIFOData register

increments, reading decrements the number of bytes present in the FIFO.

Table 58.

FIFOData register (address 05h);

Bit

Symbol

FIFOData

Access

rights

Table 59.

FIFOData bits

Bit

Symbol

Description

7 to 0

FIFOData

Data input and output port for the internal FIFO buffer. Refer to

Section

8.5 “Buffer”

9.5 Interrupt

configuration registers

The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid

the not intended modification of bits.

The mechanism of changing register contents requires the following consideration:

IRQ(x). Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on

the content of IRQ(x).Set, a write of a logical 1 to positions 0 to 6 either clears or sets the

corresponding bit. With this register the application can modify the interrupt status which

is maintained by the OM9663.

Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written

to a bit position 6…0 will trigger the setting or clearance of this bit as defined by bit 7.

Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt

request register

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9.5.1 IRQ0

Interrupt request register 0.

Table 60.

IRQ0 register (address 06h); reset value: 00h

Bit

Symbol

Set

Hi AlertIrq

Lo AlertIrq

IdleIrq

TxIrq

RxIrq

ErrIrq

RxSOF

Irq

Access

rights

dy dy

Table 61.

IRQ0 bits

Bit

Symbol

Description

Set

1: writing a 1 to a bit position 6..0 sets the interrupt request

0: Writing a 1 to a bit position 6..0 clears the interrupt request

HiAlerIrq

Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert,

HiAlertIrq stores this event and can only be reset if Set is cleared.

LoAlertIrq Set,

when bit LoAlert in register Status1 is set. In opposition to LoAlert,

LoAlertIrq stores this event and can only be reset if Set is cleared

IdleIrq

Set, when a command terminates by itself e.g. when the Command changes

its value from any command to the Idle command. If an unknown command

is started, the Command changes its content to the idle state and the bit

IdleIRq is set. Starting the Idle command by the Controller does not set bit

IdleIRq. Can only be reset if Set is cleared.

TxIrq

RxIrq

Set, when data transmission is completed, which is immediately after the last

bit is sent. Can only be reset if Set is cleared.

Set, when the receiver detects the end of a data stream.

Note: This flag is no indication that the received data stream is correct. The

error flags have to be evaluated to get the status of the reception. Can only

be reset if Set is cleared.

ErrIrq

Set, when the one of the following errors is set:

FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr.

Can only be reset if Set is cleared.

RxSOFlrq Set,

when a SOF or a subcarrier is detected. Can only be reset if Set is

cleared.

9.5.2 IRQ1

Interrupt request register 1.

Table 62.

IRQ1 register (address 07h)

Bit

Set

GlobalIrq

Timer3Irq

Timer2Irq

Timer1Irq

Timer0Irq

Symbol

LPCD_Irq Timer4Irq

dy dy

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Table 63.

IRQ1 bits

Bit

Symbol

Description

Set

1: writing a 1 to a bit position 5..0 sets the interrupt request

0: Writing a 1 to a bit position 5..0 clears the interrupt request

Set, if an enabled Irq occurs.

GlobalIrq

LPCD_Irq Set

if a card is detected in Low-power card detection sequence.

Timer4Irq Set

to logic 1 when Timer4 has an underflow.

Timer3Irq Set

to logic 1 when Timer3 has an underflow.

Timer2Irq Set

to logic 1 when Timer2 has an underflow.

Timer1Irq Set

to logic 1 when Timer1 has an underflow.

Timer0Irq Set

to logic 1 when Timer0 has an underflow.

9.5.3 IRQ0En

Interrupt request enable register for IRQ0. This register allows to define if an interrupt

request is processed by the OM9663.

Table 64.

IRQ0En register (address 08h)

Bit

Hi AlertIrqEn

r/w

LoAlertIrqEn

r/w

Symbol

Irq_Inv

r/w

IdleIrqEn

r/w

TxIrqEn

r/w

RxIrqEn

r/w

ErrIrqEn RxSOFIrqEn

r/w r/w

Access

rights

Table 65.

IRQ0En bits

Bit

Symbol

Description

Set to one the signal of the IRQ pin is inverted

Irq_Inv

Hi AlerIrqEn

Set to logic 1, it allows the High Alert interrupt Request (indicated by the

bit HiAlertIrq) to be propagated to the GlobalIrq

Lo AlertIrqEn

Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the

bit LoAlertIrq) to be propagated to the GlobalIrq

IdleIrqEn

TxIRqEn

RxIRqEn

ErrIRqEn

Set to logic 1, it allows the Idle interrupt request (indicated by the bit

IdleIrq) to be propagated to the GlobalIrq

Set to logic 1, it allows the transmitter interrupt request (indicated by the

bit TxtIrq) to be propagated to the GlobalIrq

Set to logic 1, it allows the receiver interrupt request (indicated by the bit

RxIrq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Error interrupt request (indicated by the bit

ErrorIrq) to be propagated to the GlobalIrq

RxSOFIrqEn Set

to logic 1, it allows the RxSOF interrupt request (indicated by the bit

RxSOFIrq) to be propagated to the GlobalIrq

9.5.4 IRQ1En

Interrupt request enable register for IRQ1.

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Table 66.

IRQ1EN register (address 09h);

Bit

Symbol IrqPushPull

IrqPinEn LPCD_IrqEn Timer4IrqEn Timer3IrqEn Timer2IrqE Timer1IrqEn

Timer0IrqEn

Access

rights

r/w

Table 67.

IRQ1EN bits

Bit

Symbol

Description

IrqPushPull

Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as

OpenDrain pin

IrqPinEN

Set to logic 1, it allows the global interrupt request (indicated by the bit

GlobalIrq) to be propagated to the interrupt pin

LPCD_IrqEN

Timer4IRqEn

Timer3IrqEn

Timer2IrqEn

Timer1IrqEn

Timer0IrqEn

Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit

LPCDIrq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit

Timer4Irq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit

Timer3tIrq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit

Timer2Irq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit

Timer1Irq) to be propagated to the GlobalIrq

Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit

Timer0Irq) to be propagated to the GlobalIrq

9.6 Contactless

interface configuration registers

9.6.1 Error

Error register.

Table 68.

Error register (address 0Ah)

Bit

EE_Err

FiFoWrErr

FIFOOvl

MinFrameErr

NoDataErr

CollDet

ProtErr

IntegErr

Symbol

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Table 69.

Error bits

Bit

Symbol

Description

EE_Err

An error appeared during the last EEPROM command. For

details see the descriptions of the EEPROM commands

FIFOWrErr Data

was written into the FIFO, during a transmission of a possible CRC,

during “RxWait”, “Wait for data” or “Receiving” state, or during an

authentication command. The Flag is cleared when a new CL command is

started. If RxMultiple is active, the flag is cleared after the error flags have

been written to the FIFO.

FIFOOvl

Data is written into the FIFO when it is already full. The data that is already in

the FIFO will remain untouched. All data that is written to the FIFO after this

Flag is set to 1 will be ignored.

Min

A valid SOF was received, but afterwards less then 4 bits of data were

FrameErr received.

Note: Frames with less than 4 bits of data are automatically discarded and the

RxDecoder stays enabled. Furthermore no RxIrq is set. The same is valid for

less than 3 Bytes if the EMD suppression is activated

Note: MinFrameErr is automatically cleared at the start of a receive or

transceive command. In case of a transceive command, it is cleared at the

start of the receiving phase (“Wait for data” state)

NoDataErr Data

should be sent, but no data is in FIFO

CollDet

A collision has occurred. The position of the first collision is shown in the

Note: CollDet is automatically cleared at the start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1.

ProtErr

A protocol error has occurred. A protocol error can be a wrong stop bit, a

missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of

received data bytes. When a protocol error is detected, data reception is

stopped.

Note: ProtErr is automatically cleared at start of a receive or transceive

command. In case of a transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: When a protocol error occurs the last received data byte is not written

into the FIFO.

IntegErr

A data integrity error has been detected. Possible cause can be a wrong

parity or a wrong CRC. In case of a data integrity error the reception is

continued.

Note: IntegErr is automatically cleared at start of a Receive or Transceive

command. In case of a Transceive command, it is cleared at the start of the

receiving phase (“Wait for data” state).

Note: If the NoColl bit is set, also a collision is setting the IntegErr.

9.6.2 Status

Status register.

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Table 70.

Status register (address 0Bh)

Bit

–

Crypto1On

–

Symbol

ComState

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RFU

Table 71.

Status bits

Bit

7 to 6

Symbol

Description

–

RFU

Crypto1On Indicates

if the MIFARE Crypto is on. Clearing this bit is switching the

MIFARE Crypto off. The bit can only be set by the MFAuthent command.

4 to 3

–

RFU

2 to 0

ComState ComState

shows the status of the transmitter and receiver state machine:

000b … Idle

001b … TxWait

011b … Transmitting

101b … RxWait

110b … Wait for data

111b … Receiving

100b … not used

9.6.3 RxBitCtrl

Receiver control register.

Table 72.

RxBitCtrl register (address 0Ch);

Bit

ValuesAfterColl

r/w

RxLastBits

Symbol

RxAlign

r/w

NoColl

r/w

Access

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Table 73.

RxBitCtrl bits

Bit

Symbol

Description

ValuesAfter If

cleared, every received bit after a collision is replaced by a zero. This

Coll

function is needed for ISO/IEC14443 anticollision

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Table 73.

RxBitCtrl bits

Bit

Symbol

Description

6 to 4

RxAlign

Used for reception of bit oriented frames: RxAlign defines the bit position

length for the first bit received to be stored. Further received bits are

stored at the following bit positions.

Example:

RxAlign = 0h – the LSB of the received bit is stored at bit 0, the second

received bit is stored at bit position 1.

RxAlign = 1h – the LSB of the received bit is stored at bit 1, the second

received bit is stored at bit position 2.

RxAlign = 7h – the LSB of the received bit is stored at bit 7, the second

received bit is stored in the following byte at position 0.

Note: If RxAlign = 0, data is received byte-oriented, otherwise

bit-oriented.

NoColl

If this bit is set, a collision will result in an IntegErr

2 to 0

RxLastBits

Defines the number of valid bits of the last data byte received in

bit-oriented communications. If zero the whole byte is valid.

Note: These bits are set by the RxDecoder in a bit-oriented

communication at the end of the communication. They are reset at start

of reception.

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9.6.4 RxColl

High performance NFC reader solution

Receiver collision register.

Table 74.

RxColl register (address 0Dh);

Bit

Symbol

CollPosValid

CollPos

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Table 75.

RxColl bits

Bit

Symbol

Description

CollPos

Valid

If set to 1, the value of CollPos is valid. Otherwise no collision is detected or

the position of the collision is out of the range of bits CollPos.

6 to 0

CollPos

These bits show the bit position of the first detected collision in a received

frame (only data bits are interpreted). CollPos can only be displayed for the

first 8 bytes of a data stream.

Example:

00h indicates a bit collision in the 1st bit

01h indicates a bit collision in the 2nd bit

08h indicates a bit collision in the 9th bit (1st bit of 2nd byte)

3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte)

These bits shall only be interpreted in Passive communication mode at 106

kbit/s or ISO/IEC 14443A/MIFARE reader /writer mode or

ISO/IEC 15693/ICODE SLI read/write mode if bit CollPosValid is set.

Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is included

in the CollPos.

Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is the

last bit of that UID byte). The CollPos = 7h in this case.

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9.7 Timer

configuration registers

9.7.1 TControl

Control register of the timer section.

The TControl implements a special functionality to avoid the not intended modification of

bits.

Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified.

Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4

Table 76.

TControl register (address 0Eh)

Bit

Symbol

T3Running T2Running

T1Running T0Running

T3Start

T2Start

T1Start

T0Start

StopNow

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Table 77.

TControl bits

Bit

Symbol

Description

T3Running

Indicates Timer3 is running.If the bit T3startStopNow is set/reset, this

bit and the timer can be started/stopped

T2Running

T1Running

T0Running

Indicates Timer2 is running. If the bit T2startStopNow is set/reset, this

bit and the timer can be started/stopped

Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this

bit and the timer can be started/stopped

Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this

bit and the timer can be started/stopped

T3StartStop

Now

The bit 7 of TControl T3Running can be modified if set

The bit 6of TControl T2Running can be modified if set

The bit 5of TControl T1Running can be modified if set

The bit 4 of TControl T0Running can be modified if set

T2StartStop

Now

T1StartStop

Now

T0StartStop

Now

9.7.2 T0Control

Control register of the Timer0.

Table 78.

T0Control register (address 0Fh);

Bit

–

T0AutoRestart

r/w

–

Symbol

T0StopRx

r/w

T0Start

r/w

T0Clk

r/w

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Table 79.

T0Control bits

Bit

Symbol

Description

T0StopRx

If set, the timer stops immediately after receiving the first 4 bits. If

cleared the timer does not stop automatically.

Note: If LFO Trimming is selected by T0Start, this bit has no effect.

RFU

–

5 to 4

T0Start

00b: The timer is not started automatically

01b: The timer starts automatically at the end of the transmission

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

T0AutoRestart 1:

the timer automatically restarts its count-down from T0ReloadValue,

after the counter value has reached the value zero.

0: the timer decrements to zero and stops.

The bit Timer1Irq is set to logic 1 when the timer underflows.

–

RFU

1 to 0

T0Clk

00b: The timer input clock is 13.56 MHz.

01b: The timer input clock is 211,875 kHz.

10b: The timer input clock is an underflow of Timer2.

11b: The timer input clock is an underflow of Timer1.

9.7.2.1 T0ReloadHi

High byte reload value of the Timer0.

Table 80.

T0ReloadHi register (address 10h);

Bit

Symbol

T0Reload Hi

r/w

Access

rights

Table 81.

T0ReloadHi bits

Bit

Symbol

Description

7 to 0

T0ReloadHi

Defines the high byte of the reload value of the timer. With the start

event the timer loads the value of the registers T0ReloadValHi,

T0ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.2 T0ReloadLo

Low byte reload value of the Timer0.

Table 82.

T0ReloadLo register (address 11h);

Bit

Symbol

T0ReloadLo

r/w

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Table 83.

T0ReloadLo bits

Bit

Symbol

Description

7 to0

T0ReloadLo

Defines the low byte of the reload value of the timer. With the start

event the timer loads the value of the T0ReloadValHi, T0ReloadValLo.

Changing this register affects the timer only at the next start event.

9.7.2.3 T0CounterValHi

High byte of the counter value of Timer0.

Table 84.

T0CounterValHi register (address 12h)

Bit

Symbol

T0CounterValHi

Access

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Table 85.

T0CounterValHi bits

Bit

Symbol

Description

High byte value of the Timer0.

This value shall not be read out during reception.

7to0

T0Counter

ValHi

9.7.2.4 T0CounterValLo

Low byte of the counter value of Timer0.

Table 86.

T0CounterValLo register (address 13h)

Bit

Symbol

T0CounterValLo

Access

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Table 87.

T0CounterValLo bits

Bit

Symbol

Description

7 to 0

T0CounterValLo

Low byte value of the Timer0.

This value shall not be read out during reception.

9.7.2.5 T1Control

Control register of the Timer1.

Table 88.

T1Control register (address 14h);

Bit

–

T1AutoRestart

r/w

–

Symbol

T1StopRx

r/w

T1Start

r/w

T1Clk

r/w

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Table 89.

T1Control bits

Bit

Symbol

Description

T1StopRx

If set, the timer stops after receiving the first 4 bits. If cleared, the timer

is not stopped automatically.

Note: If LFO trimming is selected by T1start, this bit has no effect.

RFU

–

5 to 4

T1Start

00b: The timer is not started automatically

01b: The timer starts automatically at the end of the transmission

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge)

T1AutoRestart Set

to logic 1, the timer automatically restarts its countdown from

T1ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRq is set to logic 1 when the timer underflows.

–

RFU

1 to 0

T1Clk

00b: The timer input clock is 13.56 MHz

01b: The timer input clock is 211,875 kHz.

10b: The timer input clock is an underflow of Timer0

11b: The timer input clock is an underflow of Timer2

9.7.2.6 T1ReloadHi

High byte (MSB) reload value of the Timer1.

Table 90.

T0ReloadHi register (address 15h)

Bit

Symbol

T1ReloadHi

r/w

Access

rights

Table 91.

T1ReloadHi bits

Bit

Symbol

Description

7 to 0

T1ReloadHi

Defines the high byte reload value of the Timer 1. With the start event

the timer loads the value of the T1ReloadValHi and T1ReloadValLo.

Changing this register affects the Timer only at the next start event.

9.7.2.7 T1ReloadLo

Low byte (LSB) reload value of the Timer1.

Table 92.

T1ReloadLo register (address 16h)

Bit

Symbol

T1ReloadLo

r/w

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Table 93.

T1ReloadValLo bits

Bit

Symbol

Description

7 to 0

T1ReloadLo

Defines the low byte of the reload value of the Timer1. Changing this

9.7.2.8 T1CounterValHi

High byte (MSB) of the counter value of byte Timer1.

Table 94.

T1CounterValHi register (address 17h)

Bit

Symbol

T1CounterValHi

Access

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Table 95.

T1CounterValHi bits

Bit

Symbol

Description

7 to 0

T1Counter

ValHi

High byte of the current value of the Timer1.

This value shall not be read out during reception.

9.7.2.9 T1CounterValLo

Low byte (LSB) of the counter value of byte Timer1.

Table 96.

T1CounterValLo register (address 18h)

Bit

Symbol

T1CounterValLo

Access

rights

Table 97.

T1CounterValLo bits

Bit

Symbol

Description

7 to 0

T1Counter

ValLo

Low byte of the current value of the counter 1.

This value shall not be read out during reception.

9.7.2.10 T2Control

Control register of the Timer2.

Table 98.

T2Control register (address 19h)

Bit

–

T2AutoRestart

r/w

–

Symbol

T2StopRx

r/w

T2Start

r/w

T2Clk

r/w

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Table 99.

T2Control bits

Bit

Symbol

Description

T2StopRx

If set the timer stops immediately after receiving the first 4 bits. If

cleared indicates, that the timer is not stopped automatically.

Note: If LFO Trimming is selected by T2Start, this bit has no effect.

–

RFU

5 to 4

T2Start

00b: The timer is not started automatically.

01b: The timer starts automatically at the end of the transmission.

10b: Timer is used for LFO trimming without underflow (Start/Stop on

PosEdge).

11b: Timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

T2AutoRestart Set

to logic 1, the timer automatically restarts its countdown from

T2ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops. The bit

Timer2IRq is set to logic 1 when the timer underflows

–

RFU

1 to 0

T2Clk

00b: The timer input clock is 13.56 MHz.

01b: The timer input clock is 212 kHz.

10b: The timer input clock is an underflow of Timer0

11b: The timer input clock is an underflow of Timer1

9.7.2.11 T2ReloadHi

High byte of the reload value of Timer2.

Table 100.

T2ReloadHi register (address 1Ah)

Bit

Symbol

T2ReloadHi

r/w

Access

rights

Table 101.

T2Reload bits

Bit

Symbol

Description

7 to 0

T2ReloadHi

Defines the high byte of the reload value of the Timer2. With the start

event the timer load the value of the T2ReloadValHi and

T2ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.12 T2ReloadLo

Low byte of the reload value of Timer2.

Table 102.

T2ReloadLo register (address 1Bh)

Bit

Symbol

T2ReloadLo

r/w

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Table 103.

T2ReloadLo bits

Bit

Symbol

Description

7 to 0

T2ReloadLo

Defines the low byte of the reload value of the Timer2. With the start

event the timer load the value of the T2ReloadValHi and

T2RelaodVaLo. Changing this register affects the timer only at the next

start event.

9.7.2.13 T2CounterValHi

High byte of the counter register of Timer2.

Table 104.

T2CounterValHi register (address 1Ch)

Bit

Symbol

T2CounterValHi

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Table 105.

T2CounterValHi bits

Bit

Symbol

Description

7 to 0

T2Counter

ValHi

High byte current counter value of Timer2.

This value shall not be read out during reception.

9.7.2.14 T2CounterValLoReg

Low byte of the current value of Timer 2.

Table 106.

T2CounterValLo register (address 1Dh)

Bit

Symbol

T2CounterValLo

Access

rights

Table 107.

T2CounterValLo bits

Bit

Symbol

Description

7 to 0

T2Counter

ValLo

Low byte of the current counter value of Timer1Timer2.

This value shall not be read out during reception.

9.7.2.15 T3Control

Control register of the Timer 3.

Table 108.

T3Control register (address 1Eh)

Bit

–

T3AutoRestart

r/w

–

Symbol

T3StopRx

r/w

T3Start

r/w

T3Clk

r/w

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Table 109.

T3Control bits

Bit

Symbol

Description

T3StopRx

If set, the timer stops immediately after receiving the first 4 bits. If

cleared, indicates that the timer is not stopped automatically.

Note: If LFO Trimming is selected by T3Start, this bit has no effect.

RFU

–

5 to 4

T3Start

00b – timer is not started automatically

01b – timer starts automatically at the end of the transmission

10b – timer is used for LFO trimming without underflow (Start/Stop on

PosEdge)

11b – timer is used for LFO trimming with underflow (Start/Stop on

PosEdge).

T3AutoRestart Set

to logic 1, the timer automatically restarts its countdown from

T3ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops.

The bit Timer1IRq is set to logic 1 when the timer underflows.

–

RFU

1 to 0

T3Clk

00b – the timer input clock is 13.56 MHz.

01b – the timer input clock is 211,875 kHz.

10b – the timer input clock is an underflow of Timer0

11b – the timer input clock is an underflow of Timer1

9.7.2.16 T3ReloadHi

High byte of the reload value of Timer3.

Table 110.

T3ReloadHi register (address 1Fh);

Bit

Symbol

T3ReloadHi

r/w

Access

rights

Table 111.

T3ReloadHi bits

Bit

Symbol

Description

7 to 0

T3ReloadHi

Defines the high byte of the reload value of the Timer3. With the start

event the timer load the value of the T3ReloadValHi and

T3ReloadValLo. Changing this register affects the timer only at the

next start event.

9.7.2.17 T3ReloadLo

Low byte of the reload value of Timer3.

Table 112.

T3ReloadLo register (address 20h)

Bit

Symbol

T3ReloadLo

r/w

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Table 113.

T3ReloadLo bits

Bit

Symbol

Description

7 to 0

T3ReloadLo

Defines the low byte of the reload value of Timer3. With the start event

the timer load the value of the T3ReloadValHi and T3RelaodValLo.

Changing this register affects the timer only at the next start event.

9.7.2.18 T3CounterValHi

High byte of the current counter value the 16-bit Timer3.

Table 114.

T3CounterValHi register (address 21h)

Bit

Symbol

T3CounterValHi

Access

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Table 115.

T3CounterValHi bits

Bit

Symbol

Description

7 to 0

T3Counter

ValHi

High byte of the current counter value of Timer3.

This value shall not be read out during reception.

9.7.2.19 T3CounterValLo

Low byte of the current counter value the 16-bit Timer3.

Table 116.

T3CounterValLo register (address 22h)

Bit

Symbol

T3CounterValLo

Access

rights

Table 117.

T3CounterValLo bits

Bit

Symbol

Description

7 to 0

T3Counter

ValLo

Low byte current counter value of Timer3.

This value shall not be read out during reception.

9.7.2.20 T4Control

The wake-up timer T4 activates the system after a given time. If enabled, it can start the

low power card detection function.

Table 118.

T4Control register (address 23h)

Bit

Symbol

T4Running

T4Start

StopNow

T4Auto

Trimm

T4Auto

LPCD

T4Auto

Restart

T4AutoWakeUp

T4Clk

r/w

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r/w

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Table 119.

T4Control bits

Bit

Symbol

Description

T4Running

Shows if the timer T4 is running. If the bit T4StartStopNow is set, this

bit and the timer T4 can be started/stopped.

T4Start

StopNow

if set, the bit T4Running can be changed.

T4AutoTrimm

If set to one, the timer activates an LFO trimming procedure when it

underflows. For the T4AutoTrimm function, at least one timer (T0 to

T3) has to be configured properly for trimming (T3 is not allowed if

T4AutoLPCD is set in parallel).

T4AutoLPCD

If set to one, the timer activates a low-power card detection

sequence. If a card is detected an interrupt request is raised and the

system remains active if enabled. If no card is detected the OM9663

enters the Power down mode if enabled. The timer is automatically

restarted (no gap). Timer 3 is used to specify the time where the RF

field is enabled to check if a card is present. Therefor you may not

use Timer 3 for T4AutoTrimm in parallel.

T4AutoRestart

Set to logic 1, the timer automatically restarts its countdown from

T4ReloadValue, after the counter value has reached the value zero.

Set to logic 0 the timer decrements to zero and stops. The bit

Timer4Irq is set to logic 1 at timer underflow.

T4AutoWakeUp If

set, the OM9663 wakes up automatically, when the timer T4 has an

underflow. This bit has to be set if the IC should enter the Power

down mode after T4AutoTrimm and/or T4AutoLPCD is finished and

no card has been detected. If the IC should stay active after one of

these procedures this bit has to be set to 0.

1 to 0

T4Clk

00b – the timer input clock is the LFO clock

01b – the timer input clock is the LFO clock/8

10b – the timer input clock is the LFO clock/16

11b – the timer input clock is the LFO clock/32

9.7.2.21 T4ReloadHi

High byte of the reload value of the 16-bit timer 4.

Table 120.

T4ReloadHi register (address 24h)

Bit

Symbol

T4ReloadHi

r/w

Access

rights

Table 121.

T4ReloadHi bits

Bit

Symbol

Description

7 to 0

T4ReloadHi

Defines high byte of the for the reload value of timer 4. With the start

event the timer 4 loads the T4ReloadVal. Changing this register affects

the timer only at the next start event.

9.7.2.22 T4ReloadLo

Low byte of the reload value of the 16-bit timer 4.

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Table 122.

T4ReloadLo register (address 25h)

Bit

Symbol

T4ReloadLo

r/w

Access

rights

Table 123.

T4ReloadLo bits

Bit

Symbol

Description

7 to 0

T4ReloadLo

Defines the low byte of the reload value of the timer 4. With the start

event the timer loads the value of the T4ReloadVal. Changing this

9.7.2.23 T4CounterValHi

High byte of the counter value of the 16-bit timer 4.

Table 124.

T4CounterValHi register (address 26h)

Bit

Symbol

T4CounterValHi

Access

rights

Table 125.

T4CounterValHi bits

Bit

Symbol

Description

High byte of the current counter value of timer 4.

7 to 0

T4CounterValHi

9.7.2.24 T4CounterValLo

Low byte of the counter value of the 16-bit timer 4.

Table 126.

T4CounterValLo register (address 27h)

Bit

Symbol

T4CounterValLo

Access

rights

Table 127.

T4CounterValLo bits

Bit

Symbol

Description

Low byte of the current counter value of the timer 4.

7 to 0

T4CounterValLo

9.8 Transmitter

configuration registers

9.8.1 TxMode

Table 128.

DrvMode register (address 28h)

Bit

–

TxClk Mode

r/w

Symbol

Tx2Inv

r/w

Tx1Inv

r/w

TxEn

r/w

Access

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RFU

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Table 129.

DrvMode bits

Bit

Symbol

Tx2Inv

Tx1Inv

Description

Inverts transmitter 2 at TX2 pin

Inverts transmitter 1 at TX1 pin

RFU

–

RFU

TxEn

If set to 1 both transmitter pins are enabled

2 to 0

TxClkMode

Transmitter clock settings (see 8.6.2.

ble 27). Codes 011b and

0b110 are not supported. This register defines, if the output is

operated in open drain, push-pull, at high impedance or pulled to a fix

high or low level.

9.8.2 TxAmp

With the set_cw_amplitude register output power can be traded off against power supply

rejection. Spending more headroom leads to better power supply rejection ration and

better accuracy of the modulation degree.

With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register

overrides the settings made by set_cw_amplitude.

Table 130.

TxAmp register (address 29h)

Bit

–

set_residual_carrier

r/w

Symbol

set_cw_amplitude

r/w

Access

rights

RFU

Table 131.

TxAmp bits

Bit

Symbol

Description

7 to 6

set_cw_amplitude

Allows to reduce the output amplitude of the transmitter by a fix

value.

Four different preset values that are subtracted from TVDD can

be selected:

0: TVDD -100 mV

1: TVDD -250 mV

2: TVDD -500 mV

3: T

VDD

-1000 mV

–

RFU

4 to 0

set_residual_ carrier

Set the residual carrier percentage. refer to

Section 8.6.2

9.8.3 TxCon

Table 132.

TxCon register (address 2Ah)

Bit

OvershootT2

r/w

Symbol

CwMax

r/w

TxInv

r/w

TxSel

r/w

Access

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Table 133.

TxCon bits

Bit

Symbol

Description

7 to 4

OvershootT2 Specifies

the length (number of carrier clocks) of the additional

modulation for overshoot prevention. Refer to

Section 8.6.2.1

“Overshoot protection”

Cwmax

Set amplitude of continuous wave carrier to the maximum.

If set, set_cw_amplitude in Register TxAmp has no influence on the

continuous amplitude.

TxInv

TxSel

If set, the resulting modulation signal defined by TxSel is inverted

1 to 0

Defines which signal is used as source for modulation

00b … no modulation

01b … TxEnvelope

10b … SigIn

11b … RFU

9.8.4 Txl

Table 134.

Txl register (address 2Bh)

Bit

OvershootT1

r/w

Symbol

tx_set_iLoad

r/w

Access

rights

Table 135.

Txl bits

Bit

Symbol

Description

7 to 4

OvershootT1 Overshoot

value for Timer1. Refer to

Section 8.6.2.1 “Overshoot

protection”

3 to 0

tx_set_iLoad

Factory trim value, sets the expected Tx load current. This value is

used to control the modulation index in an optimized way dependent

on the expected TX load current.

9.9 CRC

configuration registers

9.9.1 TxCrcPreset

Table 136.

TXCrcPreset register (address 2Ch)

Bit

RFU

–

TxCRCInvert

r/w

Symbol

TXPresetVal

r/w

TxCRCtype

r/w

TxCRCEn

r/w

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Table 137.

TxCrcPreset bits

Bit

Symbol

Description

RFU

–

6 to 4

3 to 2

TXPresetVal

TxCRCtype

Specifies the CRC preset value for transmission (see

ble 138

Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:

•

00h — CRC5

•

01h — CRC8

•

02h — CRC16

•

03h — RFU

TxCRCInvert if

set, the resulting CRC is inverted and attached to the data frame

(ISO/IEC 3309)

TxCRCEn

if set, a CRC is appended to the data stream

Table 138.

Transmitter CRC preset value configuration

TXPresetVal[6…4]

CRC16

0000h

6363h

A671h

FFFEh

–

CRC8

CRC5

00h

12h

BFh

–

FDh

–

User defined

FFFFh

User defined

FFh

User defined

1Fh

Remark:

User defined CRC preset values can be configured by EEprom (see

Section 8.7.2.1

ble 35 “Configuration area (Page 0)”

9.9.2 RxCrcCon

Table 139.

RxCrcCon register (address 2Dh)

Bit

RxForceCRCWrite

r/w

RxCRCInvert

r/w

RxCRCEn

r/w

Symbol

RXPresetVal

r/w

RXCRCtype

r/w

Access

rights

Table 140.

RxCrcCon bits

Bit

Symbol

Description

RxForceCrc

Write

If set, the received CRC byte(s) are copied to the FIFO.

If cleared CRC Bytes are only checked, but not copied to the FIFO.

This bit has to be always set in case of a not byte aligned CRC (e.g.

ISO/IEC 18000-3 mode 3/ EPC Class-1HF)

6 to 4

RXPresetVal

Defines the CRC preset value (Hex.) for transmission. (see

ble 141

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Table 140.

RxCrcCon bits

Bit

Symbol

Description

3 to 2

RxCRCtype

Defines which type of CRC (CRC8/CRC16/CRC5) is calculated:

•

00h — CRC5

•

01h — CRC8

•

02h — CRC16

•

03h — RFU

RxCrcInvert

RxCrcEn

If set, the CRC check is done for the inverted CRC.

If set, the CRC is checked and in case of a wrong CRC an error flag is

set. Otherwise the CRC is calculated but the error flag is not modified.

Table 141.

Receiver CRC preset value configuration

RXPresetVal[6…4]

CRC16

0000h

6363h

A671h

FFFEh

–

CRC8

CRC5

00h

12h

BFh

–

FDh

–

User defined

FFFFh

User defined

FFh

User defined

1Fh

9.10 Transmitter

configuration registers

9.10.1 TxDataNum

Table 142.

TxDataNum register (address 2Eh)

Bit

KeepBitGrid

r/w

TxLastBits

r/w

Symbol

RFU

RFU-

DataEn

r/w

Access

rights

Table 143.

TxDataNum bits

Bit

7 to 5

Symbol

RFU

Description

–

KeepBitGrid

If set, the time between consecutive transmissions starts is a multiple

of one ETU. If cleared, consecutive transmissions can even start

within one ETU

DataEn

If cleared – it is possible to send a single symbol pattern.

If set – data is sent.

2 to 0

TxLastBits

Defines how many bits of the last data byte to be sent. If set to 000b all

bits of the last data byte are sent.

Note – bits are skipped at the end of the byte.

Example – Data byte B2h (sent LSB first).

TxLastBits = 011b (3h) => 010b (LSB first) is sent

TxLastBits = 110b (6h) => 010011b (LSB first) is sent

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9.10.2 TxDATAModWidth

Transmitter data modulation width register

Table 144.

TxDataModWidth register (address 2Fh)

Bit

Symbol

DModWidth

r/w

Access

rights

Table 145.

TxDataModWidth bits

Bit

Symbol

Description

7 to 0

DModWidth

Specifies the length of a pulse for sending data with enabled pulse

modulation. The length is given by the number of carrier clocks + 1.

A pulse can never be longer than from the start of the pulse to the end

of the bit. The starting position of a pulse is given by the setting of

TxDataMod.DPulseType. Note: This register is only used if Miller

modulation (ISO/IEC 14443A PCD) is used. The settings are also

used for the modulation width of start and/or stop symbols.

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9.10.3 TxSym10BurstLen

If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with

this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl.

Table 146.

TxSym10BurstLen register (address 30h)

Bit

RFU

–

RFU

–

Sym0Burst Len

r/w

Symbol

Sym1Burst Len

r/w

Access

rights

Table 147.

TxSym10BurstLen bits

Bit

Symbol

Description

RFU

–

6 to 4

Sym1BurstLen Specifies

the number of bits issued for symbol 1 burst. The 3 bits

encodes a range from 8 to 256 bit:

00h – 8bit

01h – 16bit

02h – 32bit

04h – 48bit

05h – 64bit

06h – 96bit

07h – 128bit

08h – 256bit

RFU

–

2 to 0

Sym0BurstLen Specifies

the number of bits issued for symbol 1 burst. The 3 bits

encodes a range from 8 to 256 bit:

00h – 8bit

01h – 16bit

02h – 32bit

03h – 48bit

04h – 64bit

05h – 96bit

06h – 128bit

07h – 256bit

9.10.4 TxWaitCtrl

Table 148.

TxWaitCtrl register (address 31h); reset value: C0h

Bit

TxWaitStart

r/w

TxWait High

r/w

TxStopBitLength

r/w

Symbol

TxWaitEtu

r/w

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Table 149.

TXWaitCtrl bits

Bit

Symbol

Description

TxWaitStart

If cleared, the TxWait time is starting at the End of the send data

(TX).

If set, the TxWait time is starting at the End of the received data

(RX).

TxWaitEtu

If cleared, the TxWait time is TxWait



16/13.56 MHz.

If set, the TxWait time is TxWait



0.5 / DBFreq (DBFreq is the

frequency of the bit stream as defined by TxDataCon).

5 to 3

2 to 0

TxWait High

Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB.

TxStopBitLength

Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to

be send:

0h: no stop-bit, no EGT

1h: 1 stop-bit, no EGT

2h: 1 stop-bit + 1 EGT

3h: 1 stop-bit + 2 EGT

4h: 1 stop-bit + 3 EGT

5h: 1 stop-bit + 4 EGT

6h: 1 stop-bit + 5 EGT

7h: 1 stop-bit + 6 EGT

Note: This is only valid for ISO/IEC14443 Type B

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9.10.5 TxWaitLo

Table 150.

TxWaitLo register (address 32h)

Bit

Symbol

TxWaitLo

r/w

Access

rights

Table 151.

TxWaitLo bits

Bit

Symbol

Description

7 to 0

TxWaitLo

Defines the minimum time between receive and send or between two

send data streams

Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl

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