NXP-Semicon-PN7161A1EV-C100K

PN7160_PN7161  

Near Field Communication (NFC) controller  

Rev. 3.9 — 8 March 2023  

Product data sheet  

1 Introduction  

This data sheet describes the PN7160 and PN7161 NFC controllers with NCI interface and integrated firmware.  

The PN7161 support all features of PN7160 plus “Enhanced Contactless Polling” (ECP) by Apple (see Ref.  

). Please note, that the ECP feature is available after formal authorization only.  

In the following document PN7160 refers to PN7160 and PN7161, otherwise stated.  

This data sheet requires additional documents for functional chip description and design in. Refer to the  

references listed in this document for full list of documentation provided by NX

P

.  

NXP Semiconductors  

PN7160_PN7161  

Near Field Communication (NFC) controller  

2 General

 

description  

PN7160 is an NFC controller designed for integration in mobile devices and devices compliant with NFC  

standards (NFC Forum, NCI).  

PN7160 is designed based on experience from previous NXP NFC device generation to ease the integration of  

NFC technology in mobile devices by providing:  

•

A low PCB footprint and a reduced external Bill of Material  

•

An optimized architecture for low-power consumption in different modes (Standby, low-power polling loop)  

•

A highly efficient integrated power management unit allowing direct supply from an extended battery supply  

range (2.8 V to 5.5 V).  

•

Support of an external DC-to-DC like NXP PCA941xA (with x = 0, 1 and 2), to provide more output power.  

PN7160 embeds a new generation RF contactless front-end, supporting various transmission modes according  

to NFCIP-1 (see Ref.

) and NFCIP-2 (see Ref.

), ISO/IEC14443 (see Ref.

) , ISO/IEC 15693 (see Ref.  

), MIFARE and FeliCa specifications. This new contactless front-end design brings a major performance  

step-up with on one hand a higher sensitivity and on the other hand the capability to work in active load  

modulation communication enabling the support of small antenna form factor. It also allows to provide a higher  

output power by supplying the transmitter output stage from 2.7 V to 5.25

V

.  

•

Enhanced Dynamic LMA (DLMA) to optimize and to enhance load modulation amplitude depending on  

external field strength. It allows higher range communication distance in card mode.  

•

Independent LMA phase adjustment by step of 5° for type A, B and F  

•

Dynamic power control which allows to make use of the maximum power in reader mode without exceeding  

the maximum power allowed by the standard in 0 distance.  

•

Card mode receiver sensitivity of 20 mV

(p-p)  

•

Support of single ended receiver  

•

1.3 W output transmitter power  

Supported transmission modes are listed in

. For contactless card functionality, the PN7160 can act  

autonomously if previously configured by the host in such a manner. PICC functionality can be supported  

without host being turned on.  

NFC FORUM  

NFC-IP MODES  

READER  

(PCD – VCD)  

CARD  

(PICC)  

READER FOR NFC FORUM  

TAGS 1 TO 5  

ISO/IEC 14443 A  

ISO/IEC 14443 B  

ISO/IEC 15693  

T4T – ISO/IEC 14443 A  

T4T – ISO/IEC 14443 B  

P2P ACTIVE  

106 TO 424 kbps  

INITIATOR AND TARGET  

MIFARE 1K / 4K  

MIFARE DESFire  

P2P PASSIVE  

106 TO 424 kbps  

INITIATOR AND TARGET  

(1)  

Sony FeliCa  

aaa-042748  

1. According

 

to ISO/IEC 18092 (Ecma 340) standard.  

Figure 1.ꢀPN7160 transmission modes  

PN7160_PN7161  

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Product data sheet  

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NXP Semiconductors  

PN7160_PN7161  

Near Field Communication (NFC) controller  

3 Features

 

and benefits  

•

Highly integrated demodulator and decoder  

•

Buffered output drivers to connect an antenna with minimum number of external components  

•

Integrated RF level detector  

•

Integrated Polling Loop for automatic device discovery  

•

RF protocols supported  

–

ISO/IEC 14443A, ISO/IEC 14443B PICC mode  

–

ISO/IEC 14443A, ISO/IEC 14443B PCD mode designed according to NFC Forum digital protocol T4T  

platform and ISO-DEP (see Ref.

)  

–

FeliCa PCD mode  

–

MIFARE PCD encryption mechanism (MIFARE 1K/4K)  

–

NFC Forum tags T1

T

,

T

2

T

,

T

3

T

,

T

4T and T5T (see Ref.

)  

–

NFCIP-1, NFCIP-2 protocol (see Ref.

and Ref.

)  

–

NFC Forum certification for P2

P

,

r

eader and card mode (see Ref.

)  

–

ISO/IEC 15693/ICODE VCD mode (see Ref.

)  

–

NFC Forum-compliant embedded T4T for NDEF short record  

–

Support for “Enhanced Contactless Polling” by Apple (see Ref.

) (PN7161 only)  

•

Supported host interfaces  

–

NCI protocol interface according to NFC Forum standardization (see Ref.

)  

–

I

2

C-bus High-speed mode (see Ref.

)  

–

SPI-bus (see Ref.

)  

•

Flexible clock supply concept to facilitate PN7160 integration  

–

Internal oscillator for 27.12 MHz crystal connection  

–

Integrated PLL unit to make use of device reference clock and facilitate PN7160 integration  

•

Integrated power management unit  

–

Direct connection to a battery (2.5 V to 5.5 V voltage supply range)  

–

Support different low-power states configuration: Hard Power-Down state and Standby state activated by  

firmware  

–

Autonomous mode when host is shut down  

•

Automatic wake-up via RF field, internal timer, and host interfaces  

•

Integrated non-volatile memory to store data and executable code for customization  

–

Anti tearing support to recover from tearing events  

•

Standards compliance  

–

NFC Forum Device Requirements (see Ref.

)  

–

NCI 2.0  

PN7160_PN7161  

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Product data sheet  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

4 Applications  

•

Mobile devices  

•

Portable equipment (personal digital assistants, tablet, notebook, wearable)  

•

Consumer devices  

•

Smart home gateways  

PN7160_PN7161  

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Product data sheet  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

5 Quick

 

reference data  

Table 1.ꢀQuick reference data  

Symbol  

Parameter  

Conditions  

Min  

Typ  

Max Unit  

V

BAT  

battery supply voltage  

Card Emulation and Passive

T

a

rget;  

V

SS

= 0 V  

2.5  

–

5.5  

5.5  

5.8  

5.8  

V

V

V

V

Reader, Active Initiator and Active  

T

a

rget; V

SS

= 0 V  

2.8  

2.8  

2.5  

–

–

–

V

DD(UP)  

V

DD(UP)

input supply voltage  

Reader, Active Initiator and Active  

T

a

rget; V

SS

= 0 V  

All other cases except Hard Power  

Down state; V

SS

= 0 V  

V

DD(PAD)  

V

DD(PAD)

supply voltage  

battery supply current  

supply voltage for host interface; V

SS  

= 0 V  

1.65  

3.0  

–

1.8  

1.95  

3.6  

16  

V

3.3  

V

I

BAT  

in Hard Power Down state; V

BAT  

3.6 V; T = 25 °C  

=

10.5  

μA  

in Standby state; V

BAT

= 3.6 V  

enhanced RF detector  

–

–

–

32  

52  

36  

–

μA  

μA  

μA  

low sensitivity RF detector  

21  

in low-power polling loop; V

BAT

= 3.6  

V; T = 25 °C; loop time = 500 ms  

100  

continuous total current consumption  

in PCD mode at V

BAT

= 3.6 V  

–

–

290  

mA  

I

th(Ilim)  

P

tot  

current limit threshold  

total power dissipation  

current limiter on transmitter  

270  

–

300  

–

330  

620  

mA  

PCD mode at typical V

DD(TX)

= 5.25  

V,

V

DD(UP)

= 5.8 V and V

BAT

= 3.6  

V; includes power from V

BAT

and  

V

DD(UP)  

mW  

T

amb  

ambient operating temperature

 

JEDEC PCB-0.5  

-30  

–

+85  

°C  

[1] V

SS

represents V

SS(PAD)

and V

SS(TX)  

.

[2] When

 

V

DD(UP)

is below 2.8 V the TXLDO can be in follower mode (see

), there will be no more V

DD(UP)

noise rejection. Any noise below 848  

kbit/s will affect the performance.  

[3] External

 

clock on NFC_CLK_XTAL1 must be LOW.  

[4] This

 

is considering an antenna tuned to sink maximum 250 mA continuous current from the transmitter. The antenna shall be tuned to never exceed this  

250 mA maximum current.  

PN7160_PN7161  

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Product data sheet  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

6 Firmware

 

versions  

6.1 Version

 

12.50.09  

Changes in this version:  

•

NDEF write from NFC supported, when the device is in Autonomous NDEF mode.  

•

ECP supported in EMVCo profile (PN7161 only).  

•

Optimized card removal procedure when ECP is enabled (PN7161 only).  

•

Added PRBS support for ISO/IEC 15693.  

•

This version is not available on hardware, only as firmware update file  

6.2 Version

 

12.50.06  

Changes in this version:  

•

Changes to support NFC Forum CR12.  

•

Added helper command to configure the Dynamic Power Control (DPC)  

•

This version is not available on hardware, only as firmware update file  

6.3 Version

 

12.50.05  

Initial version  

Production samples will have 12.50.05 firmware.  

PN7160_PN7161  

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Product data sheet  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

7 Ordering

 

information  

Table 2.ꢀOrdering information  

Type number  

Package  

Name  

Description  

Version  

PN7160xyzz/C100

VFBGA64  

plastic very thin fine-pitch ball grid array package;  

64 balls  

SOT1860-1  

SOT618-1  

SOT1860-1  

SOT618-1  

HVQFN40  

VFBGA64  

HVQFN40  

plastic thermal enhanced very thin quad flat  

package; no leads; 40 terminals  

PN7161xyzz/C100

plastic very thin fine-pitch ball grid array package;  

64 balls  

plastic thermal enhanced very thin quad flat  

package; no leads; 40 terminals  

[1] x:

 

A = I

2

C-bus interface; B = SPI-bus interface.  

[2] y:

 

correspond to firmware variant.  

[3] zz:

 

correspond to package variant. HN = HVQFN40 package; EV = VFBGA64 package.  

PN7160 is available in different configurations:  

Table 3.ꢀProduct variants PN7160  

Part number  

Control  

Package  

Packing  

MOQ  

Marking  

12NC  

interface /  

firmware  

version  

PN7160A1EV/ I

2

C / 12.50.05  

C100  

PN7160A1EV/ I

2

C / 12.50.05  

C100  

PN7160A1HN/ I

2

C / 12.50.05  

C100  

PN7160A1HN/ I

2

C / 12.50.05  

C100  

VFBGA64  

VFBGA64  

HVQFN40  

HVQFN40  

VFBGA64  

VFBGA64  

HVQFN40  

HVQFN40  

Reel  

4500  

2450  

4000  

490  

71601  

71601  

71601  

71601  

71602  

71602  

71602  

71602  

9354 166 64518  

9354 166 64557  

9354 166 65518  

9354 166 65551  

9354 237 43518  

9354 237 43557  

9354 237 44518  

9354 237 44551  

5-Tray  

Reel  

1-Tray  

Reel  

PN7160B1EV/ SPI

 

/ 12.50.05  

C100  

4500  

2450  

4000  

490  

PN7160B1EV/ SPI

 

/12.50.05  

C100  

5-Tray  

Reel  

PN7160B1HN/ SPI

 

/12.50.05  

C100  

PN7160B1HN/ SPI

 

/ 12.50.05  

C100  

1-Tray  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

Table 4.ꢀProduct variants PN7161  

Part number  

Control  

Package  

Packing  

MOQ  

Marking  

12NC  

interface/firmwar

e  

version  

PN7161A1EV/ I

2

C / 12.50.05  

C100  

PN7161A1EV/ I

2

C / 12.50.05  

C100  

PN7161A1HN/ I

2

C / 12.50.05  

C100  

PN7161A1HN/ I

2

C / 12.50.05  

C100  

VFBGA64  

VFBGA64  

HVQFN40  

HVQFN40  

VFBGA64  

VFBGA64  

HVQFN40  

HVQFN40  

Reel  

4500  

2450  

4000  

490  

71611  

71611  

71611  

71611  

71612  

71612  

71612  

71612  

9354 237 58518  

9354 237 58557  

9354 237 59518  

9354 237 59551  

9354 237 61518  

9354 237 61557  

9354 237 62518  

9354 237 62551  

5-Tray  

Reel  

1-Tray  

Reel  

PN7161B1EV/ SPI

 

/ 12.50.05  

C100  

4500  

2450  

4000  

490  

PN7161B1EV/ SPI

 

/ 12.50.05  

C100  

5-Tray  

Reel  

PN7161B1HN/ SPI

 

/ 12.50.05  

C100  

PN7161B1HN/ SPI

 

/ 12.50.05  

C100  

1-Tray  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

8 Marking  

8.1 Marking

 

VFBGA64  

aaa-007526  

Figure 2.ꢀPN7160 package marking (top view)  

Table 5.ꢀMarking code  

Line number  

Line 1  

Marking code  

product version identification  

diffusion batch sequence number + assembly lot ID  

Line 2  

Line 3  

manufacturing code including:  

•

diffusion center code:  

–

S: Power chip (PTCT)  

•

assembly center code:  

–

S: ATKH  

•

RoHS compliancy indicator:  

–

D: Dark Green; fully compliant RoHS and no halogen and antimony  

•

manufacturing year and week, 3 digits:  

–

Y: year  

–

WW: week code  

•

product life cycle status code:  

–

X: means not qualified product  

–

nothing means released product  

PN7160_PN7161  

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8.2 Marking

 

HVQFN40  

PN7160_PN7161  

Near Field Communication (NFC) controller  

terminal 1  

index area  

A : 7  

B1 : 6  

B2 : 6  

C : 8  

0

5

aaa-043477  

Figure 3.ꢀPN7160 Package marking HVQFN40 (top view)  

Table 6.ꢀMarking codes  

Type number  

Marking code  

Line A  

7 characters used: product version identification  

Line B1 + Line B2  

Diffusion Bath ID (9 digits) + space + assembly ID number (2  

digits)  

Line C  

8 characters used: manufacturing code  

including:  

•

diffusion center code:  

–

S: Power chip (PTCT)  

•

assembly center code:  

–

S: ATKH  

•

RoHS compliancy indicator:  

–

D: Dark Green; fully compliant RoHS  

and no halogen and antimony  

•

manufacturing year and week, 3 digits:  

–

YY: year  

–

WW: week code  

•

product life cycle status code:  

–

X: means not qualified product  

–

nothing means released product  

PN7160_PN7161  

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Product data sheet  

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NXP Semiconductors  

PN7160_PN7161  

Near Field Communication (NFC) controller  

9 Block

 

diagram  

CLESS  

CLESS UART  

HOST INTERFACE  

INTERFACE UNIT  

2

SPI-bus I

 

C-bus  

RF DETECT  

DEMOD  

DRIVER  

PLL  

SENSOR  

ADC  

RX CODEC  

TX CODEC  

SIGNAL  

PROCESSING  

TxCtrl  

BG  

ARM  

DATA  

CORTEX M0  

MEMORY  

SRAM  

8 kBytes  

VMID  

EEPROM  

4 kBytes  

MEMORY  

CONTROL  

AHB to APB  

CODE  

MEMORY  

POWER  

MANAGEMENT UNIT  

MISCELLANEOUS  

CLOCK MANAGEMENT UNIT  

OSCILL

A

TOR OSCILLATOR  

ROM  

128 kBytes  

TEMPERATURE  

SENSOR  

TIMERS  

5.25 V  

TXLDO  

370 kHz  

40 MHz  

EEPROM  

28 kBytes  

FRACN  

PLL  

QUARTZ  

OSCILL

A

TOR  

CRC  

1.8 V  

COPROCESSOR  

DSLDO  

RANDOM  

NUMBER  

GENERATOR  

aaa-04

1

1

81  

Figure 4.ꢀPN7160 block diagram  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

10 Pinning

 

information  

10.1 Pinning  

H

G

F

terminal 1  

index area  

2

I C_ADR0/SPI_NSS  

DWL_REQ  

1

2

3

4

5

6

7

8

9

30 NFC_CLK_XTA

L

1  

29 X

T

A

L2  

E

D

C

B

A

2

I C_ADR1/SPI_MOSI  

28  

27  

26  

25  

V

V

V

V

BAT  

V

SS(PAD)  

DD  

2

I C_SDA/SPI_MISO  

DD(A)  

DD(HF)  

NFCC  

V

DD(PAD)  

2

I C_SCL/SPI_SCK  

IRQ  

24 ANT2  

23 ANT1  

ball A1  

index area  

1

2

3

4

5

6

7

8

V

22  

V

DD_IN2  

V

SS(A)  

SS  

aaa-027834  

VEN 10  

21 TX1  

Figure 5.ꢀPN7160 pinning VFBGA64 (bottom view)  

T

r

ansparent top view  

aaa-04

1

144  

Figure 6.ꢀPN7160 pinning HVQFN40  

Table 7.ꢀPN7160 pin description  

Symbol  

Pin  

Pin  

Type

Refer  

Description  

HVQFN40  

VFBGA64  

I

2

C_ADR0/SPI_NSS  

DWL_REQ  

I

2

C_ADR1/SPI_MOSI  

1

2

3

4

C3  

D3  

D1  

C1  

I/O  

I

V

DD(PAD)

Host interface pin 1  

V

DD(PAD)

Firmware download control pin  

V

DD(PAD)

Host interface pin 2  

I/O  

G

V

SS(PAD)  

n/a  

Pad ground. Must be connected to  

ground.  

I

2

C_SDA/SPI_MISO  

V

DD(PAD)  

I

2

C_SCL/SPI_SCK  

5

E1  

D2  

E2  

E3  

G3  

H1  

I/O  

P

V

DD(PAD)

Host interface pin 3  

n/a Pad

 

supply voltage  

6

7

I/O  

O

V

DD(PAD)

Host interface pin 4  

IRQ  

8

V

DD(PAD)

Interrupt request output  

V

SS(A)  

9

G

n/a  

Analog ground supply voltage  

VEN  

10  

I

V

BAT  

Reset pin. Set the device in Hard Power  

Down.  

i.c.  

11  

12  

–

–

–

–

Internally Connected.

T

o

b

e left open.  

V

BAT2  

P

n/a  

Battery supply voltage. Must be  

connected to V

BAT

. VFBGA package:  

internally connected.  

V

DD(UP)  

V

DD(TX)  

RXN  

13  

14  

15  

H3  

G7  

H6  

P

P

I

n/a  

TXLDO input supply voltage  

Transmitter supply voltage  

Negative receiver input  

n/a  

V

DD(A)  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

Table 7.ꢀPN7160 pin description

…continued  

Symbol  

Pin  

Pin  

Type

Refer  

Description  

HVQFN40  

VFBGA64  

RXP  

16  

17  

18  

H5  

H4  

–

I

V

DD(A)  

n/a  

Positive receiver input  

V

DD(VMID)  

TVDD_IN  

P

P

Receiver reference input supply voltage  

n/a  

Must be connected to V

DD(TX)

and  

TVDD_IN2. VFBGA package: internally  

connected.  

TX2  

19  

20  

H7  

H8  

O

G

V

DD(TX)  

n/a  

Antenna driver output  

V

SS(TX)  

Contactless transmitter ground. Must be  

connected to ground.  

TX1  

21  

22  

G8  

–

O

P

V

DD(TX)  

Antenna driver output  

TVDD_IN2  

Must be connected to V

DD(TX)

and  

TVDD_IN. VFBGA package: internally  

connected.  

ANT1  

ANT2  

V

DD(HF)  

V

DD(A)  

23  

24  

25  

26  

F7  

E7  

D6  

D7  

P

P

P

P

n/a  

n/a  

n/a  

n/a  

Antenna connection for wake-up  

Antenna connection for wake-up  

Monitor rectifier output voltage  

Analog supply voltage. Connect to  

V

DD(D)  

.

V

DD  

27  

28  

–

Must be connected to AVDD and DVDD.  

VFBGA package: internally connected.  

V

BAT  

E8  

P

n/a  

Battery supply voltage. Must be  

connected to V

BAT2  

Oscillator output  

PLL input  

.

XTAL2  

29  

30  

31  

D8  

C8  

C7  

O

I

V

DD(D)  

V

DD(D)  

n/a  

NFC_CLK_XTAL1  

V

DD(D)  

P

Digital supply voltage for decoupling.  

Must be connected to V

DD

and V

DD(A)  

.

n.c.  

32  

33  

34  

35  

36  

37  

–

n.c.  

–

n.c.  

–

n.c.  

–

n.c.  

–

DCDC_EN  

A2  

O

V

DD(PAD)

External DC-DC enable request on  

V

DD(PAD)  

i.c.  

38  

B2  

A1  

B1  

–

To

b

e left open.  

WKUP_REQ  

CLK_REQ  

V

SS  

39  

I

V

DD(PAD)

Wake-up request when in standby  

V

DD(PAD)

Clock request pin  

40  

O

G

Center Pad  

n/a  

Pad ground. Must be connected to  

ground.  

i.c.  

i.c.  

–

–

A3  

A4  

To

b

e left open.  

Must be connected to ground.  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

Table 7.ꢀPN7160 pin description

…continued  

Symbol  

Pin  

Pin  

Type

Refer  

Description  

HVQFN40  

VFBGA64  

i.c.  

–

–

–

–

–

–

–

–

–

–

–

–

–

–

A5  

A6  

A7  

A8  

B3  

B4  

B5  

B6  

B7  

B8  

C2  

C4  

C5  

C6  

To

b

e left open.  

To

b

e left open.  

Must be connected to ground.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

i.c.  

i.c.  

i.c.  

i.c.  

n.c.  

n.c.  

i.c.  

i.c.  

i.c.  

i.c.  

n.c.  

n.c.  

V

SS(D)  

G

n/a  

Digital ground supply voltage. Must be  

connected to ground.  

n.c.  

–

–

–

–

–

–

–

–

–

–

–

–

D4  

D5  

E4  

E5  

E6  

F1  

F2  

F3  

F4  

F5  

F6  

F8  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

To

b

e left open.  

n.c.  

n.c.  

n.c.  

n.c.  

i.c.  

i.c.  

i.c.  

n.c.  

n.c.  

n.c.  

TX_PWR_REQ  

O

V

DD(D)  

External TX power supply request on  

V

DD(D)  

i.c.  

–

–

–

–

–

–

G1  

G2  

G4  

G5  

G6  

H2  

Must be connected to ground.  

To

b

e left open.  

i.c.  

n.c.  

To

b

e left open.  

V

SS(A)  

V

SS(A)  

i.c.  

G

G

n/a  

n/a  

Analog ground supply voltage  

Analog ground supply voltage  

To

b

e left open.  

[1] P

 

= power supply; G = ground; I = input; O = output; I/O = input/output  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

11 Functional

 

description  

PN7160 can be connected on a host controller through different physical interfaces (I

2

C-bus and SPI-bus). The  

logical interface towards the host controller is NCI-compliant Ref.

with additional command set for NXP-  

specific product features. This IC is fully user controllable by the firmware interface described in Ref.

.  

Moreover, PN7160 provides flexible and integrated power management unit in order to preserve energy  

supporting Power Off mode.  

APPLICATION  

PROCESSOR  

Host interface  

EXTERNAL SUPPLIES  

NFCC  

AND CLOCK  

ANTENNA  

M

A

TCHING  

aaa-041132  

Figure 7.ꢀPN7160 connection in mobile system  

11.1 System

 

modes  

11.1.1 System

 

power modes  

4 power modes are specified: Full power mode, Autonomous mode, Low-power mode and Power Off mode.  

Table 8.ꢀSystem power modes description  

System power mode  

Full power mode  

Description  

The battery supply (V

BAT

) as well as the pad supply (V

DD(PAD)

) are available  

Autonomous mode  

The battery supply (V

BAT

) as well as the pad supply (V

DD(PAD)

) are available. Via a SW  

command the host sets the NFC controller in autonomous mode (AutoMode bit is set). In  

that power mode, the NFC controller will not send any command or signal over V

DD(PAD)  

connected pins.  

In case of reset via VEN pin the AutoMode bit value is kept unchanged.  

This mode is useful to present an NDEF message in Card Emulation mode although the  

main system is shut down.  

Low-power mode  

Power Off mode  

The battery supply (V

BAT

) is available but the pad supply (V

DD(PAD)

) is not available. No  

host communication is available.  

The system is not supplied from any source or the system is kept Hard Power Down  

(HPD)  

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Near Field Communication (NFC) controller  

AutoMode = 1  

Autonomous mode  

Full power mode  

= Off]  

AutoMode = 0  

[V  

[V  

= Off]  

DD(PAD)  

DD(PAD)  

[V  

= On]  

DD(PAD)  

[V  

DD(PAD)  

= On]  

[V  

= On && V  

= On  

DD(PAD)  

B

A

T  

Low-power mode  

VEN = On]  

[V  

= Off || VEN = Off]  

BAT  

[V  

= On && V  

DD(PAD)  

= Off  

B

A

T  

VEN = On]  

[V  

= Off || VEN = Off]  

BAT  

[V  

= Off || VEN = Off]  

(1)  

BAT  

Power Off mode  

[AutoMode = 1

 

&& VEN = On]  

[VEN = Off]  

aaa-022797  

1. When

 

V

BAT

goes OF

F

,

A

utoMode = 0.  

Figure 8.ꢀSystem power mode diagram  

summarizes the system power mode of the PN7160 depending on the status of the external supplies  

available in the system:  

Table 9.ꢀSystem power modes configuration  

V

BAT  

Off  

V

DD(PAD)  

VEN  

X

AutoMode bit  

Power mode  

X

X

X

0

Power Off mode  

Power Off mode  

Full power mode  

Autonomous mode  

Low-power mode  

On  

X

Off  

On  

On  

On  

On  

On  

On  

Off  

On  

1

On  

X

Depending on power modes, some application states are limited:  

Table 10.ꢀSystem power modes description  

System power mode  

Allowed communication modes  

not applicable  

Power Off mode  

Low-power mode  

Autonomous mode  

Card Emulation only  

Full power mode  

Reader/Writer, Card Emulation, P2P modes  

11.1.2 PN7160

 

power states  

Next to system power modes defined by the status of the power supplies, the power states include the logical  

status of the system. Thus extend the power modes.  

3 power states are specified: Hard Power Down (HPD), Standby, Active.  

Table 11.ꢀPN7160 power states  

Power state name  

Description  

Hard Power Down  

The PN7160 is supplied by V

BAT

within its operating range and PN7160 is kept in Hard Power  

Down (VEN voltage is kept low by host or SW programming) to have the minimum power  

consumption. The system mode is in Power Off.  

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Near Field Communication (NFC) controller  

Table 11.ꢀPN7160 power states

…continued  

Power state name  

Description  

Standby  

The PN7160 is supplied by V

BAT

within its operating range, VEN voltage is high (by host or SW  

programming) and minimum part of PN7160 is kept supplied to enable configured wake-up  

sources which allow to switch to Active state; RF field, Host interface (if V

DD(PAD)

is high). The  

system mode is Low-power mode or Full power mode.  

Active  

The PN7160 is supplied by V

BAT

within its operating range, VEN voltage is high (by host or SW  

programming), V

DD(PAD)

is high and the PN7160 internal blocks are supplied. 3 sub-modes are  

defined: Idle, Listener and Poller. The system mode is Full power mode.  

At application level, the PN7160 will continuously switch between different states to optimize the current  

consumption (polling loop mode). Refer to

for targeted current consumption in here described states.  

The PN7160 is designed to allow the host controller to have full control over its functional states.  

11.1.2.1 Hard

 

Power Down (HPD) state  

The Hard Power Down state is entered when V

DD(PAD)

and V

BAT

are high by setting VEN voltage < 0.4

V

.

A

s  

these signals are under host control, the PN7160 has no influence on entering or exiting this state.  

11.1.2.2 Standby

 

state  

Active state is PN7160’s default state after boot sequence in order to allow a quick configuration of PN7160. It is  

recommended to change the default state to Standby state after first boot in order to save power. PN7160 can  

switch to Standby state autonomously (if configured by host). This state is independent of the V

DD(PAD)

value.  

In this state, PN7160 most blocks including CPU are disconnected from power supply. Number of wake-up  

sources exist to put PN7160 into Active state (all host-related wake-up events imply that V

DD(PAD)

is available):  

•

Host interface wake-up event (I

2

C-bus, SPI-bus)  

•

Host interface wake-up via WKUP_REQ pin  

•

Antenna RF level detector  

•

Internal timer event when using polling loop (370 kHz Low-power oscillator is enabled)  

If wake-up event occurs, PN7160 will switch to Active state. Any further operation depends on software  

configuration and/or wake-up source.  

11.1.2.3 Active

 

state  

Within the Active state, the system is acting as an NFC device. The device can be in 3 different power states:  

Idle, Listener and Poller.  

Table 12.ꢀFunctional modes in active state  

Functional modes  

Description  

Idle  

the PN7160 is active and host interface communication is on going. The RF interface is not  

activated. If Standby state is de-activated PN7160 stays in Idle mode even when no host  

communication.  

Listener  

Poller  

the PN7160 is active and is listening to external device. The RF interface is activated.  

the PN7160 is active and is in Poller mode. It polls external device. The RF interface is  

activated.  

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Poller mode  

PN7160_PN7161  

Near Field Communication (NFC) controller  

In this mode, PN7160 is acting as Reader/Writer or NFC Initiator, searching for or communicating with passive  

tags or NFC target. Once RF communication has ended, PN7160 will switch to Idle mode or Standby state to  

save energy. Poller mode shall be used with 2.8 V < V

BAT

< 5.5 V and VEN voltage > 1.1

V

.

P

oller mode shall  

not be used with V

BAT

< 2.8

V

.

V

DD(PAD)

is within its operational range (see

).  

Listener mode  

In this mode, PN7160 is acting as a card or as an NFC

T

a

rget. Listener mode shall be used with 2.8 V < V

BAT  

< 5.5 V and VEN voltage > 1.1

V

.

O

nce RF communication has ended, PN7160 will switch to Idle mode or  

Standby state to save energy.  

11.1.2.4 Polling

 

loop  

The polling loop will sequentially set PN7160 in different power states (Active or Standby). All RF technologies  

supported by PN7160 can be independently enabled within this polling loop.  

There are 2 main phases in the polling loop:  

•

Listening phase. The PN7160 can be in Standby power state or Idle mode (called pause in

; no  

communication is on-going) or Listener mode (called Emulation in

; card / target communication is  

started)  

•

Polling phase. The PN7160 is in Poller mode  

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Near Field Communication (NFC) controller  

Listening phase  

Emulation  

Pause  

Type A  

Type B  

Type F  

@424  

Type F  

@212  

ISO15693  

Polling phase  

aaa-016741  

Figure 9.ꢀPolling loop: all phases enabled  

In Listening phase when no RF field PN7160 is in Standby state if enabled (otherwise it is Idle mode) and is in  

Listener mode (Emulation) when RF field is detected. When in Polling phase, PN7160 goes to Poller mode.  

To

f

urther decrease the power consumption when running the polling loop, PN7160 features a low-power RF  

polling. When PN7160 is in Polling phase instead of sending regularly RF command PN7160 senses with  

a short RF field duration if there is any NFC

T

a

rget or card/tag present. If yes, then it goes back to standard  

polling loop. With 500 ms (configurable duration, see Ref.

) listening phase duration, the average power  

consumption is around 100 μA depending on RF matching conditions.  

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Near Field Communication (NFC) controller  

Listening phase  

Emulation  

Pause  

Polling phase  

aaa-016743  

Figure 10.ꢀPolling loop: low-power RF polling  

Detailed description of polling loop configuration options is given in Ref.

.  

11.2 Host

 

interfaces

PN7160 provides the support of the following host interfaces:  

•

I

2

C-bus

T

a

rget Interface, up to 3.4 MBaud  

•

SPI-bus

T

a

rget Interface, up to 7 MBaud  

Only one host interface can be active at a time, as the pins are shared for all interfaces.  

The selection between interfaces is fused during IC manufacturing so that different ordering numbers for the  

I

2

C-bus and SPI-bus version are in place.  

The host interfaces are woken-up in the following way:  

•

wake-up with WKUP_REQ input pin  

•

I

2

C-bus: wake-up on I

2

C-bus address  

•

SPI-bus: transition of NSS serial  

•

data received on RX line  

2

Updated the terms “Master/Slave” to “Controller/

T

a

rget” to align with the recommendation of the NXP – I2C standards organization.  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

To

e

nable and ensure data flow control between PN7160 and host controller, additionally a dedicated interrupt  

line IRQ is provided which Active state is programmable. See Ref.

for more information.  

11.2.1 I

2

C-bus interface

The I

2

C-bus interface implements a target I

2

C-bus interface with integrated shift register, shift timing generation  

and target address recognition.  

I

2

C-bus Standard mode (100 kHz SCL), Fast mode (400 kHz SCL) and High-speed mode (3.4 MHz SCL) are  

supported.  

The main hardware characteristics of the I

2

C-bus module are:  

•

Support target I

2

C-bus  

•

Standard, Fast and High-speed modes supported  

•

Wake-up of PN7160 on its address only  

•

Serial clock synchronization can be used by PN7160 as a handshake mechanism to suspend and resume  

serial transfer (clock stretching)  

The I

2

C-bus interface module meets the I

2

C-bus specification Ref.

except General call, 10 bit addressing  

and Fast mode Plus (Fm+).  

11.2.1.1 I

2

C-bus configuration  

The I

2

C-bus interface shares four pins with SPI-bus interface also supported by PN7160. When I

2

C-bus is  

configured in EEPROM settings, functionality of the interface pins changes as described in

.  

Table 13.ꢀFunctionality for I

2

C-bus interface  

Pin name  

HIF1  

Functionality  

I

2

C-bus address 0  

I

2

C-bus address 1  

I

2

C-bus data line  

I

2

C-bus clock line  

HIF2  

HIF3

HIF4

[1] HIF3

 

and HIF4 are not fail-safe and V

DD(pad)

shall always be available when using the SCL and SDA lines connected to these pins.  

PN7160 supports 7-bit addressing mode. Selection of the I

2

C-bus address is done by 2-pin configurations on  

top of a fixed binary header: 0, 1, 0, 1, 0, HIF2, HIF1, R/W.  

Table 14.ꢀI

2

C-bus interface addressing  

HIF2  

HIF1  

I

2

C-bus address  

(R/W = 0, write)  

I

2

C-bus address  

(R/W = 1, read)  

0

0

1

1

0

1

0

1

0x50  

0x52  

0x54  

0x56  

0x51  

0x53  

0x55  

0x57  

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Near Field Communication (NFC) controller  

11.2.2 Serial

 

Peripheral Interface bus (SPI-bus)

11.2.2.1 Features  

•

Synchronous, Serial, Full-Duplex communication, 7 MHz maximum  

•

T

a

rget mode  

11.2.2.2 SPI-bus

 

configuration options

In order to select SPI-bus interface for host communication, some EEPROM settings are programmed during  

production.  

The CPOL/CPHA EEPROM settings are fixed as specified in

.  

The selection between interfaces is fused during IC manufacturing so that different ordering numbers for the  

SPI-bus version.  

Table 15.ꢀSPI-bus configuration  

Connection  

CPHA switch: Clock PHAse: defines the sampling edge of MOSI data  

•

CPHA = 0: data are sampled on MOSI on the odd clock edges of SCK after NSS goes low  

CPOL switch: Clock POLarity  

•

IFSEL1 = 0: the clock is idle low and the first valid edge of SCK will be a rising one  

The SPI-bus interface shares 4 pins with the I

2

C-bus interface. During production of the device, the interface  

is fixed to SPI or I²C and cannot be changed later. The functionality of the interface pins in SPI configuration is  

described in

.  

Table 16.ꢀFunctionality for SPI-bus interface  

Pin name  

HIF1  

Functionality  

NSS (Not

T

a

rget Select)  

MOSI (Controller Out

T

a

rget In)  

MISO (Controller In

T

a

rget Out)  

SCK (Serial Clock)  

HIF2  

HIF3  

HIF4  

11.2.2.3 SPI-bus

 

functional description

When a controller device transmits data to PN7160 (target device) via the MOSI line, PN7160 responds by  

sending data to the controller device via the controllers MISO line. This implies full-duplex transmission with  

both data out and data in synchronized with the same clock signal.  

PN7160 starts sampling when receiving a logic low at pin NSS and the clock at input pin SCK. Thus, PN7160 is  

synchronized with the controller. Data from the controller is received serially at the target MOSI line and loads  

the 8-bit shift register. After the 8-bit shift register is loaded, its data is transferred to the read buffer. During a  

write cycle, data is written into the shift register, then PN7160 waits for a clock train from the controller to shift  

the data out on the targets MISO line.  

•

Controller In

T

a

rget Out (MISO)  

The MISO line is configured as an input in a controller device and as an output in a target device. It is used to  

transfer data from the target to the controller, with the most significant bit sent first. The MISO line of a target  

device should be placed in the high impedance state if the target is not selected.  

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Near Field Communication (NFC) controller  

•

Controller Out

T

a

rget In (MOSI)  

The MOSI line is configured as an output in a controller device and as an input in a target device. It is used to  

transfer data from the controller to a target, with the Most Significant Bit (MSB) sent first.  

•

Serial Clock (SCK)  

The serial clock is used to synchronize data movement both in and out of the device through its MOSI and  

MISO lines. The controller and target devices are capable of exchanging a byte of information during a  

sequence of eight clock cycles. Since the controller device generates SCK, this line becomes an input on a  

target device and an output at the controller device.  

•

Not

T

a

rget Select (NSS)  

The target select input line is used to select a target device. It has to be low prior to data transactions and  

must stay low of the duration of the transaction. The NSS line on controller side must be tied high.  

Both controller and target devices must operate with the same timing. The controller device always places data  

on the MOSI line a half cycle before the clock edge SCK, in order for the target device to latch the data.  

For more information about the SPI-bus functionality, see Ref.

.  

11.3 PN7160

 

clock concept  

There are 4 different clock sources in PN7160:  

•

27.12 MHz clock coming either/or from:  

–

Internal oscillator for 27.12 MHz crystal connection on NFC_CLK_XTAL1 and XTAL2 pins  

–

External reference clock on pin NFC_CLK_XTAL1. It is internally forwarded to an integrated PLL which  

includes a 1 GHz VCO.  

•

13.56 MHz RF clock recovered from RF field  

•

Low-power oscillator 40 MHz  

•

Low-power oscillator 370 kHz  

11.3.1 27.12

 

MHz quartz oscillator  

When enabled, the 27.12 MHz quartz oscillator applied to PN7160 is the time reference for the RF front end  

when PN7160 is behaving in Reader mode or NFCIP-1 Initiator.  

Therefore stability of the clock frequency is an important factor for reliable operation. It is recommended to  

adopt the circuit shown in

.  

NFCC  

NFC_CLK_XTAL1  

X

T

AL2  

crystal  

27.12 MHz  

c

c

aaa-041133  

Figure 11.ꢀ27.12 MHz crystal oscillator connection  

describes the levels of accuracy and stability required on the crystal.  

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Near Field Communication (NFC) controller  

Table 17.ꢀCrystal requirements  

Symbol  

Parameter  

Conditions  

Min  

Typ  

Max  

Unit  

f

xtal  

crystal frequency  

ISO/IEC, FCC and FeliCa  

global compliancy  

–

27.12  

–

MHz  

Δf

xtal  

ESR  

C

L  

crystal frequency accuracy  

equivalent series resistance  

load capacitance  

full operating range  

-50  

–

+50  

100  

–

ppm  

Ω

–

–

–

50  

10  

–

pF  

P

xtal  

crystal power dissipation  

100  

μW  

[1] This

 

requirement is according to FCC regulations (± 100 ppm) and FeliCa global (± 50 ppm) requirements.

T

o

m

eet only ISO/IEC 14443 and ISO/IEC  

18092, then ± 14 kHz apply which is equivalent to ± 516 ppm.  

11.3.2 Integrated

 

PLL to make use of external clock  

When enabled, the PLL is designed to generate a low noise 27.12 MHz from an input clock 19.2 MHz, 26 MHz,  

32 MHz, 38.4 MHz and 48 MHz.  

The 27.12 MHz of the PLL is used as the time reference for the RF front end.  

The input clock on NFC_CLK_XTAL1 shall comply with the.following phase noise requirements for the following  

input frequency: 19.2 MHz, 26 MHz, 32 MHz, 38.4 MHz and 48 MHz:  

dBc/Hz  

-20dBc/decade  

input reference  

noise floor  

-140 dBc/Hz  

Hz  

input reference noise corner  

50 kHz  

aaa-026327  

Figure 12.ꢀInput reference phase noise characteristics  

This phase noise is equivalent to an RMS jitter of 6.23 ps from 10 Hz to 1 MHz. For configuration of input  

frequency, refer to Ref.

. There are 7 pre programmed and validated frequencies for the PLL: 19.2 MHz, 26  

MHz, 32 MHz, 38.4 MHz and 48 MHz.  

Table 18.ꢀPLL input requirements  

Coupling: single-ended, AC coupling;  

Symbol  

Parameter  

Conditions  

Min  

Typ  

19.2  

26  

Max  

Unit  

MHz  

MHz  

MHz  

MHz  

MHz  

f

clk  

clock frequency  

ISO/IEC, FCC and FeliCa global  

compliancy  

–

–

–

–

–

–

–

–

–

–

32  

38.4  

48  

PN7160_PN7161  

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Table 18.ꢀPLL input requirements

…continued  

Coupling: single-ended, AC coupling;  

Symbol  

Parameter  

Conditions  

Min  

Typ  

Max  

Unit  

f

i(ref)acc  

reference input frequency  

accuracy  

full operating range; frequencies  

typical values: 19.2 MHz, 26 MHz,  

32 MHz, 38.4 MHz and 48 MHz  

-20  

–

+20  

ppm  

φ

n  

phase noise  

input noise floor at 50 kHz  

-140  

–

–

dB/Hz  

Sinusoidal shape  

V

i(p-p)  

V

i(clk)  

peak-to-peak input voltage  

clock input voltage  

0.2  

0

–

–

1.8  

1.8  

V

V

Square shape  

V

i(clk)

clock input voltage  

0

–

1.8  

V

[1] This

 

requirement is according to FCC regulations (± 100 ppm) and FeliCa global (± 50 ppm) requirements.

T

o

m

eet only ISO/IEC 14443 and ISO/IEC  

18092, then ± 7 kHz apply which is equivalent to ± 516 ppm.  

[2] Overshoot

 

and undershoot shall not exceed 10%.  

For detailed description of clock request mechanisms, refer to Ref.

and Ref.

.  

11.3.3 Low-power

 

40 MHz ± 2.5 % oscillator  

Low-power 40 MHz ± 2.5 % oscillator is used as system clock of the system.  

Output clock 40 MHz is used by default to clock the system.  

11.3.4 Low-power

 

370 kHz oscillator  

A Low Frequency Oscillator (LFO) is implemented to drive a counter (WUC) waking-up PN7160 from Standby  

state. This allows implementation of low-power reader polling loop at application level.  

Moreover, this 370 kHz is used as the reference clock for write access to EEPROM memory.  

11.4 Power

 

concept  

11.4.1 PMU

 

functional description  

The Power Management Unit of PN7160 generates internal supplies required by PN7160 out of V

BAT

and  

V

DD(UP)

input supply voltages:  

•

V

DDA

: analog output supply voltage. It must be connected to V

DDD  

.

•

V

DDD

: digital input supply voltage. It is internally connected to the output of the DSLDO V

DD  

.

•

V

DD(TX)

: output supply voltage for the transmitter. It is internally connected to the transmitter input supply  

voltage  

The

describes the main blocks available in PMU:  

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V

V

V

DDA  

BAT  

DDD  

V

DD  

V

V

DD(UP)  

DD(TX)  

TXLDO  

DSLDO  

TVDD_IN  

BANDGAP  

DIE  

NFCC  

aaa-041134  

Figure 13.ꢀPMU functional diagram  

11.4.2 DSLDO:

 

Dual Supply LDO  

The input pin of the DSLDO regulator is V

BAT  

.

The output of this regulator (V

DD

) is internally connected to supply the internal digital blocks which are on V

DDD  

.

It must be externally de-coupled and V

DDD

must be connected to V

DDA  

.

11.4.3 TXLDO  

Transmitter voltage is generated by internal LDO (V

DD(TX)

).  

This TXLDO allows a maximum continuous current load up to 250 mA in order to support ISO/IEC 14443 and  

NFC Forum standard compliant operations.  

The Low Drop Out regulator has been designed to reject the noise which could interfere with the RF  

communication.  

Table 19.ꢀTXLDO  

Symbol  

Parameter  

Conditions  

Min  

Typ  

Max  

Unit  

V

DD(TXLDO)  

drop TXLDO supply  

voltage  

V

DD(UP)

= 5.3 V; Transmitter current =  

250 mA  

–

–

0.3  

V

(drop)  

The regulator has been designed to work in 2 modes:  

11.4.3.1 Configuration

 

1: the battery voltage is directly used to generate the RF field  

The input supply of the regulator is directly the V

BAT

voltage which is connected to V

DD(UP)

the input of the  

TXLDO.  

The output is called V

DD(TX)  

.

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V

V

DD(UP)  

BATTERY  

V

BAT  

NFCC  

DD(TX)  

aaa-041135  

Figure 14.ꢀV

DD(UP)

= V

BAT  

V

BAT

acceptable range depends on communication modes to be covered (see

)  

The V

DD(TX)

value is programmable and shall be chosen according to the minimum targeted VBAT value for  

which reader and card modes shall work: VTHRESHOLD.  

The TXLDO output voltage is then given by:  

shows V

DD(TX)

offset disabled behavior for both cases of V

DD(TX)

programmed for 3.0

V

,

3

.3 V or 3.6  

V.  

5.0 V  

3.6 V  

V

~ 1 Ω * load  

DD(TXLDO)(drop)  

3.3 V  

3.0 V  

2.8 V  

4.5 V  

3.6 V  

3.3 V  

3.0 V  

2.8 V  

aaa-025682  

Figure 15.ꢀV

DD(TX)

behavior when supplied from V

BAT  

In Standby state, whatever V

THRESHOLD

value is configured, V

DD(TX)

is regulated at 2.5

V

.  

shows the case where the PN7160 is in standby state.  

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V

BAT  

2.5 V  

2.5 V  

aaa-009463  

Figure 16.ꢀV

DD(TX)

behavior when PN7160 is in Standby state  

11.4.3.2 Configuration

 

2: an extra external voltage is used to generate the RF field  

TXLDO has also the possibility to generate V

DD(TX)

up to 5.25 V in case the supply of this regulator is an  

external supply.  

V

DD(UP)  

EXTERNAL 5 V  

BATTERY  

V

BAT  

NFCC  

V

DD(TX)  

aaa-041136  

Figure 17.ꢀV

DD(UP)

up to 5.8

V

,

V

BAT

up to 5.5 V  

Minimum V

DD(UP)

and V

BAT

acceptable values depend on communication modes to be covered (see

)  

The TXLDO output voltage is then given by:  

shows the behavior of V

DD(TX)

depending on V

DD(UP)

value.  

V

5.5 V  

DD(UP)  

4.75 V  

4.5 V  

V

DD(TX)  

V

~ 1 Ω * load  

DD(TXLDO)(drop)  

aaa-025683  

Figure 18.ꢀV

DD(TX)

behavior when PN7160 is supply using external supply on V

DD(UP)  

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Near Field Communication (NFC) controller  

In Standby state, whatever V

THRESHOLD

is configured, V

DD(TX)

is regulated at 2.5 V as illustrated by

.  

11.4.3.3 TXLDO

 

limiter  

The TXLDO includes a current limiter to avoid too high current within TX1 and TX2.  

The current limiter block compares an image of the TXLDO output current to a reference, when the reference is  

reached the output current gets limited.  

The limiting current is 300 mA ± 30 mA, above the specified maximum current allowed for RF operation (250  

mA).  

11.4.3.4 TXLDO:

 

configuration  

Table 20.ꢀConfigurations using TXLDO  

PN7160 power state  

TXLDO config.  

configuration 1  

configuration 2  

Mode  

V

DD(TX)  

2.7 V/3 V/3.3 V/3.6 V

Active mode  

Full-power  

Full-power  

2.7 V/3 V/3.3 V/3.6 V/3.9 V/4.2 V/4.5 V/4.7  

V/4.75 V/5 V/5.25 V

Standby  

configuration 1 and  

configuration 2  

Low-power  

Power-off  

2.5 V  

Hard-Power down  

configuration 1 and  

configuration 2  

High impedance  

[1] For

 

proper operation, the V

DD(TX)

voltage value set shall be below the V

DD(UP)

– 0.3 V value. The maximum V

DD(UP)

value is 5.8 V in configuration 2. In  

configuration 1, the voltage is given by the battery then the higher voltages might not be usable.  

When using an external DC-to-DC with pass-through functionality, the signal TX_PWR_REQ is used for control  

purpose. The DC-to-DC will be in pass-through mode except when high transmitter power is required (by default  

when RF emission or RF field present).  

Note:

the signal TX_PWR_REQ is not available on the HVQFN package variant.  

Alternatively the signal DCDC_EN can be used for the same purpose. This signal is available on both package  

variants. HVQFN and VFBGA.  

11.4.4 Very

 

low-power RF field detector  

A very specific use case is the RF field detection when the NFCC is in Power Off mode. In this scenario, the  

NFCC should detect the presence of an external magnetic field and notify the host system about its presence.  

shows the internal rectifier circuit. The circuit is built up by the input switches SW1 and SW2 which  

can disconnect the rectifier from the antenna by creating a short to ground. The rectifier itself is followed by a  

limiter.  

ANT1  

rectifier  

SW1  

SW2  

V

DD(HF)  

C

vdhf  

limiter  

ANT2  

aaa-022801  

Figure 19.ꢀInternal rectifier circuit  

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11.5 Reset

 

and download concept  

11.5.1 Resetting

 

PN7160  

To

e

nter reset, the V

EN

voltage shall be set to low (this is also the Hard Power Down state):  

Reset means resetting the embedded FW execution and the registers values to their default values. Parts of  

these default values are defined from EEPROM data loaded values, others are hardware defined. See Ref.

to know which ones are accessible to tune PN7160 to the application environment.  

To

g

et out of reset:  

•

Pulling VEN voltage high with V

BAT

within its operating range  

shows reset done via VEN pin.  

V

BAT  

V

DD(PAD)  

host  

communication  

possible  

V

EN  

t

t

boot  

WL(VEN)  

aaa-024833  

Figure 20.ꢀResetting PN7160 via VEN pin  

See

for the timings values.  

11.5.2 Power-up

 

sequences  

PN7160 allows V

BAT

and V

DD(PAD)

to be set up independently, therefore different power-up sequences have to  

be considered.  

In all cases, host communication with PN7160 will only be possible after one defined amount of time from the  

different supply sequence setup and VEN reset pin.  

11.5.2.1 V

BAT

is set up before V

DD(PAD)  

This is at least the case when V

BAT

pin is directly connected to the battery and when PN7160 V

BAT

is always  

supplied as soon the system is supplied.  

As VEN pin is referred to V

BAT

pin, V

EN

shall go high after V

BAT

has been set.  

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V

BAT  

V

DD(PAD)  

interface selection  

t

t

t(VDDPAD-VEN)  

boot  

host  

communication  

possible  

V

EN  

aaa-013871  

Figure 21.ꢀV

BAT

is set up before V

DD(PAD)  

See

and

for the timings values.  

11.5.2.2 V

DD(PAD)

and V

BAT

are set up at the same time  

This is the case, when V

BAT

pin is connected to a PMU/regulator which also supply V

DD(PAD)  

.

V

BAT  

t

t(VBAT-VEN)  

V

DD(PAD)  

t

boot  

host  

communication  

possible  

V

EN  

aaa-013872  

Figure 22.ꢀV

DD(PAD)

and V

BAT

are set up in the same time  

See

and

for the timings values.  

11.5.2.3 PN7160

 

has been enabled before V

DD(PAD)

is set up or before V

DD(PAD)

has been cut-off  

This can be the case when V

BAT

pin is directly connected to the battery and when V

DD(PAD)

is generated from a  

PMU. When the battery voltage is too low, then the PMU might no more be able to generate V

DD(PAD)

. When the  

device gets charged again, then V

DD(PAD)

is set up again.  

As the pins to select the interface are biased from V

DD(PAD)

, when V

DD(PAD)

disappears the pins might not be  

correctly biased internally and the information might be lost. Therefore it is required to make the IC boot after  

V

DD(PAD)

is set up again.  

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Near Field Communication (NFC) controller  

V

BAT  

V

DD(PAD)  

interface selection  

t

t

t(VDD

P

A

D-VEN)  

boot  

host  

communication  

possible  

V

t

WL(VEN)  

EN  

aaa-024841  

Figure 23.ꢀV

DD(PAD)

is set up or cut-off after PN7160 has been enabled  

See

and

for the timings values.  

11.5.3 Power-down

 

sequences  

During power-down sequence, V

EN

shall always be set low before V

DD(PAD)

is shut down.  

V

BAT  

V

EN  

t

WL(VEN)  

V

DD(PAD)  

aaa-024910  

Figure 24.ꢀPN7160 power-down sequence  

See

for the timings values.  

11.5.4 Download

 

mode  

PN7160 offers the possibility to download EEPROM with upgrades using the host interface commands, see Ref.  

for more details.  

To

e

nter this mode, the pin DWL_REQ shall be pulled to V

DD(PAD)

before reset via VEN pin is done.  

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Near Field Communication (NFC) controller  

V

BAT  

V

DD(PAD)  

DWL_REQ  

t

t

boot  

t(DWL_REQ-VEN)  

t

V

WL(VEN)  

EN  

download  

possible  

aaa-024842  

Figure 25.ꢀPN7160 download mode sequence  

See

and

for the timings values.  

11.6 Contactless

 

Interface Unit  

PN7160 supports various communication modes at different transfer speeds and modulation schemes. The  

following chapters give more detailed overview of selected communication modes.  

Remark:

all indicated modulation index and modes in this chapter are system parameters. This means that  

beside the IC settings a suitable antenna tuning is required to achieve the optimum performance.  

11.6.1 Reader/Writer

 

communication modes  

Generally 5 Reader/Writer communication modes are supported:  

•

PCD Reader/Writer for ISO/IEC 14443A/MIFARE (NFC Forum Types 2 and 4

T

a

gs)  

•

PCD Reader/Writer for NFC Forum Type 1

T

a

g  

•

PCD Reader/Writer for NFC Forum Type 3

T

a

g  

•

PCD Reader/Writer for ISO/IEC 14443B (NFC Forum Type 4

T

a

g)  

•

VCD Reader/Writer for NFC Forum Type 5

T

a

g  

11.6.1.1 R/W

 

mode for NFC Forum Type 1 and 2 Tags and Type 4 Tag type A  

The R/W mode for NFC Forum Type 1

T

a

g (T1T), Type 2

T

a

g (T2T) and Type 4

T

a

g type A (T4T) is the general  

reader to card communication scheme according to the ISO/IEC 14443A specification.  

describes the communication on a physical level, the communication table describes the physical  

parameters (the numbers take the antenna effect on modulation depth for higher data rates).  

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PCD to PICC  

100 % ASK at 106 kbit/s  

> 25 % ASK at 212, 424 or 848 kbit/s  

Modified Miller coded  

NFCC  

PICC (Card)  

PICC to PCD,  

subcarrier load modulation  

Manchester coded at 106 kbit/s  

ISO/IEC 14443A – MIFARE

 

BPSK coded at 212, 424 or 848 kbit/s  

PCD mode  

ISO/IEC 14443A – MIFARE  

aaa-041137  

Figure 26.ꢀR/W mode for NFC Forum T1

T

,

T

2T and T4T type A communication diagram  

Table 21.ꢀCommunication overview for NFC Forum T1

T

,

T

2T and T4T type A R/W mode  

Communication  

direction  

ISO/IEC 14443A/

 

ISO/IEC 14443A higher transfer speeds  

MIFARE/  

NFC Forum T2T  

and T4T  

Transfer speed  

Bit length  

106 kbit/s  

212 kbit/s  

424 kbit/s  

848 kbit/s  

(128/13.56) μs  

(64/13.56) μs  

(32/13.56) μs  

(16/13.56) μs  

PN7160

→

PICC  

(data sent by PN7160 to a

 

modulation on  

100 % ASK  

> 25 % ASK  

> 25 % ASK  

> 25 % ASK  

card)  

PN7160 side  

bit coding  

Modified Miller  

Modified Miller  

Modified Miller  

Modified Miller  

PICC →

PN7160  

(data received by PN7160

 

modulation on  

subcarrier load  

modulation  

subcarrier load  

modulation  

subcarrier load  

modulation  

subcarrier load  

modulation  

from a card)  

PICC side  

subcarrier  

frequency  

13.56 MHz/16  

13.56 MHz/16  

13.56 MHz/16  

13.56 MHz/16  

bit coding  

Manchester  

BPSK  

BPSK  

BPSK  

The contactless coprocessor and the on-chip CPU of PN7160 handle the complete ISO/IEC 14443A/MIFARE  

RF-protocol, nevertheless a dedicated external host has to handle the application layer communication.  

11.6.1.2 R/W

 

mode for NFC Forum Type 3 Tag, FeliCa communication mode  

The R/W mode for NFC Forum Type 3

T

a

g (T3T) is the general Reader/Writer to card communication  

scheme according to the FeliCa specification.

describes the communication on a physical level, the  

communication overview describes the physical parameters.  

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PCD to PICC,  

8 – 12 % ASK at 212 or 424 kbits/s  

Manchester coded  

NFCC  

PICC (Card)  

PICC to PCD,  

load modulation  

Manchester coded at 212 or 424 kbits/s  

ISO/IEC 18092 – FeliCa  

PCD mode  

FeliCa card  

aaa-04

1

138  

Figure 27.ꢀR/W mode for NFC Forum T3T communication diagram  

Table 22.ꢀCommunication overview for NFC Forum T3T R/W mode, FeliCa communication mode  

Communication direction  

FeliCa  

FeliCa higher transfer speeds  

424 kbit/s  

Transfer speed  

Bit length  

212 kbit/s  

(64/13.56) μs  

(32/13.56) μs  

PN7160

→

PICC  

(data sent by PN7160 to a card)  

modulation on  

PN7160 side  

8 % – 12 % ASK  

Manchester  

8 % – 12 % ASK  

Manchester  

bit coding  

PICC →

PN7160  

(data received by PN7160 from a card)  

modulation on PICC

 

load modulation  

side  

load modulation  

subcarrier frequency

 

no subcarrier  

no subcarrier  

Manchester  

bit coding  

Manchester  

The contactless coprocessor of PN7160 and the on-chip CPU handle the FeliCa protocol. Nevertheless a  

dedicated external host has to handle the application layer communication.  

11.6.1.3 R/W

 

mode for NFC Forum type 4 Tag (T4T) type B  

The R/W mode for the NFC Forum Type 4

T

a

g of type B is the general reader to card communication scheme  

according to the ISO/IEC 14443B specification.

describes the communication on a physical level, the  

communication table describes the physical parameters.  

PCD to PICC,  

8 – 14 % ASK at 106, 212, 424 or 848 kbit/s  

NRZ coded  

NFCC  

PICC (Card)  

PICC to PCD,  

subcarrier load modulation  

BPSK coded at 106, 212, 424 or 848 kbit/s  

ISO/IEC 14443 Type B  

PCD mode  

ISO/IEC 14443 Type B  

aaa-04

1

139  

Figure 28.ꢀR/W mode for NFC forumT4T type B communication diagram  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

Table 23.ꢀCommunication overview for NFC Forum T4T type B R/W mode  

Communication  

direction  

ISO/IEC 14443B

 

ISO/IEC 14443B higher transfer speeds  

Transfer speed  

Bit length  

106 kbit/s  

212 kbit/s  

424 kbit/s  

848 kbit/s  

(128/13.56) μs  

(64/13.56) μs  

(32/13.56) μs  

(16/13.56) μs  

PN7160

→

PICC  

(data sent by PN7160 to a

 

modulation on  

8 % – 14 % ASK

 

8 % – 14 % ASK

 

8 % – 14 % ASK

 

8 % – 14 % ASK  

card)  

PN7160 side  

bit coding  

NRZ  

NRZ  

NRZ  

NRZ  

PICC →

PN7160  

(data received by PN7160

 

modulation on  

subcarrier load  

modulation  

subcarrier load  

modulation  

subcarrier load  

modulation  

subcarrier load  

modulation  

from a card)  

PICC side  

subcarrier  

frequency  

13.56 MHz/16  

13.56 MHz/16  

13.56 MHz/16  

13.56 MHz/16  

bit coding  

BPSK  

BPSK  

BPSK  

BPSK  

The contactless coprocessor and the on-chip CPU of PN7160 handles the complete ISO/IEC 14443B RF-  

protocol, nevertheless a dedicated external host has to handle the application layer communication.  

11.6.1.4 R/W

 

mode for NFC Forum Type 5 Tag  

The R/W mode for NFC Forum Type 5

T

a

g (T5T) is the general reader to card communication scheme  

according to the ISO/IEC 15693 specification. PN7160 communicates with VICC (Type 5

T

a

g) using only 26.48  

kbit/s with single subcarrier.  

PN7160 supports the commands as defined by the ETSI HCI (see Ref.

) and on top offers the inventory of  

the tags (anti-collision sequence) on its own.  

VCD to VICC,  

100 % ASK at 26.48 kbit/s  

pulse position coded  

NFCC  

Card  

(VICC/TAG)  

VICC to VCD,  

subcarrier load modulation  

Manchester coded at 26.48 kbit/s  

ISO/IEC 15693  

VCD mode  

ISO/IEC 15693  

aaa-041140  

Figure 29.ꢀR/W mode for NFC Forum T5T communication diagram  

shows the communication schemes used.  

The following communication scheme is possible.  

Table 24.ꢀCommunication overview for NFC Forum T5T R/W mode  

Communication direction  

PN7160

→

VICC  

(data sent by PN7160 to a tag)  

transfer speed  

26.48 kbit/s  

(512/13.56) μs  

100 % ASK  

bit length  

modulation on PN7160 side  

PN7160_PN7161  

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V

.

A

ll rights reserved.  

Product data sheet  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

Table 24.ꢀCommunication overview for NFC Forum T5T R/W mode

…continued  

Communication direction  

bit coding  

pulse position modulation 1 out of 4 mode  

VICC →

PN7160  

(data received by PN7160 from a tag)

 

transfer speed  

bit length  

26.48 kbit/s  

(512/13.56) μs  

modulation on VICC side  

subcarrier load modulation  

single subcarrier  

Manchester  

subcarrier frequency  

bit coding  

11.6.2 ISO/IEC

 

18092, Ecma 340 NFCIP-1 communication modes  

An NFCIP-1 communication takes place between 2 devices:  

•

NFC Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication.  

•

NFC

T

a

rget: responds to NFC Initiator command either in a load modulation scheme in Passive  

communication mode or using a self-generated and self-modulated RF field for Active communication mode.  

The NFCIP-1 communication differentiates between Active and Passive communication modes.  

•

Active communication mode means both the NFC Initiator and the NFC

T

a

rget are using their own RF field to  

transmit data  

•

Passive communication mode means that the NFC

T

a

rget answers to an NFC Initiator command in a load  

modulation scheme. The NFC Initiator is active in terms of generating the RF field.  

PN7160 supports the Active Initiator, Active

T

a

rget, Passive Initiator and Passive

T

a

rget communication modes  

at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard.  

BATTERY  

HOST  

BATTERY  

HOST  

NFCC  

NFCC  

initiator: active  

target: passive or active  

aaa-04

1

141  

Figure 30.ꢀNFCIP-1 communication mode  

The contactless coprocessor of PN7160 and the on-chip CPU handle NFCIP-1 protocol, for all communication  

modes and data rates, for both NFC Initiator and NFC

T

a

rget.  

Nevertheless a dedicated external host has to handle the application layer communication.  

11.6.2.1 Active

 

communication mode  

Active communication mode means both the NFC Initiator and the NFC

T

a

rget are using their own RF field to  

transmit data.  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

host  

host  

NFCC  

NFC Target  

NFC Initiator  

1. NFC Initiator starts the communication at selected transfer speed  

power  

power  

to generate  

the field  

for digital  

processing  

host  

host  

NFCC  

NFC Target  

NFC Initiator  

2. NFC Target answers at the same transfer speed  

power  

power  

for digital  

processing  

to generate  

the field  

aaa-041142  

Figure 31.ꢀActive communication mode  

gives an overview of the Active communication modes:  

Table 25.ꢀOverview for Active communication mode  

Communication direction  

NFC Initiator to NFC Target  

NFC Target to NFC Initiator  

ISO/IEC 18092, Ecma 340, NFCIP-1  

Baud rate  

Bit length  

106 kbit/s  

212 kbit/s  

424 kbit/s  

(32/13.56) μs  

(128/13.56) μs  

(64/13.56) μs  

modulation  

bit coding  

100 % ASK  

8 % – 30 % ASK

8 % – 30 % ASK

Manchester Manchester  

Modified Miller  

modulation  

bit coding  

100 % ASK  

Miller  

8 % – 30 % ASK

8 % – 30 % ASK

Manchester Manchester  

[1] This

 

modulation index range is according to NFCIP-1 standard. It might be that some NFC Forum type 3 cards does not withstand the full range as based  

on FeliCa range which is narrow (8 % to 14 % ASK).

T

o

a

djust the index, see

.  

11.6.2.2 Passive

 

communication mode  

Passive communication mode means that the NFC

T

a

rget answers to an NFC Initiator command in a load  

modulation scheme.  

PN7160_PN7161  

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PN7160_PN7161  

Near Field Communication (NFC) controller  

host  

host  

NFCC  

NFC Target  

NFC lnitiator