onsemi-2N6071BTG
| Part # | onsemi-2N6071BTG |
Download  | onsemi-2N6071BTG |
2N6071A/B Series
Preferred Device
Sensitive Gate
T
r
iacs
Silicon Bidirectional Thyristors
Designed primarily for full‐wave AC control applications, such as
light dimmers, motor controls, heating controls and power supplies; or
wherever full‐wave silicon gate controlled solid‐state devices are
needed. Triac type thyristors switch from a blocking to a conducting
state for either polarity of applied anode voltage with positive or
negative gate triggering.
TRIACS
4.0 A RMS, 200 – 600 V
Features
•
ăSensitive Gate Triggering Uniquely Compatible for Direct Coupling
to TTL, HTL, CMOS and Operational Amplifier Integrated Circuit
Logic Functions
MT2
MT1
•
ăGate Triggering:
4 Mode – 2N6071A, B; 2N6073A, B; 2N6075A, B
G
•
ăBlocking
V
o
ltages to 600 V
•
ăAll Diffused and Glass Passivated Junctions for Greater Parameter
Uniformity and Stability
•
ăSmall, Rugged, Thermopad Construction for Low Thermal
Resistance, High Heat Dissipation and Durability
•
ăDevice Marking: Device Type, e.g., 2N6071A, Date Code
REAR VIEW
SHOW TAB
TO-225
CASE 077
STYLE 5
3
2
1
MARKING DIAGRAM
YWW
2N
607xyG
1. Cathode
2. Anode
3. Gate
x
= 1, 3, 5
= A, B
=
Y
e
ar
y
Y
WW
G
= Work Week
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Preferred
devices are recommended choices for future use
and best overall value.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting
T
e
chniques
Reference Manual, SOLDERRM/D.
©
ꢀ Semiconductor Components Industries, LLC, 2008
March, 2008 – Rev. 8
1
Publication Order Number:
2N6071/D
2N6071A/B Series
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
J
Rating
Symbol
Value
Unit
(T =
*
40 to 110
°
C, Sine Wave, 50 to 60 Hz, Gate Open)
V
DRM,
V
RRM
V
J
2N6071A,B
2N6073A,B
2N6075A,B
200
400
600
*On‐State RMS Current (T
= 85
°
C) Full Cycle Sine Wave 50 to 60 Hz
I
4.0
A
A
C
T(RMS)
*Peak Non-repetitive Surge Current (One Full cycle, 60 Hz, T
= +110
°
C)
I
30
J
TSM
2
2
Circuit Fusing Considerations (t = 8.3 ms)
I t
3.7
10
A s
*Peak Gate Power (Pulse Width
≤
1.0
m
s, T
= 85
°
C)
P
W
W
C
GM
*Average Gate Power (t = 8.3 ms, T
= 85
°
C)
P
0.5
C
G(AV)
*Peak Gate Voltage (Pulse Width
≤
1.0
m
s, T
= 85
°
C)
V
GM
5.0
V
C
*Operating Junction
T
e
mperature Range
*Storage
T
e
mperature Range
T
-40 to +110
-40 to +150
8.0
°
C
J
T
stg
°
C
–
in. lb.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. V
and V
for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such
DRM
RRM
that the voltage ratings of the devices are exceeded.
2.
T
o
rque
rating applies with use of a compression washer. Mounting torque in excess of 6 in. lb. does not appreciably lower case‐to‐sink thermal
resistance. Main terminal 2 and heatsink contact pad are common.
THERMAL CHARACTERISTICS
Characteristic
*Thermal Resistance, Junction-to-Case
Symbol
Max
3.5
75
Unit
°
C/W
°
C/W
°
C
R
q
JC
JA
L
Thermal Resistance, Junction-to-Ambient
R
q
Maximum Lead
T
e
mperature for Soldering Purposes 1/8
″
from Case for 10 Seconds
*Indicates JEDEC Registered Data.
T
260
2
2N6071A/B Series
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted; Electricals apply in both directions)
C
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
*Peak Repetitive Blocking Current
= V
I
DRM,
(V =
V
D
Gate Open)
T =
25
°
C
T =
110
°
C
J
I
RRM
–
–
–
–
10
2
m
A
mA
DRM
RRM;
J
ON CHARACTERISTICS
TM
V
V
–
–
–
1.4
–
2
2.5
–
V
V
TM
*Gate Trigger Voltage (Continuous DC), All Quadrants
GT
(Main
T
e
rminal Voltage = 12 Vdc, R
= 100
W
, T
= -40
°
C)
L
J
Gate Non-Trigger Voltage, All Quadrants
V
GD
V
(Main
T
e
rminal Voltage = 12 Vdc, R
= 100
W
, T
= 110
°
C)
0.2
L
J
*Holding Current
(Main
T
e
rminal Voltage = 12 Vdc, Gate Open, Initiating Current =
“
1 Adc)
I
H
mA
T =
-40
°
C
T =
25
°
C
J
–
–
–
–
30
15
J
Turn‐On Time (I
= 14 Adc, I
= 100 mAdc)
TM GT
t
gt
–
1.5
–
m
s
QUADRANT
(Maximum Value)
I
mA
II
mA
III
mA
IV
mA
Type
I
@
T
GT J
Gate Trigger Current (Continuous DC)
2N6071A
2N6073A
2N6075A
+25
°
C
-40
°
C
+25
°
C
-40
°
C
5
20
3
5
20
3
5
20
3
10
30
5
(Main
T
e
rminal Voltage = 12 Vdc, R
= 100
W
)
L
2N6071B
2N6073B
2N6075B
15
15
15
20
DYNAMIC CHARACTERISTICS
Critical Rate of Rise of Commutation Voltage
@ V
dv/dt(c)
–
5
–
V/
m
s
, T
= 85
°
C, Gate Open, I
= 5.7 A, Exponential Waveform,
J TM
DRM
Commutating di/dt = 2.0 A/ms
3. Pulse
T
e
st: Pulse Width
≤
2.0 ms, Duty Cycle
≤
2%.
*Indicates JEDEC Registered Data.
SAMPLE APPLICATION:
TTL‐SENSITIVE GATE 4 AMPERE TRIAC
TRIGGERS IN MODES II AND III
14
0 V
MC7400
4
LOAD
2N6071A
510
W
7
= 5.0 V
115 VAC
60 Hz
-V
EE
V
EE
+
Trigger devices are recommended for gating on Triacs. They provide:
1. Consistent predictable turn‐on points.
2. Simplified circuitry.
3. Fast turn‐on time for cooler, more efficient and reliable operation.
3
2N6071A/B Series
Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current
Quadrant 1
Main
T
e
rminal 2 +
V
TM
Symbol
Parameter
V
I
Peak Repetitive Forward Off State Voltage
Peak Forward Blocking Current
DRM
on state
I
H
DRM
I
at V
RRM
RRM
V
Peak Repetitive Reverse Off State Voltage
Peak Reverse Blocking Current
RRM
RRM
I
+ Voltage
V
Maximum On State Voltage
Holding Current
off state
TM
I
H
I
at V
DRM
DRM
I
H
Quadrant 3
V
TM
Main
T
e
rminal 2 –
Quadrant Definitions for a Triac
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2
(+) MT2
Quadrant II
Quadrant I
(-) I
GT
GATE
(+) I
GT
GATE
MT1
MT1
REF
REF
I
–
+ I
GT
GT
(-) MT2
(-) MT2
Quadrant III
Quadrant IV
(+) I
GT
GATE
(-) I
GT
GATE
MT1
REF
MT1
REF
–
MT2 NEGATIVE
(Negative Half Cycle)
All polarities are referenced to MT1.
With in-phase signals (using standard AC lines) quadrants I and III are used.
SENSITIVE GATE LOGIC REFERENCE
Firing Quadrant
IC Logic Functions
I
II
III
IV
TTL
2N6071A Series
2N6071A Series
2N6071A Series
2N6071A Series
HTL
CMOS (NAND)
CMOS (Buffer)
Operational Amplifier
Zero Voltage Switch
2N6071B Series
2N6071A Series
2N6071B Series
2N6071B Series
2N6071A Series
2N6071B Series
2N6071A Series
2N6071A Series
4
2N6071A/B Series
110
100
90
110
α
= 30
°
60
°
90
°
100
90
α
= 30
°
60
°
120
°
90
°
120
°
180
°
180
°
dc
a
a
dc
80
70
80
70
α
a
α
= CONDUCTION ANGLE
1.0
, AVERAGE ON‐STATE CURRENT (AMP)
α
= CONDUCTION ANGLE
0
2.0
3.0
4.0
0
1.0
2.0
3.0
4.0
I
I
T(RMS)
, RMS ON‐STATE CURRENT (AMP)
T(AV)
Figure 1. Average Current Derating
Figure 2. RMS Current Derating
8.0
8.0
6.0
a
a
dc
180
°
a
a
dc
120
°
6.0
4.0
2.0
0
α
= 180
°
α
= CONDUCTION ANGLE
90
°
α
= CONDUCTION ANGLE
120
°
60
°
4.0
2.0
0
α
= 30
°
30
°
60
°
90
°
0
1.0
2.0
3.0
4.0
0
1.0
2.0
3.0
4.0
I ,
AVERAGE ON‐STATE CURRENT (AMP)
T(AV)
I
T(RMS)
, RMS ON‐STATE CURRENT (AMP)
Figure 3. Power Dissipation
Figure 4. Power Dissipation
3.0
2.0
3.0
OFF‐STATE VOLTAGE = 12 Vdc
ALL MODES
OFF‐STATE VOLTAGE = 12 Vdc
ALL MODES
2.0
1.0
0.7
0.5
1.0
0.7
0.5
0.3
0.3
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40
-20
0
20
40
60
80
100 120
140
T , JUNCTION TEMPERATURE (
°
C)
J
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. Typical Gate-Trigger Voltage
Figure 6. Typical Gate-Trigger Current
5
2N6071A/B Series
40
30
3.0
2.0
GATE OPEN
APPLIES TO EITHER DIRECTION
20
1.0
10
0.7
0.5
7.0
5.0
0.3
-60 -40
-20
0
20
40
60
80
100 120
140
T
= 110
°
C
J
3.0
2.0
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 8. Typical Holding Current
T
= 25
°
C
J
1.0
0.7
0.5
34
32
30
28
26
24
0.3
0.2
T =
-40 to +110
°
C
J
ăf =
60 Hz
22
20
18
16
14
0.1
1.0
2.0
3.0
4.0 5.0
7.0
10
0
1.0
2.0
3.0
4.0
5.0
NUMBER OF FULL CYCLES
V
TM
, ON‐STATE VOLTAGE (VOLTS)
Figure 7. Maximum On-State Characteristics
Figure 9. Maximum Allowable Surge Current
10
5.0
MAXIMUM
TYPICAL
3.0
2.0
1.0
0.5
0.3
0.2
0.1
0.1
0.2
0.5
1.0
2.0
5.0
10
20
50
100
200
500
1.0 k
2.0 k
5.0 k
10 k
t, TIME (ms)
Figure 10. Thermal Response
6
2N6071A/B Series
ORDERING INFORMATION
†
Device
2N6071A
Package
Shipping
TO-225
500 Units / Box
2N6071AG
TO-225
(Pb-Free)
2N6071AT
TO-225
50 Units / Tube
2000 Units / Box
2N6071ATG
TO-225
(Pb-Free)
50 Units / Tube
2000 Units / Box
2N6071B
TO-225
500 Units / Box
2N6071BG
TO-225
(Pb-Free)
2N6071BT
TO-225
50 Units / Tube
2000 Units / Box
2N6071BTG
TO-225
(Pb-Free)
50 Units / Tube
2000 Units / Box
2N6073A
TO-225
2N6073AG
TO-225
(Pb-Free)
2N6073B
TO-225
2N6073BG
TO-225
(Pb-Free)
500 Units / Box
2N6075A
TO-225
2N6075AG
TO-225
(Pb-Free)
2N6075B
TO-225
2N6075BG
TO-225
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
7
2N6071A/B Series
PACKAGE DIMENSIONS
TO-225
CASE 77-09
ISSUE Z
NOTES:
1. DIMENSIONING
AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING
DIMENSION: INCH.
3. 077-01
THRU -08 OBSOLETE, NEW STANDARD
077-09.
-B-
F
C
U
Q
M
-A-
INCHES
DIM MIN
MAX
MILLIMETERS
1
2 3
MIN
10.80
7.50
2.42
0.51
2.93
MAX
11.04
7.74
2.66
0.66
3.30
A
B
C
D
F
0.425
0.295
0.095
0.020
0.115
0.435
0.305
0.105
0.026
0.130
H
K
G
H
J
0.094 BSC
2.39 BSC
0.050
0.015
0.575
5
0.095
0.025
0.655
1.27
0.39
14.61
5
2.41
0.63
J
V
K
M
Q
R
S
U
V
16.63
TYP
TYP
_
_
G
R
0.148
0.045
0.025
0.145
0.040
0.158
0.065
0.035
0.155
—
3.76
1.15
0.64
3.69
1.02
4.01
1.65
0.88
3.93
—
M
M
M
B
0.25 (0.010)
A
S
D
2 PL
M
M
M
B
0.25 (0.010)
A
STYLE 5:
PIN 1.
MT 1
2. MT
2
3. GATE
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
SCILLC reserves the right to make changes without further notice
to any products herein.
SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal
Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMEN
T
:
N. American Technical Support
: 800-282-9855
T
o
ll Free
ꢁUSA/Canada
Europe, Middle East and Africa Technical Support:
ꢁPhone: 421 33 790 2910
Japan Customer Focus Center
ꢁPhone: 81-3-5773-3850
ꢁLiterature Distribution Center for ON Semiconductor
ꢁ
P
.
O. Box 5163, Denver, Colorado 80217 USA
ꢁ
Phone
: 303-675-2175 or 800-344-3860
T
o
ll Free USA/Canada
ꢁ
Fax
: 303-675-2176 or 800-344-3867
T
o
ll Free USA/Canada
ꢁ
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
2N6071/D
