onsemi-2N7000

Part #onsemi-2N7000
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onsemi-2N7000
DATA SHEET  
D
S
N-Channel Enhancement  
Mode Field Effect  
Transistor  
G
2N7000, 2N7002,  
NDS7002A  
Description  
These N
−
channel enhancement mode field effect transistors are  
produced using
onsemi
’s proprietary, high cell density, DMOS  
technology. These products have been designed to minimize on
−
state  
resistance while providing rugged, reliable, and fast switching  
performance. They can be used in most applications requiring up to  
400 mAdc and can deliver pulsed currents up to 2 A. These products  
are particularly suited for low
−
voltage, low
−
current applications, such  
as small servo motor control, power MOSFET gate drivers, and other  
switching applications.  
1
−
Source  
2
−
Gate  
3
−
Drain  
1
1
2
2
3
3
TO
−
92  
CASE 135AN  
TO
−
92  
CASE 135AR  
MARKING DIAGRAM  
Features  
•
High Density Cell Design for Low R  
DS(on)  
$Y&Z&3  
2N  
7000  
•
V
o
ltage Controlled Small Signal Switch  
•
Rugged and Reliable  
•
High Saturation Current Capability  
•
This Device is Pb
−
Free and Halogen Free  
$Y  
&Z  
&3  
= Logo  
= Assembly Plant Code  
= Date Code  
2N7000 =
 
Specific Device Code  
3
1
−
Gate  
2
−
Source  
3
−
Drain  
1
2
SOT
−
23  
CASE 318
−
08  
MARKING DIAGRAM  
&E&Y  
7×2&E&G  
&E  
&Y  
7×2  
= Designates Space  
= Binary Calendar Year Coding Scheme  
= Specific Device Code  
x= 0, 1  
&G  
= Date Code  
ORDERING INFORMATION  
See detailed ordering and shipping information on

this data sheet.  
©
Semiconductor Components Industries, LLC, 1998  
1
Publication Order Number:  
July, 2022
−
Rev. 7  
NDS7002A/D  

2N7000, 2N7002, NDS7002A  
ABSOLUTE MAXIMUM RATINGS
Values are at T
 
= 25
°
C unless otherwise noted.  
C
Value  
2N7002  
60  
2N7000  
NDS7002A  
Symbol  
Parameter  
Unit  
V
V
DSS  
Drain
−
to
−
Source Voltage  
V
DGR  
Drain
−
Gate Voltage (R
 
≤
1 MW)  
60  
V
GS  
V
GSS  
Gate
−
Source Voltage
−
Continuous  
20  
V
Gate
−
Source Voltage
−
Non Repetitive (tp < 50 ms)  
Maximum Drain Current
−
Continuous  
Maximum Drain Current
−
Pulsed  
40  
I
200  
500  
400  
3.2  
115  
800  
200  
1.6  
280  
1500  
mA  
D
P
Maximum Power Dissipation Derated above 25
°
C  
300  
mW  
mW/
°
C  
°
C  
D
2.4  
T , T  
Operating and Storage
T
e
mperature Range  
−
55 to 150  
−
65 to 150  
J
STG  
T
L
Maximum Lead
T
e
mperature for Soldering Purposes,  
1/16
−
inch from Case for 10 s  
300  
°
C  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
THERMAL CHARACTERISTICS
Values are at T
 
= 25
°
C unless otherwise noted.  
C
Value  
2N7000  
2N7002  
NDS7002A  
Symbol  
Parameter  
Unit  
R
Thermal Resistance, Junction to Ambient  
312.5  
625  
417  
°
C/W  
θ
JA  
ELECTRICAL CHARACTERISTICS  
Values are at T
 
= 25
°
C unless otherwise noted.  
C
Symbol  
Parameter  
Conditions  
Type  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
BV  
I
Drain
−
Source Breakdown  
V
V
= 0
V
, I
 
=
1
0
m
A  
All  
60  
−
−
V
DSS  
GS  
D
Voltage  
Zero Gate Voltage Drain  
Current  
= 48
V
, V
 
= 0 V  
2N7000  
−
−
−
−
1
1
m
A  
DSS  
DS  
GS  
V
T
= 48
V
, V
 
= 0 V,  
mA  
DS  
C
GS  
= 125
°
C  
V
DS  
= 60
V
, V
 
= 0 V  
2N7002  
NDS7002A  
−
−
−
−
1
m
A  
GS  
V
T
= 60
V
, V
 
= 0 V,  
0.5  
mA  
DS  
C
GS  
= 125
°
C  
I
Gate
−
Body Leakage,  
Forward  
V
V
= 15
V
, V
 
= 0 V  
2N7000  
−
−
−
−
10  
nA  
nA  
GSSF  
GS  
DS  
= 20
V
, V
 
= 0 V  
2N7002  
NDS7002A  
100  
GS  
DS  
I
Gate
−
Body Leakage,  
Reverse  
V
V
=
−
15
V
, V
 
= 0 V  
2N7000  
−
−
−
−
−
10  
GSSR  
GS  
DS  
=
−
20
V
, V
 
= 0 V  
2N7002  
NDS7002A  
−
100  
GS  
DS  
ON CHARACTERISTICS  
Gate Threshold Voltage  
V
V
V
= V
 
, I
 
= 1 mA  
2N7000  
0.8  
1
2.1  
2.1  
3
V
GS(th)  
DS  
GS  
D
= V
 
, I
 
= 250
m
A  
2N7002  
NDS7002A  
2.5  
DS  
GS  
D
2

2N7000, 2N7002, NDS7002A  
ELECTRICAL CHARACTERISTICS
(continued)  
Values are at T
 
= 25
°
C unless otherwise noted.  
C
Symbol  
Parameter  
Conditions  
Type  
Min  
Typ  
Max  
Unit  
ON CHARACTERISTICS  
R
Static Drain
−
Source  
On
−
Resistance  
V
V
= 10
V
, I
 
=
5
00 mA  
2N7000  
−
−
1.2  
1.9  
5
9
W
DS(on)  
GS  
D
= 10
V
, I
 
=
5
00 mA,  
GS  
D
T
= 125
°
C  
C
V
V
V
= 4.5
V
, I
 
=
7
5 mA  
−
−
−
1.8  
1.2  
1.7  
5.3  
7.5  
GS  
GS  
GS  
D
= 10
V
, I
 
=
5
00 mA  
2N7002  
D
= 10
V
, I
 
=
5
00 mA,  
13.5  
D
T
= 100
°
C  
C
V
V
= 5
V
, I
 
=
5
0 mA  
−
−
1.7  
2.4  
7.5  
GS  
D
= 5
V
, I
 
=
5
0 mA,  
13.5  
GS  
D
T
= 100
°
C  
C
V
V
= 10
V
, I
 
=
5
00 mA  
NDS7002A  
−
−
1.2  
2
2
GS  
D
= 10
V
, I
 
=
5
00 mA,  
3.5  
GS  
D
T
= 125
°
C  
C
V
V
= 5
V
, I
 
=
5
0 mA  
−
−
1.7  
2.8  
3
5
GS  
D
= 5
V
, I
 
=
5
0 mA,  
GS  
D
T
= 125
°
C  
C
V
Drain
−
Source On
−
Voltage  
V
GS  
V
GS  
V
GS  
V
GS  
V
GS  
V
GS  
V
GS  
V
GS  
V
GS  
V
DS  
V
DS  
V
DS  
= 10
V
, I
 
=
5
00 mA  
2N7000  
2N7002  
−
−
0.6  
0.14  
0.6  
2.5  
0.4  
3.75  
1.5  
1
V
DS(on)  
D
= 4.5
V
, I
 
=
7
5 mA  
D
= 10
V
, I
 
=
5
00 mA  
−
D
= 5.0
V
, I
 
=
5
0 mA  
−
0.09  
0.6  
D
= 10
V
, I
 
=
5
00 mA  
NDS7002A  
−
D
= 5.0
V
, I
 
=
5
0 mA  
−
0.09  
600  
2700  
2700  
320  
320  
320  
0.15  
−
D
I
On
−
State Drain Current  
= 4.5
V
, V
 
=
1
0 V  
2N7000  
2N7002  
75  
500  
500  
100  
80  
80  
mA  
mS  
D(on)  
DS  
= 10
V
, V
 
≥
2 V  
−
DS  
DS(on)  
= 10
V
, V
 
≥
2 V  
NDS7002A  
2N7000  
−
DS  
DS(on)  
g
FS  
Forward Transconductance  
= 10
V
, I
 
=
2
00 mA  
−
D
≥
2 V  
≥
2 V  
,
I =
 
200 mA  
2N7002  
−
DS(on)  
D
, I
 
= 200 mA  
DS(on)  
NDS7002A  
−
D
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
Output Capacitance  
V
= 25
V
, V
 
= 0 V,  
All  
All  
All  
−
−
−
20  
11  
4
50  
25  
5
pF  
ns  
iss  
DS  
GS  
f = 1.0 MHz  
C
oss  
C
Reverse Transfer  
Capacitance  
rss  
t
on  
Turn
−
On Time  
2N7000  
−
−
−
−
−
−
−
−
V
D
R
= 15
V
, R
 
=
2
5
W
,  
L
DD  
I
= 500 mA, V
 
= 10
V
,  
GS  
10  
20  
10  
20  
= 25
W  
GEN  
V
D
R
= 30
V
, R
 
=
1
50
W
,  
2N7002  
NDS7002A  
DD  
L
I
= 200 mA, V
 
= 10
V
,  
GS  
= 25
W  
GEN  
t
off  
Turn
−
Off Time  
2N7000  
ns  
V
D
R
= 15
V
, R
 
=
2
5
W
,  
DD  
L
I
= 500 mA, V
 
= 10
V
,  
GS  
= 25
W  
GEN  
V
D
R
= 30
V
, R
 
=
1
50
W
,  
2N7002  
NDS7002A  
DD  
L
I
= 200 mA, V
 
= 10
V
,  
GS  
= 25
W  
GEN  
3

2N7000, 2N7002, NDS7002A  
ELECTRICAL CHARACTERISTICS
(continued)  
Values are at T
 
= 25
°
C unless otherwise noted.  
C
Symbol  
Parameter  
Conditions  
Type  
Min  
Typ  
Max  
Unit  
mA  
A
DRAIN
−
SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS  
I
S
Maximum Continuous Drain
−
Source Diode Forward Current  
Maximum Pulsed Drain
−
Source Diode Forward Current  
2N7002  
NDS7002A  
2N7002  
−
−
−
−
−
−
−
115  
280  
0.8  
1.5  
1.5  
I
−
SM  
NDS7002A  
2N7002  
−
V
SD  
Drain
−
Source Diode  
Forward Voltage  
V
= 0
V
, I
 
= 115 mA  
0.88  
V
GS  
S
V
= 0
V
, I
 
=
4
00 mA  
NDS7002A  
−
0.88  
1.2  
GS  
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
1. Pulse
 
test: Pulse Width
≤
300
m
s, Duty Cycel
≤
2 %  
TYPICAL PERFORMANCE CHARACTERISTICS  
2
1.5  
1
3
2.5  
2
9.0  
8.0  
V
GS  
= 10 V  
V = 4.0  
7.0  
6.0  
4.5  
5.0  
6.0  
7.0  
8.0  
5.0  
4.0  
1.5  
9.0  
10  
0.5  
0
1
3.0  
0.5  
0
0.4  
0.8  
1.2  
1.6  
2
0
1
2
3
4
5
V
DS  
, Drain
−
Source Voltage (V)  
I ,
 
Drain Current (A)  
D
Figure 1. On
−
Region Characteristics  
Figure 2. On
−
Resistance Variation with  
Gate Voltage and Drain Current  
2
3
2.5  
2
V
GS  
V
= 10 V  
= 500 mA  
GS  
1.75  
1.5  
1.25  
1
I
D
T =
 
125
°
C  
J
1.5  
1
25
°
C  
−
55
°
C  
0.75  
0.5  
0.5  
0
−
50  
−
25  
0
25  
50  
75  
100 125  
150  
0
0.4  
0.8  
1.2  
1.6  
2
T ,
 
Junction Temperature (
5
C)  
J
I ,
 
Drain Current (A)  
D
Figure 3. On
−
Resistance Variation with  
Figure 4. On
−
Resistance Variation with  
Temperature  
Drain Current and Temperature  
4
 

2N7000, 2N7002, NDS7002A  
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)  
2
1.1  
25
°
C  
V
DS  
= 10 V  
V =
 
V  
DS GS  
1.05  
I = 1 mA  
1.6  
125
°
C  
1
T =
−
55
°
C  
1.2  
0.95  
0.9  
0.8  
0.4  
0
0.85  
0.8  
0
2
4
6
8
10  
−
50  
−
25  
0
25  
50  
75  
100 125
 
150  
V
GS  
, Gate to Source Voltage (V)  
T ,
 
Junction Temperature (
5
C)  
J
Figure 5. Transfer Characteristics  
Figure 6. Gate Threshold Variation with  
Temperature  
1.100  
1.075  
1.050  
1.025  
1.000  
0.975  
0.950  
0.925  
2
1
V
GS  
= 0 V  
I
= 250
m
A  
D
0.5  
T = 125
°
C  
25
°
C  
0.1  
0.05  
−
55
°
C  
0.01  
0.005  
0.001  
1.2  
, Body Diode Forward Voltage (V)  
1.4  
−
50
−
25  
0
25  
50  
75  
100  
125  
150  
0.2  
0.4  
0.6  
0.8  
1
T ,
 
Junction Temperature (
5
C)  
J
V
SD  
Figure 7. Breakdown Voltage Variation with  
Temperature  
Figure 8. Body Diode Forward Voltage  
Variation with  
10  
8
60  
40  
V
DS  
= 25 V  
C
iss  
20  
10  
C
oss  
6
I = 500 mA  
4
2
5
C
rss  
280 mA  
115 mA  
2
1
f = 1 MHz  
V = 0 V  
0
1
2
3
5
10  
20  
30  
50  
0
0.4  
0.8  
1.2  
1.6  
2
Q ,
 
Gate Charge (nC)  
g
V
DS  
, Drain to Source Voltage (V)  
Figure 9. Capacitance Characteristics  
Figure 10. Gate Charge Characteristics  
5

2N7000, 2N7002, NDS7002A  
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)  
t
on  
V
DD  
t
off  
t
t
t
t
d(off)  
d(on)  
R
r
f
L
V
IN  
90%  
90%  
V
OUT  
D
V
GS  
Output, V  
out  
10%  
10%  
R
DUT  
GEN  
Inverted  
G
90%  
50%  
50%  
S
Input, V  
in  
10%  
Pulse Width  
Figure 11. Switching Test Circuit  
Figure 12. Switching Waveforms  
3
2
3
2
100
m
s  
1
1
R
Limit  
DS(on)  
100
m
s  
1 ms  
0.5  
0.5  
R
Limit  
DS(on)  
1 ms  
0.1  
0.1  
100 ms  
10 ms  
10 ms  
100 ms  
DC  
0.05  
0.05  
1 s  
V
= 10 V  
V
= 10 V  
GS  
GS  
10 s  
1 s  
Single Pulse  
T =
 
25
°
C  
Single Pulse  
T =
 
25
°
C  
10 s  
DS  
0.01  
0.01  
A
A
0.005  
0.005  
1
2
10  
20 30  
60 80  
1
2
5
10  
20 30  
60 80  
5
V
DS  
, Drain
−
Source Voltage (V)  
V
DS  
, Drain
−
Source Voltage (V)  
Figure 13. 2N7000 Maximum Safe Operating Area  
Figure 14. 2N7002 Maximum Safe Operating Area  
3
2
R
Limit  
100
m
s  
DS(on)  
1
1 ms  
0.5  
0.1  
10 ms  
100 ms  
0.05  
1 s  
V
GS  
= 10 V  
Single Pulse  
T =
 
25
°
C  
A
DC  
10 s  
0.01  
0.005  
1
2
5
10  
20 30  
60 80  
V
DS  
, Drain
−
Source Voltage (V)  
Figure 15. NDS7000A Maximum Safe Operating Area  
6

2N7000, 2N7002, NDS7002A  
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)  
1
D = 0.5  
0.2  
0.5  
(t)  
R
R
= r(t) * R  
q
JA  
0.2  
0.1  
q
JA  
= (See Datasheet)  
q
JA  
0.1  
0.05  
P(pk)  
0.05  
t
0.02  
0.01  
1
t
2
(t)  
T
−
T =
 
P * R  
q
JA  
Duty Cycle, D = t
 
/t  
0.02  
0.01  
J
A
Single Pulse  
0.001  
1
2
0.0001  
0.01  
0.1  
t ,
 
Time (s)  
1
10  
100  
300  
1
Figure 16. TO
−
92, 2N7000 Transient Thermal Response Curve  
1
0.5  
D = 0.5  
0.2  
0.1  
0.2  
0.1  
(t)  
R
R
= r(t) * R  
q
JA  
q
q
JA  
JA  
= (See Datasheet)  
0.05  
0.05  
P(pk)  
0.02  
0.01  
0.01  
t
1
t
2
(t)  
T
−
T =
 
P * R  
q
JA  
J
A
0.002  
0.001  
Duty Cycle, D = t
 
/t  
Single Pulse  
0.0001 0.001  
1
2
0.01  
0.1  
t ,
 
Time (s)  
1
10  
100  
300  
1
Figure 17. SOT
−
23, 2N7002 / NDS7002A Transient Thermal Response Curve  
ORDERING INFORMATION  
Min Order Qty /  
†
Immediate Pack Qty  
10000 / 1000  
2000 / 2000  
Part Number  
2N7000  
Marking  
Package  
Packing Method  
2N7000  
TO
−
92 3L  
(Pb
−
Free)  
Bulk  
2N7000
−
D74Z  
2N7000
−
D75Z  
2N7000
−
D26Z  
2N7002  
Ammo  
T
a
pe and Reel  
2000 / 2000  
2000 / 2000  
702  
712  
SOT
−
23 3L  
(Pb
−
Free)  
T
a
pe and Reel  
3000 / 3000  
NDS7002A  
3000 / 3000  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging  
Specifications Brochure, BRD8011/D.  
7

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TO
−
92 3 4.825×4.76  
CASE 135AN  
ISSUE O  
DATE 31 JUL 2016  
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Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13880G  
TO
−
92 3 4.825X4.76  
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ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TO
−
92 3 4.83×4.76 LEADFORMED  
CASE 135AR  
ISSUE O  
DATE 30 SEP 2016  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13879G  
TO
−
92 3 4.83X4.76 LEADFORMED  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
SOT
−
23 (TO
−
236)  
CASE 318
−
08  
ISSUE AS  
DATE 30 JAN 2018  
SCALE 4:1  
NOTES:  
D
1. DIMENSIONING
 
AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING
 
DIMENSION: MILLIMETERS.  
3. MAXIMUM
 
LEAD THICKNESS INCLUDES LEAD FINISH.  
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF  
THE BASE MATERIAL.  
0.25  
3
4. DIMENSIONS
 
D AND E DO NOT INCLUDE MOLD FLASH,  
PROTRUSIONS, OR GATE BURRS.  
T
H
E
E
1
2
MILLIMETERS  
INCHES  
DIM  
A
A1  
b
c
D
E
e
L
MIN  
0.89  
0.01  
0.37  
0.08  
2.80  
1.20  
1.78  
0.30  
0.35  
2.10  
0
°
 
NOM  
1.00  
0.06  
0.44  
0.14  
2.90  
1.30  
1.90  
0.43  
0.54  
2.40  
−−−  
MAX  
MIN  
0.035  
0.000  
0.015  
0.003  
0.110  
0.047  
0.070  
0.012  
0.014  
0.083  
0
°  
NOM  
0.039  
0.002  
0.017  
0.006  
0.114  
0.051  
0.075  
0.017  
0.021  
0.094  
−−−  
MAX  
0.044  
0.004  
0.020  
0.008  
0.120  
0.055  
0.080  
0.022  
0.027  
0.104  
10
°  
L
1.11  
0.10  
0.50  
0.20  
3.04  
1.40  
2.04  
0.55  
0.69  
2.64  
10
°  
3X  
b
L1  
VIEW C  
e
TOP VIEW  
L1  
A
H
E
T
c
A1  
SEE VIEW C  
SIDE VIEW  
GENERIC  
MARKING DIAGRAM*  
END VIEW  
RECOMMENDED  
SOLDERING FOOTPRINT  
XXXM
G  
G
1
3X  
0.90  
XXX = Specific Device Code  
2.90  
M
= Date Code  
G
= Pb
−
Free Package  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”,  
may or may not be present.  
3X  
0.95  
0.80  
PITCH  
DIMENSIONS: MILLIMETERS  
STYLE 1 THRU 5:  
CANCELLED  
STYLE 6:  
STYLE 7:  
PIN 1.
 
EMITTER  
2. BASE  
STYLE 8:  
PIN 1.
 
BASE  
2. EMITTER  
3. COLLECTOR  
PIN 1.
 
ANODE  
2. NO
 
CONNECTION  
3. CATHODE  
3. COLLECTOR  
STYLE 9:  
PIN 1.
 
ANODE  
2. ANODE  
STYLE 10:  
STYLE 11:  
STYLE 12:  
STYLE 13:  
PIN 1.
 
SOURCE  
2. DRAIN  
STYLE 14:  
PIN 1.
 
CATHODE  
2. GATE  
PIN 1.
 
DRAIN  
2. SOURCE  
3. GATE  
PIN 1.
 
ANODE  
PIN 1.
 
CATHODE  
2. CATHODE  
3. ANODE  
2. CATHODE  
3. CATHODE
−
ANODE  
3. CATHODE  
3. GATE  
3. ANODE  
STYLE 15:  
STYLE 16:  
STYLE 17:  
PIN 1.
 
NO CONNECTION  
2. ANODE  
STYLE 18:  
STYLE 19:  
STYLE 20:  
PIN 1.
 
GATE  
2. CATHODE  
3. ANODE  
PIN 1.
 
ANODE  
2. CATHODE  
3. CATHODE  
PIN 1.
 
NO CONNECTION
 
PIN 1.
 
CATHODE  
PIN 1.
 
CATHODE  
2. ANODE  
3. GATE  
2. CATHODE  
3. ANODE  
2. ANODE  
3. CATHODE
−
ANODE  
3. CATHODE  
STYLE 21:  
STYLE 22:  
STYLE 23:  
PIN 1.
 
ANODE  
2. ANODE  
STYLE 24:  
STYLE 25:  
STYLE 26:  
PIN 1.
 
GATE  
2. SOURCE  
3. DRAIN  
PIN 1.
 
RETURN  
2. OUTPUT  
3. INPUT  
PIN 1.
 
GATE  
2. DRAIN  
PIN 1.
 
ANODE  
2. CATHODE  
3. GATE  
PIN 1.
 
CATHODE  
2. ANODE  
3. SOURCE  
3. NO
 
CONNECTION  
3. CATHODE  
STYLE 27:  
STYLE 28:  
PIN 1.
 
CATHODE  
2. CATHODE  
3. CATHODE  
PIN 1.
 
ANODE  
2. ANODE  
3. ANODE  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98ASB42226B  
SOT
−
23 (TO
−
236)  
PAGE 1 OF 1  
ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

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