onsemi-2N7002WT1G
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2N7002W, 2V7002W
Small Signal MOSFET
60 V, 340 mA, Single, N−Channel, SC−70
Features
•
ESD Protected
•
Low R
DS(on)
•
Small Footprint Surface Mount Package
•
2V Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
V
R
MAX
I MAX
D
(BR)DSS
DS(on)
1.6
W
@ 10 V
2.5
W
@ 4.5 V
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
60 V
340 mA
Compliant
Applications
•
Low Side Load Switch
•
Level Shift Circuits
SIMPLIFIED SCHEMATIC
•
DC−DC Converter
1
2
Gate
•
Portable Applications i.e. DSC, PDA, Cell Phone, etc.
3
Drain
MAXIMUM RATINGS
(T =
25
°
C unless otherwise stated)
J
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
60
Unit
V
Source
V
DSS
(
T
o
p View)
V
GS
20
V
Steady State
I
D
mA
MARKING DIAGRAM
& PIN ASSIGNMENT
Drain
T =
25
°
C
A
310
220
A
T =
85
°
C
t < 5 s
T =
25
°
C
A
340
240
A
3
T =
85
°
C
Steady State
t < 5 s
P
mW
D
280
330
71 M
G
SC−70/SOT−323
CASE 419
G
Pulsed Drain Current (t
= 10
m
s)
I
1.4
A
STYLE 8
p
DM
1
2
Operating Junction and Storage
T
e
mperature Range
T , T
−55 to
+150
°
C
Gate
Source
J
STG
71 =
Device Code
Source Current (Body Diode)
I
250
260
mA
S
M
= Date Code
G
= Pb−Free Package
Lead
T
e
mperature for Soldering Purposes
(1/8
″
from case for 10 s)
T
°
C
L
(Note: Microdot may be in either location)
Gate−Source ESD Rating
(HBM, Method 3015)
ESD
2000
V
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
†
Device
Package
Shipping
2N7002WT1G
SC−70
(Pb−Free)
3000/
T
a
pe & Reel
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
2V7002WT1G
SC−70
(Pb−Free)
3000/
T
a
pe & Reel
Junction−to−Ambient − Steady State
R
450
°
C/W
q
JA
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our
T
a
pe and Reel Packaging Specifications
Brochure, BRD8011/D.
R
375
q
JA
1. Surface−mounted
on FR4 board using 1 in sq pad size (Cu area = 1.127 in
sq [1 oz] including traces)
©
Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
April, 2015 − Rev. 6
2N7002W/D
2N7002W, 2V7002W
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
V
GS
= 0
V
, I
=
2
50
m
A
60
V
(BR)DSS
D
Drain−to−Source Breakdown Voltage
T
e
mperature Coefficient
V
/T
J
71
mV/
°
C
(BR)DSS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
I
T =
25
°
C
1.0
15
m
A
m
A
n
A
m
A
m
A
nA
nA
DSS
J
V
V
= 0
V
,
GS
= 60 V
T =
150
°
C
J
DS
T =
25
°
C
J
100
10
V
GS
= 0
V
,
V
DS
= 50 V
T =
150
°
C
J
I
V
= 0
V
, V
=
20 V
10 V
5.0 V
10
GSS
DS
DS
DS
GS
GS
GS
V
= 0
V
, V
=
=
450
150
V
= 0
V
, V
Gate Threshold Voltage
V
V
GS
= V
, I
= 250
m
A
1.0
2.5
V
GS(TH)
DS
D
Negative Threshold
T
e
mperature
Coefficient
V
/T
4.0
mV/
°
C
GS(TH)
J
Drain−to−Source On Resistance
R
V
= 10
V
, I
=
5
00 mA
1.19
1.33
530
1.6
2.5
W
DS(on)
GS
D
V
GS
= 4.5
V
, I
=
2
00 mA
D
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
V
= 5
V
, I
=
2
00 mA
mS
pF
DS
D
C
24.5
4.2
2.2
0.7
0.1
0.3
0.1
ISS
V
= 0
V
, f = 1
M
Hz,
GS
Output Capacitance
C
C
OSS
RSS
V
DS
= 20 V
Reverse Transfer Capacitance
T
o
tal Gate Charge
Q
nC
ns
V
G(TOT)
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Q
G(TH)
V
GS
= 4.5
V
, V
=
1
0 V;
DS
I
D
= 200 mA
Q
GS
GD
Q
GS
Turn−On Delay Time
Rise Time
t
12.2
9.0
d(ON)
t
r
V
I
= 10
V
, V
=
2
5
V
,
DD
GS
= 500 mA, R
= 25
W
Turn−Off Delay Time
Fall Time
t
55.8
29
D
G
d(OFF)
t
f
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
T =
25
°
C
J
0.8
0.7
1.2
SD
V
= 0
V
,
GS
I
= 200 mA
T =
85
°
C
J
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse
T
e
st: pulse width
≤
300
m
s, duty cycle
≤
2%
3. Switching
characteristics are independent of operating junction temperatures
2
2N7002W, 2V7002W
TYPICAL CHARACTERISTICS
1.6
1.2
0.8
1.2
5.0 V
V
= 10 V
GS
4.5 V
9.0 V
4.0 V
8.0 V
7.0 V
6.0 V
0.8
3.5 V
T =
25
°
C
J
3.0 V
2.5 V
0.4
0
0.4
0
T =
125
°
C
T =
−55
°
C
J
J
0
2
4
6
0
2
4
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
3.2
2.8
2.4
2.0
1.6
1.2
0.8
3.2
2.8
2.4
2.0
1.6
1.2
0.8
V
GS
= 4.5 V
V
GS
= 10 V
T =
125
°
C
J
T =
125
°
C
J
T =
85
°
C
J
T =
85
°
C
J
T =
25
°
C
J
T =
25
°
C
J
T =
−55
°
C
J
T =
−55
°
C
J
0.4
0
0.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
I ,
DRAIN CURRENT (A)
D
I ,
DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Drain Current and
Temperature
Figure 4. On−Resistance vs. Drain Current and
Temperature
2.4
2.0
1.6
1.2
2.2
1.8
1.4
I
D
= 0.2 A
I
= 500 mA
D
V
GS
= 4.5 V
V
= 10 V
GS
I
D
= 200 mA
1.0
0.6
0.8
0.4
2
4
6
8
10
−50 −25
0
25
50
75
100
125 150
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
Figure 6. On−Resistance Variation with
Temperature
3
2N7002W, 2V7002W
TYPICAL CHARACTERISTICS
30
5
C
iss
T =
25
°
C
D
J
I
= 0.2 A
4
3
2
20
10
0
T =
25
°
C
GS
J
V
= 0 V
C
oss
1
0
C
rss
0
4
8
12
16
20
0
0.2
0.4
0.6
0.8
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1.0E−6
10
1
V
GS
= 0 V
V
GS
= 0 V
T =
150
°
C
J
1.0E−7
1.0E−8
1.0E−9
1.0E−10
T =
125
°
C
J
T =
85
°
C
J
T =
25
°
C
J
T =
85
°
C
J
0.1
T =
25
°
C
J
0.01
0.4
0.6
0.8
1.0
1.2
5
10 15 20 25 30 35 40 45 50 55 60
, DRAIN−TO−SOURCE VOLTAGE (V)
V
SD
, SOURCE−TO−DRAIN VOLTAGE (V)
V
DS
Figure 9. Diode Forward Voltage vs. Current
Figure 10. Drain−to−Source Leakage Current
vs. Voltage
4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC
−
70 (SOT
−
323)
CASE 419
ISSUE R
DATE 11 OCT 2022
SCALE 4:1
GENERIC
MARKING DIAGRAM
XX M
G
G
1
XX
M
G
= Specific Device Code
= Date Code
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 1:
STYLE 2:
PIN 1.
ANODE
2. N.C.
3. CATHODE
STYLE 3:
PIN 1.
BASE
2. EMITTER
3. COLLECTOR
STYLE 4:
STYLE 5:
PIN 1.
ANODE
2. ANODE
3. CATHODE
CANCELLED
PIN 1.
CATHODE
2. CATHODE
3. ANODE
STYLE 6:
STYLE 7:
PIN 1.
BASE
STYLE 8:
PIN 1.
GATE
2. SOURCE
3. DRAIN
STYLE 9:
STYLE 10:
STYLE 11:
PIN 1.
EMITTER
PIN 1.
ANODE
PIN 1.
CATHODE
2. ANODE
PIN 1.
CATHODE
2. CATHODE
2. BASE
2. EMITTER
2. CATHODE
3. COLLECTOR
3. COLLECTOR
3. CATHODE-ANODE
3. ANODE-CATHODE
3. CATHODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42819B
SC
−
70 (SOT
−
323)
PAGE 1 OF 1
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Semiconductor Components Industries, LLC, 2019
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:
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