onsemi-BSS84
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BSS84
P-Channel Enhancement Mode Field-Effect Transistor
Description
Features
This P-channel enhancement-mode field-effect
transistor is produced using
ON Semiconductor
’s
proprietary, high cell density, DMOS technology.
This very high density process minimizes on-state
resistance and to provide
rugged and reliable
performance and fast switching.
The BSS84 can
.
.
-0.13 A, -50 V,
R
DS(ON)
= 10
Ω
at V
GS
= -5 V
Voltage-Controlled P-Channel Small-Signal
Switch
.
.
High-Density Cell Design for Low R
DS(ON)
be used, with
a minimum of effort, in most
High Saturation Current
D
applications requiring up to 0.13 A DC and can
deliver current up to 0.52 A. This product is
particularly suited to low-voltage applications
D
requiring
a
low-current
high-side
switch.
S
G
S
G
SOT-23
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. Values are at T
A
= 25°C unless otherwise noted.
Symbol
V
DSS
V
GSS
Parameter
Ratings
−
50
Unit
V
V
Drain-Source Voltage
Gate-Source Voltage
20
Continuous
Pulsed
A
A
−
0.13
−
0.52
0.36
I
D
Drain Current
(1)
Maximum Power Dissipation
(1)
W
mW /
°
C
°
C
P
D
2.9
−
55 to +150
Derate Above 25
°
C
T
J
, T
STG
Operating and Storage Junction Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/16” from Case for 10 Seconds
T
L
300
°
C
Thermal Characteristics
θ
JA
Note:
Thermal Resistance, Junction-to-Ambient
(1)
R
350
°
C/W
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference
is guaranteed by design, while R
is
θ
JA
is defined as the solder mounting surface of the drain pins. R
θ
JA
determined by the user’s board design.
θ
JA
a) 350°C/W
when mounted on a minimum pad
Scale 1: 1 on letter-size paper.
Package Marking and Ordering Information
Device Marking
Device
BSS84
Reel Size
Tape width
Quantity
SP
7’’
8mm
3000
© 2002
Semiconductor Components Industries, LLC.
September
-2017, Rev. 2
Publication Order Number:
BSS84/D
Electrical Characteristics
(2)
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
–50
–48
V
V
GS
= 0 V, I
D
= –250
μ
A
I
D
= –250
μ
A,
Referenced to 25
℃
V
DS
= –50 V,
V
GS
= 0 V
V
DS
= –50 V, V
GS
= 0 V,
T
J
= 125
°
C
Δ
BV
DSS
Breakdown Voltage Temperature
mV /
℃
Coefficient
Δ
T
J
I
DSS
I
GSS
–15
–60
μ
A
μ
A
Zero Gate Voltage Drain Current
Gate–Body Leakage.
nA
V
V
GS
= 20
V, V
DS
= 0 V
10
BV
DSS
Drain–Source Breakdown Voltage
On Characteristics
(2)
–50
V
GS
= 0 V,
I
D
= –250
μ
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= –1 mA
I
D
= –1 mA,
–0.8
–1.7
3
–2
V
V
GS(TH)
Gate Threshold Voltage
mV /
℃
T
J
Temperature Coefficient
Referenced to 25
℃
V
GS
= –5 V, I
D
= –0.10 A
V
GS
= –5 V, I
D
= –0.10 A,
T
J
= 125
°
C
V
GS
= –5 V, V
DS
= – 10 V
V
DS
= –25 V, I
D
= – 0.10 A
1.2
1.9
10.0
17.0
Ω
Ω
Static Drain–Source
On–Resistance
R
DS(on)
I
D(on)
g
FS
On–State Drain Current
Forward Transconductance
–0.6
0.05
A
S
0.60
Dynamic Characteristics
C
ISS
Input Capacitance
73
10
pF
pF
V
DS
= –25 V,
C
OSS
Output Capacitance
V
GS
= 0 V,
C
RSS
Reverse Transfer Capacitance
Gate Resistance
5
9
pF
f = 1.0 MHz
V
GS
= –15 mV, f = 1.0 MHz
R
G
Ω
Switching Characteristics
(2)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn–On Delay
Turn–On Rise Time
Turn–Off Delay
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
2.5
6.3
10
4.8
0.9
0.2
0.3
5.0
13.0
20
9.6
1.3
ns
ns
ns
V
DD
= –30 V,
I
D
= – 0.27 A,
V
GS
= –10 V,
R
GEN
= 6
ns
nC
nC
nC
V
V
DS
= –25 V, I
D
= –0.10 A,
GS
= –5 V
Drain-Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain-Source Diode Forward Current
-0.13
-1.2
A
V
Drain-Source Diode Forward
V
GS
= 0 V, I
S
= – 0.26 A
(2)
Voltage
V
SD
-0.8
t
RR
Diode Reverse-Recovery Time
Diode Reverse-Recovery Charge
10
3
ns
I
F
= -0.1 A,
d
iF
/ d
t
= 100 A / µs
(2)
Q
RR
nC
Note:
2. Pulse
Test: Pulse Width
≤
300
μ
s, Duty Cycle
≤
2.0%.
2
Typical Characteristics
1
2
1.8
1.6
1.4
1.2
1
V
GS
= -5V
-4.5V
-3.5V
0.8
0.6
0.4
0.2
0
V
GS
=-3.0V
-3.0V
-3.5V
-4.0V
-4.5V
-5.0V
-2.5V
0.8
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
1
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
-I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation with Drain
Current and Gate Voltage
1.8
1.6
1.4
1.2
1
5
I
D
= -0.10A
I
D
= -0.05A
V
GS
= -5V
4
3
T
A
= 125
o
C
0.8
0.6
0.4
2
T
A
= 25
o
C
1
-50
-25
0
25
50
75
100
125
150
2
2.5
3
3.5
4
4.5
5
T
J
, JUNCTION TEMPERATURE (
o
C)
-V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature
Figure 4. On-Resistance Variation with Gate-to-
Source Voltage
1
1
0.8
0.6
0.4
0.2
0
V
DS
= -5V
V
GS
= 0V
25
o
C
T
A
= -55
o
C
0.1
125
o
C
T
A
= 125
o
C
25
o
C
0.01
-55
o
C
0.001
0.0001
1
1.5
2
2.5
3
3.5
4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-V
SD
, BODY
DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation with
Source Current and Temperature
3
Typical Characteristics
(Continued)
5
100
80
60
40
20
0
V
DS
= -8V
f = 1 MHz
V
GS
= 0 V
I
D
= -0.10A
-25V
4
-30V
C
ISS
3
2
1
0
C
OSS
C
RSS
0
0.2
0.4
0.6
0.8
1
0
10
20
30
40
50
Q
g
, GATE CHARGE (nC)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
5
4
3
2
1
0
SINGLE PULSE
R
θ
JA
= 350
캜
/W
T
A
= 25
캜
0.01
0.1
1
10
100
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area
Figure 10. Single-Pulse Maximum Power
Dissipation
1
D = 0.5
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 350
o
C/W
0.2
0.1
0.1
P(pk)
0.05
0.02
t
1
t
2
0.01
0.01
T
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 11. Transient Thermal Response Curve
Thermal characterization performed using the conditions described on page 1.
Transient thermal response will change depending on the circuit board design.
4
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