onsemi-EMC5DXV5T1G
| Part # | onsemi-EMC5DXV5T1G |
Download  | onsemi-EMC5DXV5T1G |
EMC2DXV5T1G,
EMC3DXV5T1G,
EMC4DXV5T1G,
EMC5DXV5T1G
Dual Common
Base-Collector Bias
Resistor
T
r
ansistors
3
2
1
R1
R2
NPN and PNP Silicon Surface Mount
Transistors with Monolithic Bias
Resistor Network
Q2
R2
Q1
R1
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the EMC2DXV5T1G series,
two complementary BRT devices are housed in the SOT−553 package
which is ideal for low power surface mount applications where board
space is at a premium.
4
5
5
1
SOT−553
CASE 463B
Features
•
Simplifies Circuit Design
•
Reduces Board Space
MARKING DIAGRAM
•
Reduces Component Count
Ux M
G
•
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
G
Ux = Specific
Device Code
x = C, 3, E, or 5
•
These are Pb−Free Devices
M
G
=
=
Date Code
Pb−Free Package
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted, common for Q
A
1
(Note: Microdot may be in either location)
and Q
, − minus sign for Q
(PNP) omitted)
2
1
Rating
Symbol
Value
50
Unit
ORDERING INFORMATION
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
V
Vdc
Vdc
CBO
CEO
See detailed ordering and shipping information in the package
V
50
I
C
100
mAdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
©
Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
May, 2014 − Rev. 7
EMC2DXV5T1/D
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
ONE JUNCTION HEATED
T
o
tal Device Dissipation
P
D
T =
25
°
C
mW
mW/
°
C
A
Derate above 25
°
C
Thermal Resistance, Junction-to-Ambient
BOTH JUNCTIONS HEATED
T
o
tal Device Dissipation
R
°
C/W
q
JA
P
D
T =
25
°
C
mW
mW/
°
C
A
Derate above 25
°
C
Thermal Resistance, Junction-to-Ambient
R
−
5
5 to +150
°
C/W
°
C
q
JA
Junction and Storage
T
e
mperature
1. FR−4
@ Minimum Pad
T , T
J stg
DEVICE ORDERING INFORMATION, MARKING AND RESISTOR VALUES
Transistor 1 − PNP
Transistor 2 − NPN
†
Device
EMC2DXV5T1G
NSVEMC2DXV5T1G*
EMC3DXV5T1G
EMC3DXV5T5G
EMC4DXV5T1G
EMC5DXV5T1G
Marking
UC
R1 (K)
22
R2 (K)
22
R1 (K)
22
R2 (K)
22
Package
Shipping
4000 /
T
a
pe & Reel
4000 /
T
a
pe & Reel
4000 /
T
a
pe & Reel
8000 /
T
a
pe & Reel
4000 /
T
a
pe & Reel
4000 /
T
a
pe & Reel
UC
22
22
22
22
SOT−553
(Pb−Free)
U3
10
10
10
10
UE
U5
10
47
10
47
47
47
47
4.7
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our
T
a
pe and Reel Packaging
Specifications Brochure, BRD8011/D.
*NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
250
200
150
100
R
= 833
°
C/W
q
JA
50
0
-ꢀ50
0
50
100
150
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 1. Derating Curve
2
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
A
Characteristic
Symbol
Min
Typ
Max
Unit
Q1 TRANSISTOR: PNP
OFF CHARACTERISTICS
Collector-Base Cutoff Current (V
= 50
V
, I
=
0
)
I
I
−
−
−
−
100
500
nAdc
nAdc
mAdc
CB
E
CBO
Collector-Emitter Cutoff Current (V
= 50
V
, I
=
0
)
CB
B
CEO
Emitter-Base Cutoff Current
(V =
6.0
V
, I
=
0
)
EMC2DXV5T1G
EMC3DXV5T1G
EMC4DXV5T1G
EMC5DXV5T1G
I
−
−
−
−
−
−
−
−
0.2
0.5
0.2
1.0
EBO
EB
C
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (I
= 10
m
A, I
= 0)
V
V
50
50
−
−
−
−
Vdc
Vdc
C
E
(BR)CBO
Collector-Emitter Breakdown Voltage (I
= 2.0 mA, I
= 0)
C
B
(BR)CEO
DC Current Gain
(V =
10
V
, I
=
5
.0 mA)
EMC2DXV5T1G
h
FE
60
35
80
20
100
60
140
35
−
−
−
−
EMC3DXV5T1G
EMC4DXV5T1G
EMC5DXV5T1G
CE
C
Collector−Emitter Saturation Voltage (I
= 10 mA, I
= 0.3 mA)
V
−
−
−
−
−
0.25
0.2
−
Vdc
Vdc
Vdc
k
W
C
B
CE(SAT)
Output Voltage (on) (V
= 5.0 V, V
= 2.5 V, R
= 1.0 k
W
)
V
OL
CC
B
L
Output Voltage (off) (V
= 5.0 V, V
= 0.5 V, R
= 1.0 k
W
)
V
OH
4.9
CC
B
L
Input Resistor
Resistor Ratio
EMC2DXV5T1G
EMC3DXV5T1G, EMC4DXV5T1G
EMC5DXV5T1G
R1
15.4
7.0
3.3
22
10
4.7
28.6
13
6.1
EMC2DXV5T1G
EMC3DXV5T1G
EMC4DXV5T1G
EMC5DXV5T1G
R1/R2
0.8
0.8
0.17
0.38
1.0
1.0
0.21
0.47
1.2
1.2
0.25
0.56
Q2 TRANSISTOR: NPN
OFF CHARACTERISTICS
Collector-Base Cutoff Current (V
= 50
V
, I
=
0
)
I
I
−
−
−
−
100
500
nAdc
nAdc
mAdc
CB
E
CBO
Collector-Emitter Cutoff Current (V
= 50
V
, I
=
0
)
CB
B
CEO
Emitter-Base Cutoff Current
(V =
6.0
V
, I
=
0
)
EMC2DXV5T1G
EMC3DXV5T1G
I
−
−
−
−
−
−
0.2
0.5
0.1
EBO
EB
C
EMC4DXV5T1G, EMC5DXV5T1G
ON CHARACTERISTICS
Collector-Base Breakdown Voltage (I
= 10
m
A, I
= 0)
V
V
50
50
−
−
−
−
Vdc
Vdc
C
E
(BR)CBO
Collector-Emitter Breakdown Voltage (I
= 2.0 mA, I
= 0)
C
B
(BR)CEO
DC Current Gain
(V =
10
V
, I
=
5
.0 mA)
EMC2DXV5T1G
EMC3DXV5T1G
EMC4DXV5T1G, EMC5DXV5T1G
h
FE
60
35
80
100
60
140
−
−
−
CE
C
Collector−Emitter Saturation Voltage (I
= 10 mA, I
= 0.3 mA)
V
−
−
−
−
−
0.25
0.2
−
Vdc
Vdc
Vdc
k
W
C
B
CE(SAT)
Output Voltage (on) (V
= 5.0 V, V
= 2.5 V, R
= 1.0 k
W
)
V
OL
CC
B
L
Output Voltage (off) (V
= 5.0 V, V
= 0.5 V, R
= 1.0 k
W
)
V
OH
4.9
CC
B
L
Input Resistor
Resistor Ratio
EMC2DXV5T1G
EMC3DXV5T1G
EMC4DXV5T1G, EMC5DXV5T1G
R1
15.4
7.0
33
22
10
47
28.6
13
61
EMC2DXV5T1G
EMC3DXV5T1G
R1/R2
0.8
0.8
0.8
1.0
1.0
1.0
1.2
1.2
1.2
EMC4DXV5T1G, EMC5DXV5T1G
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC2DXV5T1 PNP TRANSISTOR
1000
10
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
1
25
°
C
75
°
C
25
°
C
T ꢁ=ꢁ-25
°
C
A
-25
°
C
100
ꢀ0.1
10
0.01
1
10
I ,
COLLECTOR CURRENT (mA)
0
ꢀ20
ꢀ40
ꢀ50
100
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 2. V
CE(sat)
versus I
C
Figure 3. DC Current Gain
4
3
2
100
25
°
C
75
°
C
f = 1 MHz
l =
0 mA
T ꢁ=ꢁ-25
°
C
A
E
10
1
T =
25
°
C
A
ꢀ0.1
1
0
ꢀ0.01
V =
5 V
O
ꢀ0.001
0
1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
10
0
10
20
30
40
50
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
25
°
C
75
°
C
1
ꢀ0.1
0
10
ꢀ20
ꢀ30
ꢀ40
ꢀ50
I ,
COLLECTOR CURRENT (mA)
C
Figure 6. Input Voltage versus Output Current
4
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC2DXV5T1 NPN TRANSISTOR
1
1000
I /I
= 10
C B
V
CE
= 10 V
T ꢁ=ꢁ-25
°
C
A
25
°
C
T ꢁ=ꢁ75
°
C
A
25
°
C
-25
°
C
0.1
75
°
C
100
0.01
0.001
10
0
20
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 7. V
CE(sat)
versus I
C
Figure 8. DC Current Gain
4
3
100
10
25
°
C
75
°
C
f = 1 MHz
I =
0 mA
E
T ꢁ=ꢁ-25
°
C
A
T =
25
°
C
A
1
0.1
2
1
0.01
0.001
V =
5 V
O
0
0
10
20
30
40
50
0
1
2
3
4
5
6
7
8
9
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 9. Output Capacitance
Figure 10. Output Current versus Input Voltage
10
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
25
°
C
75
°
C
1
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 11. Input Voltage versus Output
Current
5
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC3DXV5T1 PNP TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
T ꢁ=ꢁ-25
°
C
A
25
°
C
ꢀ0.1
100
-25
°
C
25
°
C
75
°
C
ꢀ0.01
10
ꢀ20
I ,
COLLECTOR CURRENT (mA)
1
10
100
0
ꢀ40
50
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 12. V
CE(sat)
versus I
C
Figure 13. DC Current Gain
4
3
100
10
1
25
°
C
75
°
C
f = 1 MHz
l =
0 mA
E
T ꢁ=ꢁ-25
°
C
A
T =
25
°
C
A
2
1
0
ꢀ0.1
ꢀ0.01
V =
5 V
O
ꢀ0.001
0
10
20
30
40
50
0
1
ꢀ2
3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 14. Output Capacitance
Figure 15. Output Current versus Input
Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
25
°
C
75
°
C
1
ꢀ0.1
0
10
ꢀ20
ꢀ30
ꢀ40
ꢀ50
I ,
COLLECTOR CURRENT (mA)
C
Figure 16. Input Voltage versus Output
Current
6
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC3DXV5T1 NPN TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
25
°
C
25
°
C
T ꢁ=ꢁ-25
°
C
A
0.1
-25
°
C
75
°
C
100
0.01
10
0.001
1
10
100
0
20
40
50
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 17. V
CE(sat)
versus I
C
Figure 18. DC Current Gain
4
3
2
1
0
100
10
1
75
°
C
25
°
C
f = 1 MHz
I =
0 mA
T ꢁ=ꢁ-25
°
C
A
E
T =
25
°
C
A
0.1
0.01
V =
5 V
O
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 19. Output Capacitance
Figure 20. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
10
1
25
°
C
75
°
C
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 21. Input Voltage versus Output
Current
7
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS −EMC4DXV5T1 PNP TRANSISTOR
1
180
T ꢁ=ꢁ75
°
C
A
I /I
= 10
C B
V
CE
= 10 V
160
140
120
100
80
T ꢁ=ꢁ-25
°
C
A
25
°
C
-25
°
C
25
°
C
0.1
75
°
C
0.01
60
40
20
0.001
0
0
20
40
60
80
1
2
4
6
8
10 15
20 40 50 60 70 80 90
100
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 22. V
CE(sat)
versus I
C
Figure 23. DC Current Gain
4.5
4
100
10
1
T ꢁ=ꢁ75
°
C
f = 1 MHz
l =
0 V
A
25
°
C
E
3.5
3
T =
25
°
C
A
-25
°
C
2.5
2
1.5
1
0.5
0
V =
5 V
O
0
2
4
6
8
10 15 20 25 30 35 40 45 50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 24. Output Capacitance
Figure 25. Output Current versus Input Voltage
10
+12 V
V =
0.2 V
O
25
°
C
T ꢁ=ꢁ-25
°
C
A
75
°
C
Typical Application
for PNP BRTs
1
LOAD
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 26. Input Voltage versus Output Current
Figure 27. Inexpensive, Unregulated Current Source
8
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC5DXV5T1 PNP TRANSISTOR
1000
1
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
25
°
C
100
-25
°
C
T ꢁ=ꢁ75
°
C
A
25
°
C
0.1
-25
°
C
10
1
0.01
1
10
100
1000
0
10
20
30
40
50
60
I ,
COLLECTOR CURRENT (mA)
C
I ,
COLLECTOR CURRENT (mA)
C
Figure 28. V
CE(sat)
versus I
C
Figure 29. DC Current Gain
12
100
10
f = 1 MHz
I =
0 mA
10
8
E
75
°
C
T =
25
°
C
A
6
1
0.1
V =
5 V
O
4
SERIES 1
T ꢁ=ꢁ-25
°
C
A
2
0
25
°
C
0.01
0
5
10
15
20
25
30
35
40
45
0
2
4
6
8
10
12
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 30. Output Capacitance
Figure 31. Output Current versus Input Voltage
9
EMC2DXV5T1G, EMC3DXV5T1G, EMC4DXV5T1G, EMC5DXV5T1G
TYPICAL ELECTRICAL CHARACTERISTICS − EMC4DXV5T1, EMC5DXV5T1 NPN TRANSISTOR
10
1000
100
10
V
CE
= 10 V
I /I
= 10
C B
T ꢁ=ꢁ75
°
C
A
1
25
°
C
-25
°
C
25
°
C
75
°
C
T ꢁ=ꢁ-25
°
C
A
0.1
0.01
0
20
I ,
COLLECTOR CURRENT (mA)
40
50
1
10
100
I ,
COLLECTOR CURRENT (mA)
C
C
Figure 32. V
CE(sat)
versus I
C
Figure 33. DC Current Gain
1
100
10
1
25
°
C
f = 1 MHz
I =
0 mA
75
°
C
E
T ꢁ=ꢁ-25
°
C
A
0.8
T =
25
°
C
A
0.6
0.4
0.1
0.01
0.2
0
V =
5 V
O
0.001
0
10
20
30
40
50
0
2
4
6
8
10
V ,
REVERSE BIAS VOLTAGE (V)
R
V ,
INPUT VOLTAGE (V)
in
Figure 34. Output Capacitance
Figure 35. Output Current versus Input Voltage
100
V =
0.2 V
O
T ꢁ=ꢁ-25
°
C
A
25
°
C
75
°
C
10
1
0.1
0
10
20
30
40
50
I ,
COLLECTOR CURRENT (mA)
C
Figure 36. Input Voltage versus Output Current
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT
−
553, 5 LEAD
CASE 463B
ISSUE C
SCALE 4:1
DATE 20 MAR 2013
NOTES:
D
−
X
−
1. DIMENSIONING
AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING
DIMENSION: MILLIMETERS
A
L
3. MAXIMUM
LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
5
4
3
MILLIMETERS
INCHES
NOM
0.022
0.009
0.005
0.063
0.047
0.020 BSC
0.008
0.063
E
−
Y
−
DIM
A
b
c
D
E
e
L
H
MIN
0.50
0.17
0.08
1.55
1.15
NOM
0.55
0.22
0.13
1.60
MAX
MIN
MAX
0.024
0.011
0.007
0.065
0.049
H
E
0.60
0.27
0.18
1.65
1.25
0.020
0.007
0.003
0.061
0.045
1
2
b
5 PL
c
1.20
e
M
0.50 BSC
0.20
1.60
0.08 (0.003)
X Y
0.10
1.55
0.30
1.65
0.004
0.061
0.012
0.065
E
RECOMMENDED
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.3
0.0118
XXM
G
G
0.45
0.0177
XX =
Specific Device Code
1.0
0.0394
M
G
= Date Code
= Pb
−
Free Package
(Note: Microdot may be in either location)
1.35
0.0531
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
0.5
0.5
0.0197 0.0197
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
STYLE 1:
STYLE 2:
STYLE 3:
PIN 1.
ANODE 1
2. N/C
STYLE 4:
STYLE 5:
PIN 1.
BASE
PIN 1.
CATHODE
PIN 1.
SOURCE 1
2. DRAIN
1/2
3. SOURCE
1
4. GATE
1
PIN 1.
ANODE
2. EMITTER
3. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
2. COMMON
ANODE
3. CATHODE
2
4. CATHODE
3
5. CATHODE
4
3. ANODE
2
4. CATHODE
2
5. CATHODE
1
4. COLLECTOR
5. CATHODE
5. GATE
2
STYLE 9:
STYLE 6:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 7:
PIN 1.
BASE
STYLE 8:
PIN 1.
ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
PIN 1.
CATHODE
2. COLLECTOR
3. N/C
2. EMITTER
3. EMITTER
1
4. COLLECTOR
1
5. COLLECTOR
2/BASE 1
3. BASE
4. COLLECTOR
5. COLLECTOR
4. BASE
5. EMITTER
98AON11127D
DOCUMENT NUMBER:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
O
N
S
E
M
ICONDUCTOR STANDARD
STATUS:
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SOT
−
553, 5 LEAD
PAGE 1 O
F
2
DOCUMENT NUMBER:
98AON11127D
PAGE 2 OF 2
ISSUE
REVISION
ADDED STYLES 3
−
9. REQ. BY D. BARLOW
DATE
A
B
11 NOV 2003
27 MAY 2005
ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.
BY HONG XIAO
C
UPDATED DIMENSIONS D, E, AND HE. REQ. BY J. LETTERMAN.
20 MAR 2013
ON Semiconductor
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SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.
All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
SCILLC does not convey any license under its patent rights
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
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This literature is subject to all applicable copyright laws and is not for resale in any manner.
©
Semiconductor Components Industries, LLC, 2013
Case Outline Number:
March, 2013
−
Rev. C
463B
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