onsemi-FAM65HR51DS2
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H-Bridge in APM16 Series
for LLC and Phase-shifted
DC-DC Converter
FAM65HR51DS1,
FAM65HR51DS2
Features
•
SIP or DIP H−Bridge Power Module for On−board Charger (OBC) in
EV or PHEV
•
5 kV/1 sec Electrically Isolated Substrate for Easy Assembly
•
Creepage and Clearance per IEC60664−1, IEC 60950−1
•
Compact Design for Low Total Module Resistance
•
Module Serialization for Full Traceability
•
Lead Free, RoHS and UL94V−0 Compliant
•
Automotive Qualified per AEC Q101 and AQG324 Guidelines
APMCA−A16
16 LEAD
CASE MODGF
Applications
•
DC−DC Converter for On−board Charger in EV or PHEV
Benefits
•
Enable Design of Small, Efficient and Reliable System for Reduced
V
e
hicle Fuel Consumption and CO
Emission
2
•
Simplified Assembly, Optimized Layout, High Level of Integration,
and Improved Thermal Performance
APMCA−B16
16 LEAD
CASE MODGJ
MARKING DIAGRAM
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
XXXX = Specific Device Code
ZZZ =
Lot ID
AT
Y
= Assembly &
T
e
st Location
=
Y
e
ar
W
= Work Week
NNN =
Serial Number
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
©
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2020 − Rev. 1
FAM65HR51DS1/D
FAM65HR51DS1, FAM65HR51DS2
ORDERING INFORMATION
Snubber
DBC
Pb−Free and
Operating
Packing
Capacitor Inside
Material RoHS
Compliant Temperature
(T )
Method
Part Number
FAM65HR51DS1
FAM65HR51DS2
Package
Lead Forming
Y−Shape
A
APM16−CAA
APM16−CAB
Y
e
s
Y
e
s
Al O
Y
e
s
Y
e
s
−40
°
C ~ 125
°
C
−40
°
C ~ 125
°
C
Tube
Tube
2
3
3
L−Shape
Al O
2
Pin Configuration and Block Diagram
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
AC1
Pin Description
Phase 1 Leg of the H−Bridge
Source Sense of Q1
1, 2
3
Q1 Sense
Q1 Gate
B+
4
Gate
T
e
rminal of Q1
5, 6
7, 8
9
Positive Battery
T
e
rminal
Negative Battery
T
e
rminal
Source Sense of Q2
B−
Q2 Sense
Q2 Gate
Q4 Sense
Q4 Gate
Q3 Sense
Q3 Gate
AC2
10
Gate
T
e
rminal of Q2
11
Source Sense of Q4
12
Gate
T
e
rminal of Q4
13
Source Sense of Q3
14
Gate
T
e
rminal of Q3
15, 16
Phase 2 Leg of the H−Bridge
2
FAM65HR51DS1, FAM65HR51DS2
Block Diagram
Figure 2. Schematic
Table 2. ABSOLUTE MAXIMUM RATINGS
(T =
25
°
C, Unless Otherwise Specified)
J
Symbol
Parameter
Max
Unit
V
V
V
(Q1~Q4)
(Q1~Q4)
Drain−to−Source Voltage
Gate−to−Source Voltage
650
DS
GS
20
33
V
A
I
(Q1~Q4)
C
GS
D
21
A
C
GS
E
AS
(Q1~Q4)
21
mJ
W
°
C
°
C
°
C
P
D
Maximum Junction
T
e
mperature
Maximum Case
T
e
mperature
Storage
T
e
mperature
135
T
T
−55 to +150
−40 to +125
−40 to +125
J
C
T
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum
continuous current and power, without switching losses, to reach T
= 150
°
C respectively at T
= 25
°
C and T
= 100
°
C; defined
J
C
C
by design based on MOSFET R
and R
and not subject to production test
q
DS(ON)
JC
2. Starting
T =
25
°
C, L = 1 mH, I
= 6.5 A, V
= 145 V during inductor charging and V
= 0 V during time in avalanche
J
AS
DD
DD
Table 3. COMPONENTS
Supplier
Part Number
Parameter
Capacitance
VDC Rating
Min
135
−
Typ
150
630
Max
165
−
Unit
nF
V
GCJ43QR7LV154KXJ1
3. Please
refer to datasheet of the Murata capacitor
DBC Substrate
Compliance to RoHS Directives
0.63 mm Al
O alumina
with 0.3 mm copper on both sides.
DBC substrate is NOT nickel plated.
The power module is 100% lead free and RoHS compliant
2000/53/C directive.
2
3
Lead Frame
Solder
OFC copper alloy, 0.50 mm thick. Plated with 8
um to
25.4 um thick Matte Tin
Solder used is a lead free SnAgCu alloy.
Solder presents high risk to melt at temperature beyond
210
°
C. Base of the leads, at the interface with the package
body, should not be exposed to more than 200
°
C during
mounting on the PCB or during welding to prevent the
re−melting of the solder joints.
Flammability Information
All materials present in the power module meet UL
flammability rating class 94V−0.
3
FAM65HR51DS1, FAM65HR51DS2
Table 4. ELECTRICAL SPECIFICATIONS
(T =
25
°
C, Unless Otherwise Specified)
J
Symbol
Parameter
Conditions
I =
1 mA, V
= 0 V
D
Min
650
3.0
−
Typ
−
Max
−
Unit
V
BV
Drain−to−Source Breakdown Voltage
Gate to Source Threshold Voltage
Q1 – Q4 MOSFET On Resistance
Q1 – Q4 MOSFET On Resistance
Forward Transconductance
DSS
GS
V
GS(th)
V
GS
= V
, I
= 3.3 mA
−
5.0
51
−
V
DS
D
R
R
V
GS
= 10
V
, I
=
2
0 A
44
79
30
−
m
W
m
W
S
DS(ON)
DS(ON)
D
V
GS
−
D
J
g
FS
V
DS
−
−
D
I
Gate−to−Source Leakage Current
Drain−to−Source Leakage Current
V
=
20
V
, V
= 0 V
−100
−
+100
10
nA
m
A
GSS
GS
DS
DS
I
V
= 650
V
, V
= 0 V
−
DSS
GS
C
Input Capacitance
V
= 400 V
−
−
−
−
4864
109
16
−
−
−
−
pF
pF
pF
pF
iss
DS
V
= 0 V
GS
C
Output Capacitance
oss
f = 1 MHz
= 0 to 520 V
DS
C
Reverse Transfer Capacitance
Effective Output Capacitance
rss
C
V
652
oss(eff)
V
GS
= 0 V
R
Gate Resistance
f = 1 MHz
−
−
−
−
2
−
−
−
−
W
g
Q
T
o
tal Gate Charge
V
= 380 V
= 20 A
123
37.5
49
nC
nC
nC
g(tot)
DS
I
D
Q
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
gs
V
= 0 to 10 V
GS
Q
gd
t
Turn−on Time
V
= 400 V
= 20 A
−
−
−
−
−
−
87
47
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
on
DS
I
D
t
Turn−on Delay Time
Turn−on Rise Time
Turn−off Time
d(on)
V
= 10 V
GS
t
r
43
R
= 4.7
W
G
t
148
118
29
off
d(off)
t
Turn−off Delay Time
Turn−off Fall Time
t
f
BODY DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
Reverse Recovery Time
I
= 20 A, V
= 0 V
−
−
−
0.95
133
669
−
−
−
V
SD
SD
GS
T
V
= 520
V
, I
=
2
0 A,
ns
nC
rr
DS
D
I
t
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Defined
by design, not subject to production test
Table 5. THERMAL RESISTANCE
Parameters
Min
−
Typ
0.66
1.2
Max
0.92
−
Unit
°
C/W
°
C/W
R
R
(per chip)
(per chip)
θ
JC
JS
−
θ
5.
T
e
st
method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package
at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed
6. Defined
by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal
interface material
Table 6. ISOLATION
(Isolation resistance at tested voltage from the base plate to control pins or power terminals.)
Test
Test Conditions
Isolation Resistance
Unit
Leakage @ Isolation Voltage (Hi−Pot)
V
AC
= 5 k
V
,
6
0 Hz
100M <
W
4
FAM65HR51DS1, FAM65HR51DS2
PARAMETER DEFINITIONS
BV
DSS
Q1 – Q4 MOSFET Drain−to−Source Breakdown Voltage
The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain
P−N junction in off state.
V
GS(th)
Q1 – Q4 MOSFET Gate to Source Threshold Voltage
The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at
T
able 3.
R
DS(ON)
Q1 – Q4 MOSFET On Resistance
R
DS(on)
is the total resistance between the source and the drain during the on state.
g
FS
Q1 – Q4 MOSFET Forward Transconductance
Transconductance is the gain in the MOSFE
T
,
e
xpressed in the Equation below.
It describes the change in drain current by the change in the gate−source bias voltage: g
= [ −
D
I /
D
V ]
fs
DS
GS VDS
I
GSS
Q1 – Q4 MOSFET Gate−to−Source Leakage Current
The current flowing from Gate to Source at the maximum allowed V
GS
I
DSS
Q1 – Q4 MOSFET Drain−to−Source Leakage Current
Drain – Source current is measured in off state while providing the maximum allowed drain−to
–
source voltage and the
gate is shorted to the source.
I
DSS
has a positive temperature coefficient
.
5
FAM65HR51DS1, FAM65HR51DS2
Figure 3. Timing Measurement Variable Definition
Table 7. PARAMETER OF SWITCHING CHARACTERISTICS
Turn−On Delay (t
):
d(on)
This is the time needed to charge the input capacitance, Ciss, before the load current I
D
starts flowing.
Rise Time (t ):
The rise time is the time to discharge output capacitance, Coss.
After that time the MOSFET conducts the given load current I
D
.
r
Turn−On Time (t
):
Is the sum of turn−on−delay and rise time
on
Turn−Off Delay (t
):
d(off)
td(off) is the time to discharge Ciss after the MOSFET is turned off.
During this time the load current I
D
is still flowing
Fall Time (t ):
f
The fall time, tf, is the time to charge the output capacitance, Coss.
During this time the load current drops down and the voltage V
DS
rises accordingly.
Turn−Off Time (t
):
Is the sum of turn−off−delay and fall time
off
6
FAM65HR51DS1, FAM65HR51DS2
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
40
35
30
25
20
15
V
GS
= 10 V
10
R
= 0.92
°
C/W
q
JC
0.2
0
5
0
0
3
0
25
50
75
100
125
150
25
50
75
100
125
150
175
T ,
CASE TEMPERATURE (
°
C)
T ,
CASE TEMPERATURE (
°
C)
C
C
Figure 4. Normalized Power Dissipation vs.
Case
Figure 5. Maximum Continuous I
D
vs. Case
Temperature
V =
0 V
GS
60
50
40
30
20
V
= 20 V
DS
100
10
1
T =
25
°
C
J
T =
150
°
C
T =
25
°
C
J
J
0.1
T =
150
°
C
J
10
0
T =
−55
°
C
J
0.01
4
5
6
7
8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
V
, BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 6. Transfer Characteristics
Figure 7. Forward Diode
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
V
GS
= 15 V
10 V
8.0 V
V
= 15 V
GS
10 V
7.0 V
6.0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
5.5 V
5.0 V
10
0
10
0
1
2
3
4
5
6
7
8
9
10
0
10 20 30
40 50 60 70
80 90
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 8. Saturation (25
5
C)
Figure 9. Saturation (150
5
C)
7
FAM65HR51DS1, FAM65HR51DS2
TYPICAL CHARACTERISTICS
200
150
100
2.5
I
V
= 20 A
I
D
= 20 A
D
= 10 V
GS
2.0
1.5
1.0
T =
150
°
C
J
T =
25
°
C
J
50
0
0.5
0
5.5
6.5
7.5
8.5
9.5
−75 −50 −25
0
25
50 75
100 125 150
175
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (
°
C)
J
Figure 10. On−Resistance vs. Gate−to−Source
Voltage
Figure 11. R
DS(norm)
vs. Junction Temperature
1.2
1.0
1.2
1.1
1.0
I
D
= 3.3 mA
I =
10 A
D
0.8
0.6
0.9
0.8
−75 −50
−25
0
25 50 75
100 125 150 175
−75 −50
−25
0
25 50 75
100 125
150 175
T ,
AMBIENT TEMPERATURE (
°
C)
A
T ,
AMBIENT TEMPERATURE (
°
C)
A
Figure 12. Normalized V
th
vs. Temperature
Figure 13. Breakdown Voltage vs. Temperature
30
25
20
15
10
100K
10K
1K
C
ISS
C
C
OSS
100
RSS
V
= 0 V
GS
10
1
5
0
f = 1 MHz
0
100
200
300
400
500
600
700
0.1
1
10
100
1000
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 14. Eoss vs. Drain−to−Source Voltage
Figure 15. Capacitance Variation
8
FAM65HR51DS1, FAM65HR51DS2
TYPICAL CHARACTERISTICS
10
8
0.060
T
C
= 25
°
C
130 V
0.055
0.050
400 V
V
GS
= 10 V
6
4
V
GS
= 20 V
0.045
0.040
2
0
0
40
80
CHARGE (nC)
120
160
0
20
40
60
80
I ,
DRAIN CURRENT (A)
D
Figure 16. Gate Charge
Figure 17. R
DS(on)
vs. I
D
100
10
For temperatures above 25
°
C
1000
derate peak current as follows:
100
m
s
150
*
T
C
Ǹ
I
+
I
2
125
1 ms
Limited I
82.5 A
DM
100
10
10 ms
1
R
Limit
DS(on)
NOTE:
Duty Factor: D = t
/t
100 ms
100
Thermal Limit
Package Limit
1
2
1 s
Peak T
= P
X Z
X R
+ TC
JC
Single Pulse
q
q
J
DM
JC
0.1
1
10
1000
0.000001 0.0001
0.001
0.01
0.1
1
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
t, RECTANGULAR PULSE DURATION (s)
Figure 18. Safe Operating Area
Figure 19. Peak Current Capability
10
1
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.1
0.01
0.01
Single Pulse
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t, RECTANGULAR PULSE DURATION (sec)
Figure 20. Transient Thermal Impedance
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA
−
A16 / 16LD, AUTOMOTIVE MODULE
CASE MODGF
ISSUE A
DATE 02 MAY 2019
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ =
Lot ID
*This information is generic. Please refer to
AT
Y
W
= Assembly &
T
e
st Location
=
Y
e
ar
= Work Week
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
NNN =
Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON94732G
APMCA
−
A16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2018
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
APMCA
−
B16 / 16LD, AUTOMOTIVE MODULE
CASE MODGJ
ISSUE A
DATE 02 MAY 2019
GENERIC
MARKING DIAGRAM*
XXXX = Specific Device Code
ZZZ =
Lot ID
*This information is generic. Please refer to
XXXXXXXXXXX
ZZZ ATYWW
NNNNNNN
AT
Y
W
= Assembly &
T
e
st Location
=
Y
e
ar
= Work Week
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
NNN =
Serial Number
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON97133G
APMCA
−
B16 / 16LD, AUTOMOTIVE MODULE
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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©
Semiconductor Components Industries, LLC, 2018
ON Semiconductor and
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