onsemi-FCH165N65S3R0-F155
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FCH165N65S3R0
SUPERFET III, Easy Drive
650
V
,
1
9 A, 165 m
W
Description
SUPERFET III MOSFET is ON Semiconductor’s brand-new high
voltage super-junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on-resistance and lower gate
charge performance. This advanced technology is tailored to minimize
conduction loss, provide superior switching performance, and
withstand extreme dv/dt rate. Consequently, SUPERFET III MOSFET
Easy drive series helps manage EMI issues and allows for easier
design implementation.
V
R
MAX
I MAX
D
DSS
DS(ON)
650 V
165 m
W
@ 10 V
19 A
D
Features
•
700 V @ T
= 150
°
C
J
•
Typ. R
= 140 m
W
DS(on)
G
•
Ultra Low Gate Charge (Typ. Q
= 39 nC)
g
•
Low Effective Output Capacitance (Typ. C
•
100% Avalanche Tested
= 341 pF)
oss(eff.)
S
N-Channel MOSFET
Applications
•
Telecom / Server Power Supplies
•
Industrial Power Supplies
•
UPS / Solar
G
D
S
TO
−
247
−
3LD
CASE 340CH
MARKING DIAGRAM
$Y&Z&3&K
FCH165
N65S3R0
$Y
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
&Z
&3
&K
FCH165N65S3R0 =
Specific Device Code
ORDERING INFORMATION
this data sheet.
©
Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
August, 2019
−
Rev. 0
FCH165N65S3R0/D
FCH165N65S3R0
ABSOLUTE MAXIMUM RATINGS
(T =
25
°
C, Unless otherwise specified)
C
Symbol
Parameter
Value
650
Unit
V
V
DSS
V
GSS
Drain to Source Voltage
Gate to Source Voltage
DC
30
V
AC (f > 1 Hz)
30
V
I
D
Drain Current
Continuous (T
= 25
°
C)
19
A
C
Continuous (T
= 100
°
C)
12.3
47.5
87
C
I
Drain Current
A
mJ
A
DM
E
MOSFET dv/dt
AS
AS
I
2.7
E
1.54
100
mJ
V/ns
AR
dv/dt
Power Dissipation
20
P
(T =
25
°
C)
154
W
W/
°
C
°
C
D
C
Derate Above 25
°
C
1.23
−
55 to +150
300
T , T
Operating and Storage
T
e
mperature Range
J
STG
T
Maximum Lead
T
e
mperature for Soldering, 1/8
″
from Case for 5 s
°
C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive
rating: pulse-width limited by maximum junction temperature.
2. I
= 2.7 A, R
= 25
W
, starting T
= 25
°
C.
AS
G
J
3. I
≤
9.5 A, di/dt
≤
200 A/
m
s, V
≤
400 V, starting T
= 25
°
C.
SD
DD
J
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.81
40
Unit
R
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
_
C/W
q
JC
JA
R
q
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Shipping
30 Units / Tube
FCH165N65S3R0
−
F155
FCH165N65S3R0
TO
−
247
−
3LD
2
FCH165N65S3R0
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
650
700
V
V
V
V
I
= 0
V
, I
= 1 mA, T
= 25
_
C
DSS
GS
D
J
= 0
V
, I
= 1 mA, T
= 150
_
C
GS
D
J
D
BV
/
D
T
Breakdown Voltage
T
e
mperature
Coefficient
= 1 mA, Referenced to 25
_
C
0.64
0.85
V/
_
C
DSS
J
D
I
Zero Gate Voltage Drain Current
V
DS
V
DS
V
GS
= 650
V
, V
= 0 V
1
m
A
DSS
GS
= 520
V
, T
=
1
25
_
C
C
I
Gate to Body Leakage Current
=
30
V
, V
= 0 V
100
nA
GSS
DS
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
GS
V
GS
V
DS
= V
, I
= 0.44 mA
2.5
4.5
V
m
W
S
GS(th)
DS(on)
DS
D
R
Static Drain to Source On Resistance
Forward Transconductance
= 10
V
, I
=
9
.5 A
140
12
165
D
g
FS
= 20
V
, I
=
9
.5 A
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 400
V
, V
= 0 V, f = 1
M
Hz
1500
35
pF
pF
pF
pF
nC
nC
nC
W
iss
DS
GS
C
Output Capacitance
oss
C
Effective Output Capacitance
Energy Related Output Capacitance
T
o
tal Gate Charge at 10 V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Equivalent Series Resistance
V
DS
V
DS
V
DS
= 0 V to 400 V, V
= 0 V
341
49
oss(eff.)
GS
C
= 0 V to 400 V, V
= 0 V
GS
oss(er.)
Q
= 400
V
, I
=
9
.5 A, V
= 10 V
39
g(tot)
D
GS
Q
11
gs
Q
16
gd
ESR
f = 1 MHz
0.5
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
V
V
= 400
V
, I
=
9
.5 A,
17
15
44
5
ns
ns
ns
ns
d(on)
DD
GS
D
= 10
V
, R
=
4
.7
W
g
t
r
t
d(off)
t
f
SOURCE-DRAIN DIODE CHARACTERISTICS
I
Maximum Continuous Source to Drain Diode Forward Current
Maximum Pulsed Source to Drain Diode Forward Current
19
47.5
1.2
A
A
V
S
I
SM
V
SD
Source to Drain Diode Forward
Voltage
V
GS
= 0
V
, I
=
9
.5 A
SD
t
Reverse Recovery Time
V
= 400
V
, I
=
9
.5 A,
339
5.8
ns
rr
DD
F
SD
dI /dt
= 100 A/
m
s
Q
Reverse Recovery Charge
m
C
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially
independent of operating temperature typical characteristics.
3
FCH165N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS
50
50
10
*Notes:
V
GS
= 10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
1. V
= 20 V
DS
2. 250
m
s Pulse
T
e
st
5.5 V
10
150
°
C
25
°
C
−
55
°
C
*Notes:
1. 250
m
s Pulse
T
e
st
2. T
= 25
°
C
C
1
1
3
4
5
6
7
8
9
0.2
1
10
V
GS
, Gate
−
Source Voltage [V]
V
DS
, Drain
−
Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.4
0.3
0.2
100
10
*Notes:
*Note: T
= 25
°
C
C
1. V
= 0 V
GS
2. 250
m
s Pulse
T
e
st
150
°
C
1
25
°
C
V
GS
= 10 V
0.1
V
GS
= 20 V
−
55
°
C
0.1
0.0
0.01
1E
−
3
0
10
20
30
40
0.0
0.5
1.0
1.5
V
SD
, Body Diode Forward Voltage [V]
I
D
, Drain Current [A]
Figure 3. On-Resistance Variation vs. Drain
Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
100000
10
*Note: I
= 9.5 A
D
10000
1000
100
8
6
4
2
0
C
iss
V
DS
= 130 V
V
= 400 V
DS
C
oss
*Notes:
10
1. V
= 0 V
GS
2. f = 1 MHz
C
C
C
= C
+ C
(C =
Shorted)
gs gd
ds
= C
+ C
= C
C
rss
iss
1
oss
rss
ds
gd
gd
0.1
0.1
1
10
100
1000
0
10
20
30
40
Q
g
, Total Gate Charge [nC]
V
DS
, Drain
−
Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
4
FCH165N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
1.2
1.1
1.0
0.9
0.8
3.0
*Notes:
*Notes:
1. V
= 0 V
1. V
= 10 V
GS
GS
2.5
2. I
= 10 mA
D
2. I
= 9.5 A
D
2.0
1.5
1.0
0.5
0.0
−
50
0
50
100
150
−
50
0
50
100
150
T
J
, Junction Temperature [
o
C]
T
J
, Junction Temperature [
o
C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variant vs. Temperature
20
15
10
5
100
30
m
s
100
m
s
1 ms
10 ms
DC
10
1
Operation in This Area
is Limited by R
DS(on)
*Notes:
0.1
0.01
1. T
= 25
°
C
C
2. T
= 150
°
C
J
3. Single Pulse
0
25
1
10
100
1000
50
75
100
125
150
T
C
, Case Temperature
[
o
C]
V
DS
, Drain
−
Source Voltage [V]
Figure 9. Maximum Safe Operation Area
Figure 10. Maximum Drain Current
vs. Case Temperature
8
6
4
2
0
0
130
260
390
520
650
V
DS
, Drain to Source Voltage [V]
Figure 11. E
OSS
vs. Drain to Source Voltage
5
FCH165N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
2
1
DUTY CYCLE
−
DESCENDING ORDER
D = 0.5
0.2
0.1
P
DM
0.1
0.01
0.05
0.02
0.01
t
1
t
2
NOTES:
Z
R
(t) = r(t) x R
o
q
JC
q
JC
= 0.81
C/W
q
JC
SINGLE PULSE
10
−
4
Peak T
= P
Duty Cycle, D = t
/ t
x Z
(t) + T
J
DM
q
JC C
1
2
0.001
10
−
5
10
−
3
10
−
2
10
−
1
10
0
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Transient Thermal Response Curve
6
FCH165N65S3R0
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 13. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 14. Resistive Switching Test Circuit & Waveforms
L
2
1
2
E
AS
+
@
LI
AS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
7
FCH165N65S3R0
+
DUT
V
SD
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
−
dv/dt controlled by R
G
−
I controlled
by pulse period
SD
Gate Pulse Width
D
+
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO
−
247
−
3LD
CASE 340CH
ISSUE A
DATE 09 OCT 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
XXXX = Specific Device Code
A
Y
= Assembly Location
=
Y
e
ar
WW =
Work Week
G
= Pb
−
Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13853G
TO
−
247
−
3LD
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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©
Semiconductor Components Industries, LLC, 2018
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