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November 2013
FCI7N60
N-Channel SuperFET
MOSFET
®
600 V, 7 A, 600 m
Ω
Features
Description
•
•
•
•
•
•
650V @ T
J
= 150°C
SuperFET
®
MOSFET is Fairchild Semiconductor’s first genera-
tion of high voltage super-junction (SJ) MOSFET family that is
utilizing charge balance technology for outstanding low on-
resistance and lower gate charge performance. This technology
is tailored to minimize conduction loss, provide superior switch-
ing performance, dv/dt rate and higher avalanche energy. Con-
sequently, SuperFET MOSFET is very suitable for the switching
power applications such as PFC, server/telecom power, FPD
TV power, ATX power and industrial power applications.
Typ. R
DS(on)
= 530 m
Ω
Ultra Low Gate Charge (Typ. Q
g
= 23 nC)
Low Effective Output Capacitance (Typ. C
oss(eff.)
= 60 pF)
100% Avalanche
T
e
sted
RoHS compliant
Application
•
•
•
Lighting
Solar Inverter
AC-DC Power Supply
D
G
G
I
2
-PAK
D
S
S
MOSFET Maximum Ratings
T
C
= 25
o
C unless otherwise noted.
Symbol
V
DSS
Parameter
FCI7N60
Unit
Drain to Source Voltage
Drain Current
600
V
– Continuous (T
C
= 25
o
C)
– Continuous (T
C
= 100
o
C)
– Pulsed
7
4.4
I
D
A
I
DM
Drain Current
(Note 1)
21
A
V
V
GSS
E
AS
I
AR
Gate to Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
±30
230
7
(Note 2)
(Note 1)
(Note 1)
(Note 3)
mJ
A
E
AR
dv/dt
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
8.3
mJ
V/ns
W
W/
o
C
o
C
4.5
(T
C
= 25
o
C)
– Derate Above 25
o
C
83
P
D
Power Dissipation
0.67
-55 to +150
300
T
J
, T
STG
T
L
Operating and Storage
T
e
mperature Range
Maximum Lead
T
e
mperature for Soldering, 1/8” from Case for 5 Seconds
o
C
Thermal Characteristics
Symbol
Parameter
FCI7N60
1.5
Unit
o
C/W
o
C/W
R
θ
JC
R
θ
JA
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
62.5
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
1
Package Marking and Ordering Information
Part Number
Top Mark
Package
I
2
-PAK
Packing Method
Reel Size
Tape Width
Quantity
FCI7N60
FCI7N60
Tube
N/A
N/A
50 units
Electrical Characteristics
T
C
= 25
o
C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Off Characteristics
V
GS
= 0 V, I
D
= 250
μ
A, T
C
= 25
o
C
V
GS
= 0 V, I
D
= 250
μ
A, T
C
= 150
o
C
600
–
–
–
–
V
V
BV
DSS
Drain to Source Breakdown Voltage
650
Δ
BV
DSS
/
Δ
T
J
BV
DS
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, Referenced to 25
o
C
–
–
0.6
–
–
V/
o
C
Drain-Source Avalanche Breakdown
Voltage
V
GS
= 0 V, I
D
= 7 A
700
V
V
DS
= 600 V, V
GS
= 0 V
–
–
–
–
–
–
1
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Body Leakage Current
μ
A
V
DS
= 480 V, T
C
= 125
o
C
10
V
GS
= ±30 V, V
DS
= 0 V
±100
nA
On Characteristics
V
GS(th)
R
DS(on)
g
FS
Gate Threshold Voltage
V
GS
= V
DS
, I
D
= 250
μ
A
V
GS
= 10 V, I
D
= 3.5 A
V
DS
= 40 V, I
D
= 3.5 A
3.0
–
0.53
6
5.0
0.6
–
V
Ω
S
Static Drain to Source On Resistance
Forward Transconductance
–
–
Dynamic Characteristics
C
iss
Input Capacitance
–
–
–
–
–
710
380
34
920
500
–
pF
pF
pF
pF
pF
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
Output Capacitance
C
oss
V
DS
= 480 V, V
GS
= 0 V, f = 1 MHz
V
DS
= 0 V to 400
V
,
V
GS
= 0 V
22
29
–
C
oss(eff.)
Effective Output Capacitance
60
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
–
–
–
–
–
–
–
35
55
80
120
160
75
ns
ns
V
DD
= 300 V, I
D
= 7 A,
Turn-On Rise Time
V
GS
= 10 V, R
G
= 25
Ω
Turn-Off Delay Time
75
ns
Turn-Off Fall Time
32
ns
(Note 4)
(Note 4)
Q
g(tot)
Q
gs
Q
gd
T
o
tal Gate Charge at 10V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
23
30
nC
nC
nC
V
V
DS
= 480 V, I
D
= 7 A,
GS
= 10 V
4.2
11.5
5.5
–
Drain-Source Diode Characteristics
I
S
Maximum Continuous Drain to Source Diode Forward Current
Maximum Pulsed Drain to Source Diode Forward Current
–
–
–
–
–
–
–
7
21
1.4
–
A
A
I
SM
V
SD
t
rr
Drain to Source Diode Forward Voltage
Reverse Recovery Time
V
GS
= 0 V, I
SD
= 7 A
–
V
360
4.5
ns
μ
C
V
GS
= 0 V, I
SD
= 7 A,
dI
F
/dt = 100 A/
μ
s
Q
rr
Reverse Recovery Charge
–
Notes:
1. Repetitive rating: pulse-width limited by maximum junction temperature.
2. I
= 3.5 A, V
= 50
V
, R
=
2
5
Ω
, starting T
= 25
°
C.
AS
DD
G
J
3. I
≤
7 A, di/dt
≤
200 A/
μ
s, V
≤
BV
, starting T
= 25
°
C.
SD
DD
DSS
J
4. Essentially independent of operating temperature typical characteristics.
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
2
Typical Performance Characteristics
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
V
GS
Top :
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
10
1
10
1
10
0
10
-1
Bottom :
5.5 V
150
°
C
25
°
C
10
0
-55
°
C
* Notes :
1. 250
μ
s Pulse Test
2. T
C
= 25
°
C
* Note
1. V
DS
= 40V
2. 250
μ
s Pulse Test
10
-1
10
-1
10
0
10
1
2
4
6
8
10
V
GS
, Gate-Source Voltage
[V]
V
DS
, Drain-Source Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperatue
2.0
1.8
1.6
1.4
10
1
V
GS
= 10V
1.2
1.0
0.8
10
0
150
°
C
25
°
C
0.6
V
GS
= 20V
0.4
* Notes :
1. V
GS
= 0V
0.2
2. 250
μ
s Pulse Test
* Note : T
J
= 25
°
C
10
-1
0.2
0.0
0
5
10
15
20
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V
SD
, Source-Drain Voltage
[V]
I
D
, Drain Current [A]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
3000
12
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
V
DS
= 100V
C
oss
= C
ds
+ C
gd
C
rss
= C
gd
V
DS
= 250V
10
V
DS
= 400V
2000
1000
0
8
C
oss
6
4
2
* Notes :
1. V
GS
= 0 V
C
iss
2. f = 1 MHz
C
rss
* Note : I
D
= 7A
20
0
10
-1
10
0
10
1
0
5
10
15
25
V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
3
Typical Performance Characteristics
(Continued)
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
* Notes :
1. V
GS
= 0 V
0.9
0.8
* Notes :
1. V
GS
= 10 V
2. I
D
= 250
μ
A
2. I
D
= 3.5 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
°
C]
T
J
, Junction Temperature [
°
C]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
10.0
7.5
5.0
2.5
0.0
10
2
Operation in This Area
is Limited by R
DS(on)
100 us
1 ms
10 ms
10
1
10
0
DC
* Notes :
1. T
C
= 25
°
C
10
-1
2. T
J
= 150
°
C
3. Single Pulse
10
-2
10
0
10
1
10
2
10
3
25
50
75
100
125
150
V
DS
, Drain-Source Voltage [V]
T
C
, Case Temperature [
°
C]
Figure 11. Transient Thermal Response Curve
10
0
10
-1
10
-2
D
=
0.5
0.2
* N
o
tes
1. Z
θ
J
C
(t)
2. D
uty Factor, D
=t
1
/t
2
:
=
1.5
°
C /W
M ax.
0.1
0.05
0.02
3. T
J
M
–
T
C
=
P
D
M
*
Z
θ
J
C
(t)
P
DM
0.01
t
1
t
2
single pulse
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
,
S
quare W
ave Pulse Duration [sec]
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
4
V
GS
Same Type
as DUT
50K
Ω
Q
g
12V
200nF
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
I
= const.
G
Charge
Figure 12. Gate Charge Test Circuit & Waveform
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
V
GS
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Figure 13. Resistive Switching Test Circuit & Waveforms
BV
DSS
——————–
BV
DSS
– V
DD
L
1
2
2
—-
E
AS
=
L I
AS
V
DS
I
D
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
V
DS
(t)
V
DD
DUT
G
S
t
p
t
p
Time
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
5
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
©2008 Fairchild Semiconductor Corporation
FCI7N60 Rev. C1
6
10.29
9.65
A
4.83
4.06
B
8.33
6.22
1.40
1.14
1.40
1.00
7°
7.88
6.86
9.65
8.64
5°
5°
2
1
3
3.96
2.80
B
2.13
14.73
12.70
2.79
2.03
1.78
1.14
SEE NOTE “G”
B
0.64
0.33
B
2.54
0.90
0.64
B
5.08
M
0.254 A
B
NOTES:
A. EXCEPT WHERE NOTED CONFORMS TO
TO262 JEDEC VARIATION AA.
B
DOES NOT COMPLY JEDEC STD. VALUE.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS.
E. DIMENSION AND TOLERANCE AS PER ANSI
Y14.5-1994.
F. LOCATION OF PIN HOLE MAY VARY
(LOWER LEFT CORNER, LOWER CENTER
AND CENTER OF PACKAGE)
G. MAXIMUM WIDTH FOR F102 DEVICE = 1.35 MAX.
H. DRAWING FILE NAME: TO262A03REV6
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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