onsemi-FDBL86366-F085

Part #onsemi-FDBL86366-F085
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onsemi-FDBL86366-F085

MOSFET

– POWERTRENCH

)  

N-Channel  
80
V
,
2
20 A, 3.0 m
W
 
FDBL86366-F085  
Features  
•
Typical R  
•
Typical Q  
•
UIS Capability  
•
AEC
−
Q101 Qualified and P
P
A
P Capable  
•
These Devices are Pb
−
Free and are RoHS Compliant  
= 2.4 m
ꢀ
at V
 
= 10
V
, I
 
=
8
0 A  
GS D  
DS(on)  
= 86 nC at V
 
= 10
V
, I
 
=
8
0 A  
g(tot)  
GS  
D
D
Applications  
G
•
Automotive Engine Control  
•
PowerTrain Management  
•
Solenoid and Motor Drivers  
•
Integrated Starter/Alternator  
•
Primary Switch for 12 V Systems  
S
N
−
Channel  
MOSFET MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
J
Symbol  
Parameter  
Drain
−
to
−
Source Voltage  
Gate
−
to
−
Source Voltage  
Drain Current
−
Continuous  
Ratings  
80  
Unit  
V
V
DSS  
V
A
V
GS  
20  
H
−
PSOF8L  
CASE 100CU  
I
D
220  
(V =
 
10), T
 
= 25
°

GS  
C
205  
Pulsed Drain Current, T
 
= 25
°
C  
MARKING DIAGRAM  
C
mJ  
E
AS  
Single Pulse Avalanche Energy  
W
P
300  
2.0  
Power Dissipation  
D
$Y&Z&3&K  
FDBL  
86366  
W/
°
C  
°
C  
Derate Above 25
°
C  
T , T  
−
55 to +175  
0.5  
Operating and Storage
T
e
mperature  
Thermal Resistance, Junction to Case  
J
STG  
°
C/W  
°
C/W  
R
ꢁ
ꢁ
JC  
R
43  
Maximum Thermal Resistance,  
JA  
$Y  
&Z  
&3  
&K  
= ON Semiconductor Logo  
= Assembly Plant Code  
= Numeric Date Code  
= Lot Code  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
1. Current
 
is limited by silicon.  
FDBL86366  
= Specific Device Code  
2. Starting
 
T =
 
25
°
C, L = 0.1 mH, I
 
= 64 A, V
 
= 80 V during inductor charging  
J
AS  
DD  
and V
 
= 0 V during time in avalanche.  
DD  
3. R  
is the sum of the junction
−
to
−
case and case
−
to
−
ambient thermal  
ꢁ
JA  
ORDERING INFORMATION  
resistance, where the case thermal reference is defined as the solder  
{
mounting surface of the drain pins. R  
is guaranteed by design, while R  
ꢁ
JA  
Device  
Top Mark  
Package Shipping  
ꢁ
JC  
is determined by the board design. The maximum rating presented here is  
FDBL86366 FDBL86366
 
H
−
PSOF8L 2000
 
Units/  
2
based on mounting on a 1 in
 
pad of 2oz copper.  
−
F085  
T
a
pe&Reel  
*For additional information on our Pb
−
Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
T
e
chniques Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
January, 2020
−
Rev. 3  
FDBL86366
−
F085/D  
 

FDBL86366
−
F085  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise noted)  
J
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
OFF CHARACTERISTICS  
BV  
I
Drain
−
to
−
Source Breakdown Voltage  
Drain
−
to
−
Source Leakage Current  
I
= 250
ꢂ
A, V
 
= 0 V  
80  
−
−
−
−
−
−
1
V
DSS  
D
GS  
V
V
= 80
V
,  
= 0 V  
T =
 
25
°
C  
J
ꢂ
A  
mA  
nA  
DSS  
DS  
GS  
T =
 
175
°

J
−
1
I
Gate
−
to
−
Source Leakage Current  
V
=
20 V  
−
100  
GSS  
GS  
ON CHARACTERISTICS  
V
R
Gate to Source Threshold Voltage  
Drain to Source on Resistance  
V
I
= V
 
, I
 
= 250
ꢂ
A  
2.0  
−
3.0  
2.4  
4.9  
4.0  
3.0  
6.1  
V
GS(th)  
GS  
DS  
D
= 80 A,  
= 10 V  
T =
 
25
°
C  
J
m
ꢀ  
ꢀ
DS(on)  
D
V
GS  
T =
 
175
°

−
m
J
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
= 40
V
, V
 
= 0 V, f = 1
M
Hz  
−
−
−
−
−
−
−
−
6320  
1030  
32  
−
−
pF  
iss  
DS  
GS  
C
Output Capacitance  
pF  
pF  
ꢀ
oss  
C
Reverse Transfer Capacitance  
Gate Resistance  
−
rss  
R
f = 1 MHz  
2.1  
86  
−
g
Q
T
o
tal Gate Charge at 10 V  
Threshold Gate Charge  
Gate
−
to
−
Source Gate Charge  
Gate
−
to
−
Drain “Miller” Charge  
V
GS  
V
GS  
V
DD  
= 0 to 10 V  
= 0 to 2 V  
V =
 
64
V
,  
DD  
D
112  
18  
−
nC  
nC  
nC  
nC  
g(
T
o
T)  
I
= 80 A  
Q
12  
g(th)  
Q
= 64
V
, I
 
=
8
0 A  
30  
gs  
D
Q
18  
−
gd  
SWITCHING CHARACTERISTICS  
t
Turn
−
On Time  
Turn
−
On Delay  
Rise Time  
V
DD  
V
GS  
= 40
V
, I
 
=
8
0 A,  
−
−
−
−
−
−
−
98  
−
ns  
ns  
ns  
ns  
ns  
ns  
on  
D
= 10
V
, R  
= 6  
ꢀ
GEN  
t
t
30  
34  
40  
17  
−
d(on)  
t
r
−
Turn
−
Off Delay  
Fall Time  
−
d(off)  
t
f
−
t
Turn
−
Off Time  
86  
off  
DRAIN
−
SOURCE DIODE CHARACTERISTIC  
V
Source
−
to
−
Drain Diode Voltage  
I
I
= 80 A, V
 
= 0 V  
−
−
−
−
−
−
1.25  
1.2  
V
V
SD  
SD  
GS  
= 40 A, V
 
= 0 V  
SD  
GS  
t
Reverse
−
Recovery Time  
Reverse
−
Recovery Charge  
I =
 
80 A, dI
 
/dt = 100 A/
ꢂ
s,  
F
V
80  
95  
120  
140  
ns  
nC  
rr  
SD  
= 64 V  
DD  
Q
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
4. The
 
maximum value is specified by design at T
 
= 175
°
C. Product is not tested to this condition in production.  
J
2
 

FDBL86366
−
F085  
TYPICAL CHARACTERISTICS  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
250  
200  
150  
V
GS  
= 10 V  
Current limited  
by silicon  
100  
50  
0
0
25  
50  
75  
100  
125  
150  
175  
25  
50  
75  
100  
125  
150  
175  
200  
T ,
 
Case
T
e
mperature [
°
C]  
C
T ,
 
Case
T
e
mperature [
°
C]  
C
Figure 1. Normalized Power Dissipation  
vs. Case Temperature  
Figure 2. Maximum Continuous Drain Current  
vs. Case Temperature  
2
1
DUTY CYCLE
−
DESCENDING ORDER  
D = 0.50  
0.20  
0.10  
0.05  
0.02  
P
DM  
0.01  
0.1  
t
1
t
2
NOTES:  
Duty factor: D = t
 
/ t  
SINGLE PULSE  
1
2
Peak T
 
= P  
×
Z  
ꢁ
×
R  
+ T  
JA C  
ꢁ
J
DM  
JA  
0.01  
−
5  
−
4  
−
3  
−
2  
−
1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, Rectangular Pulse Duration (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
10000  
1000  
100  
T 25
°
C  
C =  
For temperatures  
above 25
°
C derate peak  
current as follows:  
V
GS  
= 10 V  
175
*
T  
C
Ǹ

I
+
I

ƪ ƫ  
2
150  
SINGLE PULSE  
10  
−
5  
−
4  
−
3  
−
2  
−
1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, Rectangular Pulse Duration (s)  
Figure 4. Peak Current Capability  
3

FDBL86366
−
F085  
TYPICAL CHARACTERISTICS
(continued)  
1000  
1000  
100  
10  
If R = 0  
t
= (L)(I
 
) / (1.3
×
Rated BV
 
V  
)
AV  
AS  
DSS
−
DD  
If R
≠
0  
t
= (L/R)ln[(I
 
×
R) / (1.3
×
Rated BV  
−
V )
 
+ 1]  
DSS DD  
AV  
AS  
100  
10  
1
100
ꢂ
s  
Operation in this  
area may be  
Starting T
 
= 25
°
C  
J
limited by r  
DS(on)  
1
1 ms  
Starting T
 
= 150
°
C  
J
SINGLE PULSE  
10 ms  
100 ms  
T
T
= max rated  
= 25
°
C  
J
C
0.1  
0.1  
1
10  
100  
500  
0.001  
0.01  
0.1  
1
10  
100  
1000  
V
DS  
, Drain to Source Voltage [V]  
t ,
 
Time in Avalanche [ms]  
AV  
NOTE: Refer to ON Semiconductor Application Notes

and

.  
Figure 5. Forward Bias Safe Operating Area  
Figure 6. Unclamped Inductive Switching Capability  
300  
300  
Pulse duration = 80
ꢂ
s  
V
GS  
= 0 V  
Duty cycle = 0.5% MAX  
100  
10  
1
250  
200  
150  
V
DD  
= 5 V  
T
= 175
°
C  
J
T
J
= 25
°
C  
T
J
= 25
°
C  
100  
50  
T
J
=
−
55
°
C  
T
J
= 175
°
C  
0
2
0.1  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
3
4
5
6
7
8
V
GS  
, Gate to Source Voltage [V]  
V
SD  
, Body Diode Forward Voltage [V]  
Figure 7. Transfer Characteristics  
Figure 8. Forward Diode Characteristics  
300  
300  
V
GS  
V
GS  
15 V
T
o
p  
10 V  
8 V  
7 V  
6 V  
15 V
T
o
p  
10 V  
8 V  
7 V  
6 V  
250  
200  
150  
100  
50  
250  
200  
150  
80
ꢂ
s Pulse Width  
5.5 V  
5 V Bottom  
5.5 V  
5 V Bottom  
T
J
= 25
°
C  
100  
50  
80
ꢂ
s Pulse Width  
T
J
= 175
°
C  
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
DS  
, Drain to Source Voltage [V]  
V
DS  
, Drain to Source Voltage [V]  
Figure 9. Saturation Characteristics  
Figure 10. Saturation Characteristics  
4

FDBL86366
−
F085  
TYPICAL CHARACTERISTICS
(continued)  
50  
40  
2.4  
I
D
= 80 A  
Pulse duration = 80
ꢂ
s  
Duty cycle = 0.5% MAX  
Pulse duration = 80
ꢂ
s  
Duty cycle = 0.5% MAX  
2.0  
1.6  
1.2  
30  
20  
10  
0
T
J
= 25
°
C  
T
J
= 175
°
C  
0.8  
0.4  
I
= 80 A  
D
V
= 10 V  
GS  
4
6
8
10  
−
80  
−
40  
0
40  
80  
120  
160  
200  
V
GS  
, Gate to Source Voltage [V]  
T , Junction
T
e
mperature [
°
C]  
J
Figure 11. R

DSON

vs. Gate Voltage  
Figure 12. Normalized R

DSON

vs. Junction Temperature  
1.5  
1.2  
0.9  
0.6  
0.3  
0.0  
1.10  
I
D
= 5 mA  
V
D
= V  
DS  
GS  
I
= 250
ꢂ
A  
1.05  
1.00  
0.95  
0.90  
−
80  
−
40  
0
40  
80  
120  
160  
200  
−
80  
−
40  
0
40  
80  
120  
160  
200  
T , Junction
T
e
mperature [
°
C]  
J
T , Junction
T
e
mperature [
°
C]  
J
Figure 13. Normalized Gate Threshold Voltage  
vs. Temperature  
Figure 14. Normalized Drain to Source  
Breakdown Voltage vs. Junction Temperature  
10  
10000  
I
D
= 80 A  
C
iss  
V
DD  
= 40 V  
8
1000  
100  
10  
V
= 32 V  
V
DD  
= 48 V  
DD  
6
4
C
C
oss  
rss  
2
0
f = 1 MHz  
GS  
V
= 0 V  
0.1  
1
10  
100  
0
20  
40  
60  
80  
100  
Q ,
 
Gate Charge [nC]  
g
V
DS  
, Drain to Source Voltage [V]  
Figure 15. Capacitance vs. Drain to Source Voltage  
Figure 16. Gate Charge vs. Gate to Source Voltage  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other  
countries.  
5

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
H
−
PSOF8L 11.68×9.80  
CASE 100CU  
ISSUE A  
DATE 06 JAN 2020  
GENERIC  
MARKING DIAGRAM*  
AYWWZZ  
XXXXXXXX  
XXXXXXXX  
A
Y
= Assembly Location  
=
Y
e
ar  
*This information is generic. Please refer to  
device data sheet for actual part marking.  
Pb
−
Free indicator, “G” or microdot “
G
”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
WW =
 
Work Week  
ZZ  
XXXX = Specific Device Code  
= Assembly Lot Code  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13813G  
H
−
PSOF8L 11.68×9.80  
PAGE 1 OF 1  
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©
Semiconductor Components Industries, LLC, 2019  

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