onsemi-FDC699P
| Part # | onsemi-FDC699P |
Download  | onsemi-FDC699P |
January 2004
FDC699P
P-Channel 2.5V
PowerTrench MOSFET
General Description
Features
This P-Channel 2.5V specified MOSFET is a rugged
gate version of Fairchild Semiconductor’s advanced
PowerTrench process. It has been optimized for power
management applications with a wide range of gate
drive voltage (2.5V – 12V).
•
–7 A, –20 V
R
DS(ON)
= 22 m
Ω
@ V
GS
= –4.5 V
R
DS(ON)
= 30 m
Ω
@ V
GS
= –2.5 V
•
High performance trench technology for extremely
low R
DS(ON)
•
Fast switching speed
Applications
•
FLMP SuperSOT-6 package:
Enhanced thermal
performance in industry-standard package size
•
•
•
Battery management
Load Switch
Battery protection
G
6
4
1
2
3
S
S
5
S
S
Bottom Drain
S
SuperSOT-6
TM
FLMP
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
–20
V
V
A
V
GSS
I
D
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
±
12
–7
–40
(Note 1a)
Power Dissipation
(Note 1a)
(Note 1b)
2
1.5
P
D
W
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°
C
Thermal Characteristics
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
60
111
0.5
R
θ
JA
°
C/W
Thermal Resistance, Junction-to-Case
R
θ
JC
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
.699
FDC699P
7’’
8mm
3000 units
FDC699P Rev
C2 (W)
2004 Fairchild Semiconductor Corporation
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
–20
V
V
GS
= 0 V,
I
D
= –250
µ
A
∆
BV
DSS
Breakdown Voltage Temperature
–12
I
D
= – 250
µ
A, Referenced to 25
°
C
mV/
°
C
Coefficient
∆
T
J
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate–Body Leakage
V
DS
= –16 V,
V
GS
= 0 V
V
GS
=
±
12 V,
V
DS
= 0 V
–1
±
100
µ
A
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
–0.6
–0.9
3
–1.5
V
V
DS
= V
GS
I
D
= – 250
µ
A, Referenced to 25
°
C
,
I
D
= –250
µ
A
∆
V
GS(th)
Gate Threshold Voltage
mV/
°
C
Temperature Coefficient
∆
T
J
R
DS(on)
Static Drain–Source
On–Resistance
V
GS
= –4.5 V,
I
D
= –7 A
V
GS
= –2.5 V, I
D
= –6 A
14
21
17
22
30
31
m
Ω
V
GS
= –4.5 V, I
D
= –7 A, T
J
=125
°
C
g
FS
Forward Transconductance
V
DS
= –5 V,
I
D
= –7 A
30
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
2640
560
280
3.6
pF
pF
pF
Ω
V
DS
= – 10 V,
V
GS
= 0 V,
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
f = 1.0 MHz
V
GS
= 15 mV,
f = 1.0 MHz
Switching Characteristics
(Note 2)
V
DD
= –10 V,
I
D
= –1 A,
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
16
11
75
41
27
5
28
19
120
65
ns
ns
ns
V
GS
= –4.5 V,
R
GEN
= 6
Ω
ns
V
DS
= –10 V,
I
D
= –7 A,
V
GS
= –5 V
Q
g
Q
gs
Q
gd
38
nC
nC
nC
7
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
–1.6
–1.2
A
V
V
SD
V
GS
= 0 V,
I
S
= –1.6 A
(Note 2)
–0.7
Voltage
t
rr
Reverse Recovery Time
28
14
ns
nC
I
F
= –7 A,
d
iF
/d
t
= 100 A/µs
Q
rr
Reverse Recovery Charge
Notes: 1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting
surface of the drain pins.
R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user’s board design.
a)
60°C/W when
b)
111°C/W when mounted
on a minimum pad of 2 oz
copper
mounted on a 1in
2
pad
of 2 oz copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%
FDC699P Rev C2 (W)
Dimensional Outline and Pad Layout
Bottom View
Top View
Recommended Landing Pattern
FDC699P Rev C2 (W)
Typical Characteristics
40
2.8
2.6
2.4
2.2
2
V
GS
= -4.5V
-3.5V
-3.0V
-2.5V
V
GS
= -2.0V
30
20
10
0
1.8
1.6
1.4
1.2
1
-2.0V
-2.5V
-3.0V
-3.5V
-4.0V
-4.5V
0.8
0
10
20
-I
D
, DRAIN CURRENT (A)
30
40
0
0.5
1
1.5
2
2.5
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.05
1.4
1.3
1.2
1.1
1
I
D
= -3.5A
I
D
= -7A
0.045
0.04
V
GS
= -4.5V
0.035
0.03
T
A
= 125
o
C
0.025
0.02
T
A
= 25
o
C
0.9
0.8
0.015
0.01
1
2
3
4
5
-50
-25
0
25
50
75
100
125
150
-V
GS
, GATE TO SOURCE VOLTAGE (V)
T
J
, JUNCTION TEMPERATURE (
o
C)
Figure 3. On-Resistance Variation
withTemperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
40
30
20
10
0
100
V
GS
= 0V
V
DS
= -5V
10
1
T
A
= 125
o
C
0.1
25
o
C
25
o
C
0.01
0.001
0.0001
T
A
= 125
o
C
-55
o
C
-55
o
C
0
0.2
0.4
0.6
0.8
1
1.2
0.5
1
1.5
2
2.5
3
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDC699P Rev C2 (W)
Typical Characteristics
5
4000
3500
3000
2500
2000
1500
1000
500
I
D
= -7A
f = 1MHz
V
GS
= 0 V
V
DS
= -5V
-10V
4
3
2
1
0
C
ISS
-15V
C
oss
C
rss
0
0
5
10
15
20
0
5
10
15
20
25
30
Q
g
, GATE CHARGE (nC)
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
50
40
30
20
10
0
100
10
10µs
SINGLE PULSE
R
DS(ON)
LIMIT
R
θ
JA
= 111°C/W
100µs
1ms
10ms
T
A
= 25°C
100ms
1s
10s
DC
1
V
GS
= -4.5V
0.1
0.01
SINGLE PULSE
R
θ
JA
= 111
o
C/W
T
A
= 25
o
C
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
R
R
θ
JA
(t) = r(t) * R
θ
JA
θ
JA
= 111 °C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
t
1
0.01
t
2
0.01
T
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDC699P Rev C2 (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
POP™
SuperFET™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
FACT Quiet Series™
FAST
FASTr™
FPS™
FRFET™
ActiveArray™
Bottomless™
CoolFET™
CROSSVOLT
™
DOME™
EcoSPARK™
E
2
CMOS
TM
EnSigna
TM
FACT™
Power247™
PowerTrench
QFET
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
QS™
QT Optoelectronics™
TinyLogic
GlobalOptoisolator™
GTO™
Quiet Series™
RapidConfigure™
RapidConnect™
TINYOPTO™
TruTranslation™
UHC™
HiSeC™
I
2
C™
SILENT SWITCHER
UltraFET
ImpliedDisconnect™
SMART START™
SPM™
Stealth™
VCX™
OPTOLOGIC
OPTOPLANAR™
PACMAN™
Across the board. Around the world.™
The Power Franchise™
Programmabl
e
A
ctive Droop™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVE
S
T
HE RIGH
T
T
O MAKE CHANGES WITHOU
T
F
URTHER NOTIC
E
T
O
A
NY
PRODUCTS HEREI
N
T
O IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD DOES NO
T
A
SSUM
E
A
N
Y
L
IABILITY
ARISING OU
T
O
F
T
H
E
A
PPLICATION OR USE O
F
A
N
Y
P
RODUC
T
O
R CIRCUI
T
D
ESCRIBED HEREIN; NEITHER DOES IT
CONVE
Y
A
N
Y
L
ICENSE UNDER ITS PATEN
T
R
IGHTS, NO
R
T
HE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I7
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FDC699P
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Contents
•
General description
•
Features
•
Order Samples
•
Models
Product Change Notices
(PCNs)
Datasheet
•
Applications
•
Qualification Support
Download this
datasheet
•
Product status/pricing/packaging
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Sales support
Quality and reliability
Design center
General description
This P-Channel 2.5V specified MOSFET is a rugged gate version of
Fairchild Semiconductor’s advanced PowerTrench process. It has been
optimized for power management applications with a wide range of gate
drive voltage (2.5V – 12V).
e-mail this datasheet
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Print version
Features
This product
Use in FETBench
Analysis
z
-7 A, -20V R
= 22 mOhm @ VGS = -4.5 V
= 30 mOhm @ VGS = -2.5 V
DS(ON)
R
DS(ON)
z
High performance trench technology for extremely low R
Fast switching speed
DS(ON)
z
z
FLMP SuperSOT-6 package: Enhanced thermal performance in
industry-standard package size
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Applications
z
z
z
Battery management
Load Switch
Battery protection
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Product status/pricing/packaging
Pb-free
Status
Package
type
Packing
method
Product
FDC699P
Product status
Pricing*
Leads
Package Marking Convention**
Line 1: &E&
(Binary Calendar Year
Y
Not recommended for new
designs
SSOT-6
FLMP
$0.45
6
TAPE REEL
Coding)
Line 2: .699
Line 1: &E&
(Binary Calendar Year
Y
SSOT-6
FLMP
FDC699P_F077
Full Production
$0.57
6
TAPE REEL
Coding)
Line 2: .699
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild’s on-line samples program. If there is no sample button, please
contact a
Fairchild distributor
to obtain samples
Indicates product with Pb-free second-level interconnect. For more information
click here.
Package marking information for product FDC699P is available.
Click here for more information
.
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Models
Package & leads
SSOT-6 FLMP-6
Condition
Temperature range
PSPICE
Software version
Revision date
Electrical
25°C to 125°C
Orcad 9.1
Jan 6, 2004
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Qualification Support
Click on a product for detailed qualification data
Product
FDC699P
FDC699P_F077
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