onsemi-FDD2572
| Part # | onsemi-FDD2572 |
Download  | onsemi-FDD2572 |
Ju
ly
2014
FDD2572 / FDU2572
N-Channel PowerTrench
®
MOSFET
150V, 29A, 54m
Ω
Features
Applications
•
•
•
•
•
r
DS(ON)
= 45m
Ω
(
T
y
p.), V
GS
= 10
V
,
I
D
= 9A
Q
g
(tot) = 26nC (Typ.), V
GS
= 10V
Low Miller Charge
•
•
•
•
DC/DC converters and Off-Line UPS
Distributed Power Architectures and VRMs
Primary Switch for 24V and 48V Systems
High Voltage Synchronous Rectifier
Low Q
Body Diode
RR
UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82860
DRAIN
(FLANGE)
D
SOURCE
DRAIN
DRAIN
(FLANGE)
GATE
GATE
G
SOURCE
TO-252AA
FDD SERIES
TO-251AA
FDU SERIES
S
MOSFET Maximum Ratings
T
C
= 25°C unless otherwise noted
Symbol
V
DSS
V
GS
Parameter
Ratings
150
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
±
20
Continuous (T
C
= 25
o
C, V
GS
= 10V)
Continuous (T
C
= 100
o
C, V
GS
= 10V)
Continuous (
T
amb
= 25
o
C,
V
GS
= 10V, R
θ
JA
= 52
o
C/W)
Pulsed
29
20
A
A
I
D
4
Figure 4
36
A
mJ
E
AS
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Derate above 25
o
C
135
W
P
D
0.9
W/
o
C
o
C
T
J
, T
STG
Operating and Storage
T
e
mperature
-55 to 175
Thermal Characteristics
R
θ
JC
R
θ
JA
R
θ
JA
Thermal Resistance Junction to Case TO-251, TO-252
1.11
100
52
o
C/W
o
C/W
o
C/W
Thermal Resistance Junction to Ambient TO-251, TO-252
Thermal Resistance Junction to Ambient TO-252, 1in
2
copper pad area
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Package Marking and Ordering Information
Device Marking
FDD2572
Device
FDD2572
FDU2572
Package
TO-252AA
TO-251AA
Reel Size
330mm
T
u
be
Tape Width
16mm
Quantity
2500 units
75 units
FDU2572
N/A
Electrical Characteristics
T
C
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
VDSS
Drain to Source Breakdown Voltage
Zero Gate
V
o
ltage Drain Current
Gate to Source Leakage Current
I
D
= 250
µ
A, V
GS
= 0V
150
–
–
–
–
–
V
V
DS
= 120V
V
GS
= 0V
GS
=
±
20V
–
–
–
1
I
DSS
µ
A
T
C
= 150
o
250
±
100
I
GSS
V
nA
On Characteristics
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
µ
A
2
–
–
4
V
I
D
=9A, V
GS
=10V
0.045 0.054
0.050 0.075
0.126 0.146
r
DS(ON)
Drain to Source On Resistance
I
D
= 4A, V
GS
= 6
V
,
–
Ω
I
D
=9A, V
GS
=10
V
,
T
C
=175
o
C
–
Dynamic Characteristics
C
ISS
Input Capacitance
–
–
–
–
–
–
–
–
1770
183
40
26
3.3
8
–
–
pF
pF
pF
nC
nC
nC
nC
nC
V
DS
= 25V, V
GS
= 0
V
,
C
OSS
C
RSS
Q
g(TOT)
Q
g(TH)
Q
gs
Output Capacitance
f = 1MHz
Reverse
T
r
ansfer Capacitance
Total Gate Charge at 10V
Threshold Gate Charge
–
V
GS
= 0V to 10V
34
4.3
–
V
GS
= 0V to 2V
V
DD
= 75V
D
= 9A
I
g
= 1.0mA
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
I
Q
gs2
5
–
Q
gd
6
–
Resistive Switching Characteristics
(V
GS
= 10V)
t
ON
t
d(ON)
t
r
Turn-On T ime
Turn-On D elay T ime
Rise Time
–
–
–
–
–
–
–
36
–
ns
ns
ns
ns
ns
ns
11
14
31
14
–
–
V
DD
= 75
V
,
I
D
= 9A
GS
= 10V, R
GS
= 11.0
Ω
V
t
d(OFF)
t
f
Turn-Off Delay Time
Fall Time
–
–
t
OFF
Turn-Off Time
66
Drain-Source Diode Characteristics
I
I
I
I
SD
= 9A
–
–
–
–
–
–
–
–
1.25
1.0
74
V
V
V
SD
Source to Drain Diode Voltage
SD
= 4A
t
rr
Reverse Recovery Time
SD
= 9A, dI
SD
/dt =100A/
µ
s
SD
= 9A, dI
SD
/dt =100A/
µ
s
ns
nC
Q
RR
Reverse Recovered Charge
169
Notes:
1:
Starting T
= 25°C, L = 0.2mH, I
= 19A.
J
AS
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Typical Characteristics
T
C
= 25°C unless otherwise noted
1.2
40
V
= 10V
GS
35
1.0
30
0.8
25
20
0.6
15
0.4
10
0.2
5
0
0
150
0
25
50
75
100
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE (
C)
C
T
, CASE TEMPERATURE (
C)
C
Figure 1.
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
Maximum Continuous Drain Current vs
Case Temperature
2.0
DUTY CYCLE – DESCENDING ORDER
1.0
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
SINGLE PULSE
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
x Z
x R
+ T
J
DM
θ
JC
θ
JC C
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
10
10
10
t,
R
ECTANGULAR PULSE DUR
A
T
ION (s)
Figure 3.
Normalized Maximum Transient Thermal Impedance
500
o
T
= 25 C
C
FOR TEMPERATURES
o
TRANSCONDUC
T
ANCE
M
A
Y
L
IMIT CURRENT
IN THIS REGION
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
150
C
I = I
25
100
V
= 10V
GS
20
-5
-4
-3
-2
-1
0
1
10
10
10
10
t,
P
ULSE WIDTH (s)
10
10
10
Figure 4.
Peak Current Capability
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Typical Characteristics
T
C
= 25°C unless otherwise noted
1000
100
10
100
10
1
o
10
µ
s
S
T
ARTING T
= 25
C
J
100
µ
s
1ms
10ms
DC
OPERATION IN THIS
AREA M
A
Y
B
E
o
S
T
ARTING T
= 150 C
J
LIMITED BY r
DS(ON)
1
If R = 0
= (L)(I
)/(1.3*R
A
T
ED BV
t
– V
DD
)
SINGLE PULSE
AV
AS
DSS
T
= MAX RATED
If R
≠
0
J
o
t
= (L/R)ln[(I
*R)/(1.3*RATED BV
– V
) +1]
DSS DD
T
= 25
C
AV
AS
C
0.1
0.1
0.001
0.01
0.1
1
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
V
t ,
TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6.
Unclamped Inductive Switching
Capability
Figure 5.
Forward Bias Safe Operating Area
60
60
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
V
= 10V
T
= 25
C
GS
C
50
40
30
20
10
0
50
40
30
20
10
0
V
= 15V
DD
V
= 7V
GS
o
T
= 175
C
J
V
= 6V
GS
o
T
= 25
C
V
= 5V
J
GS
o
T
= -55
C
J
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
Figure 7.
Transfer Characteristics
Figure 8.
Saturation Characteristics
60
3.0
2.5
2.0
1.5
1.0
0.5
0
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= 6V
GS
55
50
V
= 10V
GS
45
40
V
= 10
V
, I
=
9A
D
GS
0
10
20
30
-80
-40
0
40
80
120
160
200
o
I ,
DRAIN CURRENT (A)
T ,
JUNCTION TEMPERATURE (
C)
D
J
Figure 9.
Drain to Source On Resistance vs Drain
Current
Figure 10.
Normalized Drain to Source On
Resistance vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Typical Characteristics
T
C
= 25°C unless otherwise noted
1.4
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
V
= V
, I
= 250
µ
A
DS D
I
= 250
µ
A
GS
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T ,
JUNCTION TEMPERATURE ( C)
J
J
Figure 11.
Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12.
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
1000
10
V
= 75V
DD
C
=
C +
C
GS GD
ISS
1000
100
10
8
6
4
2
0
C
C
+ C
OSS
DS GD
C
=
C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
I
I
= 9A
= 4A
D
D
V
= 0V, f = 1MHz
1
GS
0.1
10
150
0
5
10
15
20
25
30
V
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
G
A
TE CHARGE (nC)
DS
g
Figure 13.
Capacitance vs Drain to Source
Voltage
Figure 14.
Gate Charge Waveforms for Constant
Gate Currents
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t
TO OBTAIN
P
+
–
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
0
AS
0.01
Ω
t
AV
Figure 15.
Unclamped Energy Test Circuit
Figure 16.
Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
V
DD
V
GS
–
V
= 2V
DUT
GS
Q
gs2
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17.
Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
0
DS
90%
90%
+
V
GS
V
DD
10%
10%
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19.
Switching Time Test Circuit
Figure 20.
Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
Thermal Resistance vs. Mounting Pad Area
The max imum r ated j unction t emperature, T
JM
, an d t he
125
thermal resistance of the heat dissipating path determines
the m
a
x
imum a
l
l
owable d
e
v
ice
p
o
wer d
i
s
sipation,
P
DM
, in an
R
= 33.32+ 23.84/(0.268+Area) EQ.2
= 33.32+ 154/(1.73+Area) EQ.3
θ
JA
R
application. T
herefore t
he a
pplication’s amb
ient
θ
JA
100
75
temperature, T
A
(
o
C), a
n
d t
h
ermal resistance
R
θ
JA
(
o
C/W)
must be
reviewed to e
n
s
ure
t
h
at
T
JM
is n
e
v
er e
x
c
eeded.
Equation 1 m
a
t
hematically represents the relationship and
serves as the basis for establishing the rating of the part.
(
T
–
T
)
JM
A
(EQ. 1)
P
=
–
—————————-
50
DM
R
θ
JA
In us ing su rface
mount de vices suc h as t
he TO-252
package, the environment in which it is applied will have a
significant in fluence o n t he p art’s cur rent
and max imum
power
d
i
ssipation ratings. Precise
d
e
termination of
P
DM
is
complex and influenced by many factors:
25
0.01
(0.0645)
0.1
(0.645)
1
10
(6.45)
(64.5)
2
2
AREA, TOP COPPER AREA in
(cm )
Figure 21.
Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2.
T
h
e number
o
f
c
o
p
per l
a
y
ers and
t
h
e
t
h
ickness of
t
h
e
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6.
F
o
r no n s teady st ate ap plications,
t
h
e pu lse w idth, t he
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild p
rovides t
hermal information to
as sist
t he
designer’s preliminary
ap plication ev aluation. F igure 21
defines t he R
θ
JA
f or t he de vice
as a
f unction
of t he t op
copper ( component si de) ar ea. T his is
f or a h
orizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of s
t
e
ady s
t
a
te
p
o
wer with no air flow. This graph provides
the necessary information for calculation of the steady state
junction t
emperature o
r p
ower di
ssipation. P
ulse
applications ca n be ev aluated us ing t he F airchild
device
Spice t hermal
model or
m anually u tilizing t he no rmalized
maximum transient thermal impedance curve.
Thermal resistances co rresponding to ot her co pper areas
can be
obtained f rom F igure
21 or
by calculation
using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches
s
q
uare a
n
d e
q
uation 3 i s for a
r
e
a
i
n
c
e
n
timeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
(
0.268 +
Area
)
R
=
33.32 +
–
———————————–
(EQ. 2)
θ
JA
θ
JA
Area in Inches Squared
154
R
=
33.32 +
–
——————————–
(EQ. 3)
(
1.73 +
Area
)
Area in Centimeters Squared
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
PSPICE Electrical Model
.SUBCKT FDD2572 2 1 3 ;
CA 12 8
5
.
5
e-10
Cb 15 14 7.4e-10
Cin 6 8 1.7e-9
rev April 2002
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 D
b
o
dyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
11
Ebreak 11 7 17 18 160
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
–
+
50
–
17
DBODY
RDRAIN
6
8
EBREAK 18
–
ESG
EVTHRES
+
16
21
+
–
19
8
MWEAK
LGATE
EVTEMP
RG
A
TE
GATE
1
6
+
–
18
22
It 8 17 1
MMED
9
20
MSTRO
8
RLGATE
Lgate 1 9 1
.
21e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 4.45e-9
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
RLgate 1 9 12.1
RLdrain 2 5 10
RLsource 3 7 44.5
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RVTEMP
19
–
S1B
S2B
Mmed 16 6 8 8
M
m
edMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 35e-3
Rgate 9 20 1.6
–
–
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 3.0e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50
VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*52),3))}
.MODEL DbodyMOD D (IS=6.0E-11 N=1.14 RS=3.9e-3 TRS1=3.5e-3 TRS2=3.0e-6
+ CJO=1.1e-9 M=0.63 TT=6.2e-8 XTI=4.5)
.MODEL DbreakMOD D (RS=10 TRS1=5.0e-3 TRS2=-5.0e-6)
.MODEL DplcapMOD D (CJO=3.5e-10 IS=1.0e-30 N=10 M=0.65)
.MODEL MmedMOD NMOS (VTO=3.55 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.6)
.MODEL MstroMOD NMOS (VTO=4.0 KP=25 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.95 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.15e-3 TC2=-9.5e-7)
.MODEL RdrainMOD RES (TC1=9.0e-3 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.5e-6)
.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)
.MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (TC1=-4.0e-3 TC2=1.0e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
SABER Electrical Model
REV April 2002
ttemplate FDD2572 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod =
(isl=6.0e-11,nl=1.14,rs=3.9e-3,trs1=3.5e-3,trs2=3.0e-6,cjo=1.1e-9,m=0.63,tt=6.2e-8,xti=4.5)
dp..model dbreakmod = (rs=10,trs1=5.0e-3,trs2=-5.0e-6)
dp..model dplcapmod =
(cjo=3.5e-10,isl=10.0e-30,nl=10,m=0.65)
m..model mmedmod = (type=_n,vto=3.55,kp=3,is=1e-40, tox=1)
m..model mstrongmod = (type=_n,vto=4.0,kp=25,is=1e-30, tox=1)
LDRAIN
m..model mweakmod = (type=_n,vto=2.95,kp=0.05,is=1e-30, tox=1,rs=0.1)
DPLCAP
5
DRAIN
2
sw_vcsp..model s1amod =
(ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)
sw_vcsp..model s1bmod =
(ron=1e-5,roff=0.1,von=-3.5,voff=-5.0)
sw_vcsp..model s2amod =
(ron=1e-5,roff=0.1,von=-0.5,voff=0.3)
sw_vcsp..model s2bmod =
(ron=1e-5,roff=0.1,von=0.3,voff=-0.5)
c.ca n12 n8 = 5
.
5
e-10
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
c.cb n15 n14 = 7.4e-10
c.cin n6 n8 = 1.7e-9
DBREAK
11
50
–
RDRAIN
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
6
8
ESG
DBODY
EVTHRES
+
16
21
+
–
19
8
MWEAK
LGATE
EVTEMP
RG
A
T
E
G
A
TE
1
+
6
spe.ebreak n11 n7 n17 n18 = 160
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
–
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
–
RLGATE
LSOURCE
CIN
SOURCE
3
7
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RSOURCE
RLSOURCE
S1A
S2A
i.it n8 n17 = 1
RBREAK
12
15
13
8
14
13
17
18
l.lgate n1 n9 = 1
.
2
1e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.45e-9
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
–
+
+
VBAT
res.rlgate n1 n9 = 12.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 44.5
6
8
5
8
EGS
EDS
+
–
–
8
22
RVTHRES
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18
= 1, tc1=1.15e-3,tc2=-9.5e-7
res.rdrain n50 n16
= 35e-3, tc1=9.0e-3,tc2=2.5e-5
res.rgate n9 n20 = 1.6
res.rslc1 n5 n51
= 1.0e-6, tc1=3.0e-3,tc2=2.5e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7
= 3.0e-3, tc1=4.0e-3,tc2=1.0e-6
res.rvthres n22 n8
= 1, tc1=-4.1e-3,tc2=-1.0e-5
res.rvtemp n18 n19
= 1, tc1=-4.0e-3,tc2=1.0e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/52))** 3))}
}
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
SPICE Thermal Model
JUNCTION
th
REV 26 April 2002
FDD2572
CTHERM1 TH 6 3.8e-3
CTHERM2 6 5 4.0e-3
CTHERM3 5 4 4.2e-3
CTHERM4 4 3 4.3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 TL 3.0e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.7e-1
RTHERM6 2 TL 3.8e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDD2572
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.8e-3
ctherm.ctherm2 6 5 =4.0e-3
ctherm.ctherm3 5 4 =4.2e-3
ctherm.ctherm4 4 3 =4.3e-3
ctherm.ctherm5 3 2 =8.5e-3
ctherm.ctherm6 2 tl =3.0e-2
4
3
2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =
5
.
0e-3
rtherm.rtherm3 5 4 =
4
.
5e-2
rtherm.rtherm4 4 3 =
1
0
.5e-2
rtherm.rtherm5 3 2 =
3
.
7e-1
rtherm.rtherm6 2 tl =3.8e-1
}
tl
CASE
©2002 Fairchild Semiconductor Corporation
FDD2572 / FDU2572 Rev. 2.3
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