onsemi-FDD8870
| Part # | onsemi-FDD8870 |
Download  | onsemi-FDD8870 |
September 2004
FDD8870 / FDU8870
N-Channel PowerTrench
®
MOSFET
30V, 160A, 3.9
m
Ω
General Description
Features
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It
has been optimized for low gate charge, low
•
•
•
r
= 3.9m
Ω
, V
= 1
0
V, I
= 35A
DS(ON)
GS
GS
D
r
= 4.4m
Ω
, V
= 4
.
5V, I
= 35A
DS(ON)
D
High performance trench technology for extremely low
r
and fast switching speed.
DS(ON)
r
DS(ON)
•
•
Low gate charge
Applications
High power and current handling capability
•
DC/DC converters
D
D
G
S
I-PAK
(TO-251AA)
G
D-PAK
(TO-252)
S
G D S
MOSFET Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
Parameter
Ratings
30
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
Drain Current
V
V
DSS
GS
±
20
o
160
150
A
A
Continuous (T
= 25
C, V
= 10V) (Note 1)
= 4.5V) (Note 1)
= 1
0
V, with R
= 52
C/W)
θ
JA
C
GS
GS
o
I
Continuous (T
= 25
C, V
D
C
o
o
Continuous (T
Pulsed
= 25
C, V
21
A
amb
GS
Figure 4
690
A
E
P
Single Pulse Avalanche Energy (Note 2)
Power dissipation
mJ
W
AS
D
160
o
o
Derate above 25
C
1.07
W/ C
o
T , T
Operating and Storage Temperature
-55 to 175
C
J
STG
Thermal Characteristics
o
R
θ
JC
R
θ
JA
R
θ
JA
Thermal Resistance Junction to Case TO-252, TO-251
0.94
100
52
C/W
o
Thermal Resistance Junction to Ambient TO-252, TO-251
C/W
2
o
Thermal Resistance Junction to Ambient TO-252, 1in
copper pad area
C/W
Package Marking and Ordering Information
Device Marking
FDD8870
Device
FDD8870
FDU8870
Package
TO-252AA
TO-251AA
Reel Size
13”
Tape Width
Quantity
12mm
N/A
2500 units
75 units
FDU8870
Tube
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Electrical Characteristics
T =
25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250
µ
A, V
= 0V
GS
30
–
–
–
–
–
V
V
D
SS
D
V
V
V
= 24V
= 0V
–
–
–
1
DS
GS
GS
I
µ
A
nA
DSS
GSS
o
T
= 150
C
250
±
100
C
I
=
±
20V
On Characteristics
V
Gate to Source Threshold Voltage
V
I
= V
, I
= 250
µ
A
1.2
–
2.5
V
GS(TH)
GS
DS
D
GS
GS
GS
= 35A, V
= 35A, V
= 35A, V
= 10V
= 4.5V
= 10V,
–
–
0.0032 0.0039
0.0036 0.0044
D
I
I
D
r
Drain to Source On Resistance
Ω
DS(ON)
D
–
0.0051 0.0063
o
T
= 175
C
J
Dynamic Characteristics
C
C
C
R
Input Capacitance
–
–
–
–
–
–
–
–
–
–
5160
990
590
2.1
91
–
pF
pF
pF
Ω
ISS
OSS
RSS
G
V
= 15V, V
= 0V,
GS
DS
Output Capacitance
–
f = 1MHz
Reverse Transfer Capacitance
Gate Resistance
–
–
V
V
V
V
= 0.5V, f = 1MHz
= 0V to 10V
GS
GS
GS
GS
Q
Q
Q
Q
Q
Q
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
118
62
6.5
–
nC
nC
nC
nC
nC
nC
g(TOT)
g(5)
g(TH)
gs
= 0V to 5V
48
V
DD
= 15V
= 0V to 1V
5
I
I
= 35A
= 1.0mA
D
g
14
9
–
gs2
18
–
gd
Switching Characteristics
(V =
10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
–
–
–
–
–
–
–
139
ns
ns
ns
ns
ns
ns
ON
9
–
d(ON)
83
83
42
–
–
V
V
= 15V, I
= 35A
D
r
DD
GS
= 1
0
V,
R
= 3.3
Ω
Turn-Off Delay Time
Fall Time
–
–
GS
d(OFF)
f
Turn-Off Time
189
OFF
Drain-Source Diode Characteristics
I
= 35A
= 15A
–
–
–
–
–
–
–
–
1.25
1.0
37
V
V
SD
V
t
Source to Drain Diode Voltage
SD
I
I
I
SD
SD
SD
Reverse Recovery Time
= 35A, dI
/dt = 100A
/
µ
s
ns
nC
rr
SD
Q
Reverse Recovered Charge
= 35A, dI
/dt = 100A
/
µ
s
21
RR
SD
Notes:
1:
Package current limitation is 35A.
2:
Starting T
= 25°C, L = 1.77mH,
I
A
S
= 28A, V
D
D
= 27V, V
GS
= 10V.
J
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Typical Characteristics
T =
25°C unless otherwise noted
C
1.2
175
1.0
0.8
0.6
0.4
0.2
0
150
125
100
75
CURRENT LIMITED
BY PACKAGE
50
25
0
150
0
25
50
75
100
125
175
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
T
C
, CASE TEMPERATURE
(
o
C)
Figure 1.
Normalized Power Dissipation vs Case
Temperature
Figure 2.
Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE – DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/
t
2
SINGLE PULSE
0.01
PEAK
T
J
=
P
DM
x
Z
θ
JC
x R
θ
JC
+ T
C
1
1
0
-5
1
0
-4
1
0
-3
1
0
-2
1
0
-1
1
0
0
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3.
Normalized Maximum Transient Thermal Impedance
2000
T
C
= 2
5
o
C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
1000
CURRENT AS FOLLOWS:
V
GS
= 4.5V
175 – T
C
I = I
25
150
100
30
-1
1
0
-5
1
0
-4
1
0
-3
1
0
-2
10
1
0
0
1
0
1
t, PULSE WIDTH (s)
Figure 4.
Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Typical Characteristics
T =
25°C unless otherwise noted
C
1000
100
10
100
10
1
1
0
µ
s
STARTING T
J
= 25
o
C
10
0
µ
s
STARTING T
J
= 15
0
o
C
OPERATION IN THIS
AREA MAY BE
1ms
LIMITED BY
r
DS(ON)
10ms
DC
1
If R = 0
t
A
V
= (L)(I
A
S
)/(1.3*RATED B
V
D
SS
–
V
D
D
SINGLE PULSE
)
T
J
= MAX RATED
If
R
≠
0
T
C
= 2
5
o
C
t
A
V
= (L/R)ln[(
I
A
S
*R)/(1.3*RATED BV
DSS
– V
D
D
) +1]
0.1
1
10
V
D
S
, DRAIN TO SOURCE VOLTAGE (V)
60
0.1
1
10
100
t
A
V
, TIME IN AVALANCHE (ms)
NOTE:
Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5.
Forward Bias Safe Operating Area
Figure 6.
Unclamped Inductive Switching
Capability
100
100
PULSE DURATION = 8
0
µ
s
V
GS
= 5V
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
80
80
V
GS
= 4V
T
J
= 17
5
o
C
V
GS
= 10V
60
60
40
20
0
V
GS
= 3V
T
J
= 25
o
C
40
V
GS
= 2.5V
T
C
= 2
5
o
C
20
PULSE DURATION = 8
0
µ
s
DUTY CYCLE = 0.5% MAX
o
T
J
= -55 C
0
0
0.2
0.4
0.6
1.5
2.0
2.5
3.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
D
S
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7.
Transfer Characteristics
Figure 8.
Saturation Characteristics
8
8
6
4
2
1.6
1.4
1.2
1.0
0.8
0.6
PULSE DURATION = 8
0
µ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
I
D
= 35A
I
D
= 1A
V
GS
= 10V, I
D
= 35A
2
4
6
8
10
-80
-40
0
40
80
120
160
200
V
G
S
, GATE TO SOURCE VOLTAGE (V)
T
J
, JUNCTION TEMPERATURE (
o
C)
Figure 9.
Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 10.
Normalized Drain to Source On
Resistance vs Junction Temperature
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Typical Characteristics
T =
25°C unless otherwise noted
C
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
I
D
= 250
µ
A
V
GS
=
V
D
S
, I
D
= 25
0
µ
A
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE
(
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
Figure 11.
Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12.
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
10
V
D
D
= 15V
C
ISS
=
C
GS
+ C
GD
8
6
C
OSS
≅
C
DS
+ C
GD
C
RSS
=
C
GD
4
1000
WAVEFORMS IN
2
0
DESCENDING ORDER:
I
D
= 35A
I
D
= 5A
V
GS
= 0V, f = 1MHz
400
0.1
1
10
30
0
20
40
60
80
100
V
D
S
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 13.
Capacitance vs Drain to Source
Voltage
Figure 14.
Gate Charge Waveforms for Constant
Gate Current
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Test Circuits and Waveforms
V
DS
B
V
DSS
t
P
L
V
D
S
I
AS
VARY
t
P
TO OBTAIN
+
V
D
D
R
G
REQUIRED PEAK
I
AS
V
GS
V
DD
–
DUT
t
P
I
A
S
0V
0
0.0
1
Ω
t
A
V
Figure 15.
Unclamped Energy Test Circuit
Figure 16.
Unclamped Energy Waveforms
V
D
S
V
DD
Q
g(TOT)
V
GS
V
DS
L
V
GS
= 10V
Q
g(5)
V
GS
+
Q
g
s2
V
D
D
V
GS
= 5V
–
DUT
V
GS
= 1V
I
g(REF)
0
Q
g(TH)
Q
gs
Q
gd
I
g(REF)
0
Figure 17.
Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
V
D
S
t
ON
t
d(ON)
t
OFF
t
d(OFF)
R
L
t
r
t
f
V
D
S
90%
90%
+
V
GS
V
DD
10%
10%
–
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
V
GS
10%
0
Figure 19.
Switching Time Test Circuit
Figure 20.
Switching Time Waveforms
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
, and the
thermal resistance of the heat dissipating path determines
JM
125
100
75
R
θ
JA
= 33.32+ 23.84/(0.268+Area) EQ.2
R
θ
JA
= 33.32+ 154/(1.73+Area) EQ.3
the maximum allowable device power dissipation, P
, in an
DM
application.
Therefore the application’s ambient
o
o
temperature, T
( C), and thermal resistance R
( C/W)
A
θ
JA
must be reviewed to ensure that T
is never exceeded.
JM
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(
T
–
T
)
A
JM
(EQ. 1)
P
=
–
—————————-
50
D M
R
θ
JA
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
25
0.01
(0.0645)
0.1
(0.645)
1
10
(6.45)
(64.5)
power dissipation ratings. Precise determination of P
complex and influenced by many factors:
is
DM
AREA, TOP COPPER AREA i
n
2
(c
m
2
)
Figure 21.
Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
for the device as a function of the top
θ
JA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
23.84
(
0.268 +
Area
)
R
=
33.32 +
–
————————————
(EQ. 2)
θ
JA
θ
JA
Area in Inches Squared
154
R
=
33.32 +
–
———————————
(EQ. 3)
(
1.73 +
A
re
a
)
Area in Centimeters Squared
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
PSPICE Electrical Model
.SUBCKT FDD8870
2 1 3 ; rev July 2003
Ca 12 8 4.2e-9
Cb 15 14 4.2e-9
Cin 6 8 4.7e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
11
51
Ebreak 11 7 17 18 32.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
–
50
+
–
17
18
–
DBODY
RDRAIN
6
8
ESG
EBREAK
MWEAK
Esg 6 10 6 8 1
EVTHRES
+
16
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
GATE
21
+
–
19
8
LGATE
EVTEMP
RGATE
+
6
–
18
22
1
MMED
It 8 17 1
9
20
MSTRO
8
RLGATE
Lgate 1 9 5e-9
Ldrain 2 5 1.0e-9
LSOURCE
CIN
SOURCE
3
7
Lsource 3 7 2e-9
RSOURCE
RLSOURCE
RLgate 1 9 50
RLdrain 2 5 10
RLsource 3 7 20
S1A
S1B
S2A
RBREAK
12
15
13
14
13
17
18
8
S2B
RVTEMP
19
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.57e-3
Rgate 9 20 2.1
–
–
8
22
RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50
VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=1.3E-11 IKF=10 N=1.01 RS=1.8e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=2e-9 M=0.57 TT=1e-10 XTI=0.9)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.6e-9 IS=1e-30 N=10 M=0.38)
.MODEL MmedMOD NMOS (VTO=1.76 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.2 KP=650 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.47 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7)
.MODEL RdrainMOD RES (TC1=2e-4 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=8e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2e-3 TC2=-9.5e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
SABER Electrical Model
rev July 2003
template FDD8870 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod =
(isl=1.3e-11,ikf=10,nl=1.01,rs=1.8e-3,trs1=8e-4,trs2=2e-7,cjo=2e-9,m=0.57,tt=1e-10,xti=0.9)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod =
(cjo=1.6e-9,isl=10e-30,nl=10,m=0.38)
m..model mmedmod = (type=_n,vto=1.76,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=650,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.47,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod =
(ron=1e-5,roff=0.1,von=-4,voff=-3)
sw_vcsp..model s1bmod =
(ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod =
(ron=1e-5,roff=0.1,von=-2,voff=-0.5)
sw_vcsp..model s2bmod =
(ron=1e-5,roff=0.1,von=-0.5,voff=-2)
c.ca n12 n8 = 4.2e-9
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
RSLC2
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 4.7e-9
ISCL
DBREAK
11
50
–
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
DBODY
EVTHRES
+
16
21
+
–
19
8
MWEAK
LGATE
EVTEMP
spe.ebreak n11 n7 n17 n18 = 32.7
GATE
1
RGATE
+
6
18
22
–
EBREAK
+
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
MMED
9
20
MSTRO
8
17
18
–
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
l.lgate n1 n9 = 5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2e-9
S1B
S2B
RVTEMP
19
13
CB
CA
IT
14
–
+
+
res.rlgate n1 n9 = 50
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 20
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
RVTHRES
res.rbreak n17 n18
= 1, tc1=8.3e-4,tc2=-4e-7
res.rdrain n50 n16
= 1.57e-3, tc1=2e-4,tc2=8e-6
res.rgate n9 n20 = 2.1
res.rslc1 n5 n51
= 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 1.2e-3, tc1=8e-3,tc2=1e-6
res.rvthres n22 n8
= 1, tc1=-2e-3,tc2=-9.5e-6
res.rvtemp n18 n19
= 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
PSPICE Thermal Model
JUNCTION
th
REV 23 July 2003
FDD8870T
CTHERM1 TH 6 1e-3
CTHERM2 6 5 2e-3
CTHERM3 5 4 3e-3
CTHERM4 4 3 9e-3
CTHERM5 3 2 1e-2
CTHERM6 2 TL 2e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 TH 6 3e-2
RTHERM2 6 5 8e-2
RTHERM3 5 4 1.1e-1
RTHERM4 4 3 1.6e-1
RTHERM5 3 2 1.72e-1
RTHERM6 2 TL 2e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model FDD8870T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1e-3
ctherm.ctherm2 6 5 =2e-3
ctherm.ctherm3 5 4 =3e-3
ctherm.ctherm4 4 3 =9e-3
ctherm.ctherm5 3 2 =1e-2
ctherm.ctherm6 2 tl =2e-2
4
3
2
rtherm.rtherm1 th 6 =3e-2
rtherm.rtherm2 6 5 =8e-2
rtherm.rtherm3 5 4 =1.1e-1
rtherm.rtherm4 4 3 =1.6e-1
rtherm.rtherm5 3 2 =1.72e-1
rtherm.rtherm6 2 tl =2e-1
}
tl
CASE
©2004 Fairchild Semiconductor Corporation
FDD8870 / FDU8870 Rev. C
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Rev. I12
