onsemi-FDG6317NZ
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FDG6317NZ
MOSFET
– Dual, N-Channel,
POWERTRENCH
)
20
V
,
2
.1 A, 550 m
W
General Description
This dual N
−
Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using either
synchronous or conventional switching PWM controllers. It has been
optimized use in small switching regulators, providing an extremely
V
R
MAX
I MAX
D
DSS
DS(ON)
20 V
550 m
W
2.1 A
Iow R
and gate charge (QG) in a small package.
DS(ON)
Features
•
0.7 A, 20 V
♦
R
♦
R
= 400 m
W
@ V
= 4.5 V
GS
DS(ON)
= 550 m
W
@ V
= 2.5 V
DS(ON)
GS
•
Gate
−
Source Zener for ESD ruggedness
•
Low Gate Charge
•
High Performance Trench Technology for Extremely Low R
•
Compact Industry Standard SC70
−
6 Surface Mount Package
•
These Devices are Pb
−
Free and are RoHS Compliant
DS(ON)
D
G
Applications
D
•
DC/DC Converter
•
Power Management
•
Load Switch
D
G
S
Pin 1
SC70
−
6
CASE 419B
MAXIMUM RATINGS
(T =
25
°
C unless otherwise noted)
A
Symbol
Parameter
Drain
−
Source Voltage
Gate
−
Source Voltage
Ratings
20
Units
MARKING DIAGRAM
V
DSS
V
GSS
V
V
A
12
&E&E&E&
&Y
&.67&G
I
D
Drain Current:
Continuous (Note1)
Pulsed
0.7
2.1
P
D
Power Dissipation for Single
Operation
0.3
W
&Y
&.67&G
= Data Code
= Specific Device Code
T , T
Operating and Storage Junction
T
e
mperature Range
−
55 to +150
°
C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
THERMAL CHARACTERISTICS
Symbol
Parameter
FDG6317NZ
Unit
R
Thermal Resistance, Junction to Ambient, (Note 1)
415
_
C/W
q
JA
1. R
is the sum of the junction
−
to
−
case and case
−
to
−
ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design. R
q
JA
= 415
_
C/W when
q
q
JC
JA
mounted on a minimum pad.
©
Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
July, 2019
−
Rev.2
FDG6317NZ/D
FDG6317NZ
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Reel Size
Tape Width
Quantity
.67
FDG6317NZ
7”
8 mm
3000 units
ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise noted)
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
V
I
= 0
V
, I
= 250
m
A
20
−
−
−
V
DSS
GS
D
D
BV
/
D
T
Breakdown Voltage
T
e
mperature
Coefficient
= 250
m
A, Referenced to 25
_
C
−
13
mV/
_
C
DSS
J
D
I
Zero Gate Voltage Drain Current
Gate
−
Body Leakage
V
DS
V
GS
V
GS
= 16
V
, V
= 0 V
−
−
−
−
1
m
A
m
A
m
A
DSS
GS
I
=
=
12
V
, V
= 0 V
10
1
GSS
GSS
DS
I
Gate
−
Body Leakage
4.5
V
, V
= 0 V
DS
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
I
= V
, I
= 250
m
A
0.6
1.2
1.5
V
GS(th)
DS
GS
D
D
V
/
D
T
Gate Threshold Voltage
T
e
mperature Coefficient
=
−
250
m
A, Referenced to 25
_
C
−
−
2
mV/
_
C
GS(th)
J
D
R
Static Drain
−
Source
On
−
Resistance
V
V
V
= 4.5
V
, I
= 0.7 A
300
450
390
400
550
560
m
W
DS(on)
GS
GS
GS
D
= 2.5
V
, I
= 0.6 A
D
= 4.5
V
, I
= 0.7 A, T
= 125
_
C
D
J
I
On
−
State Drain Current
V
GS
V
DS
= 10
V
, V
= 0 V
1
A
S
D(on)
DS
g
FS
Forward Transconductance
= 20
V
, I
= 5 A
−
1.8
−
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 10
V
, V
= 0 V, f =
1
.0 MHz
−
−
−
−
66.5
19
−
−
−
−
pF
pF
pF
W
iss
DS
GS
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
10
rss(eff.)
R
V
= 15 m
V
, f =
1
.0 MHz
5.8
G
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
T
o
tal Gate Charge
Gate
−
Source Charge
Gate
−
Drain Charge
V
V
= 10
V
, I
= 1
A
,
−
−
−
−
5.5
7
11
15
15
5
ns
ns
d(on)
DD
GS
D
= 4.5
V
, R
= 6
W
GEN
t
r
t
7.5
ns
d(off)
t
f
2.5
ns
Q
V
DS
V
GS
= 10
V
, I
=
0
.7 A,
0.76
0.18
0.20
1.1
nC
nC
nC
g
D
= 4.5
V
,
Q
gs
gd
Q
DRAIN
−
SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Source to Drain Diode Forward Current
I
S
−
−
−
0.25
1.2
A
V
V
SD
Source to Drain Diode Forward
Voltage
V
GS
= 0
V
, I
=
0
.25 A (Note 2)
0.8
S
t
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
I =
0.7 A, dI
/dt = 100 A/
m
s
−
−
8.3
1.2
−
−
nS
nC
rr
F
F
Q
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse
T
e
st: Pulse Width < 300
m
s, Duty Cycle < 2.0%
3. The
diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
2
FDG6317NZ
TYPICAL PERFORMANCE CHARACTERISTICS
1.7
2
1.5
1
3.0V
V
GS
= 10V
4.5V
V
GS
= 2.5V
2.5V
2.0V
1.5
1.3
1.1
0.9
3.0V
3.5V
4.0V
2.0V
4.5V
0.5
0
6.0V
1.5
10V
0
0.5
1
2
0
0.5
1
1.5
2
2.5
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN
−
SOURCE VOLTAGE (V)
Figure 1. On
−
Region Characteristics
Figure 2. On
−
Resistance Variation with
Drain Current and Gate Voltage
1
1.5
1.4
1.3
1.2
1.1
1
I
D
= 0.7A
I
D
= 0.35A
V
GS
=10V
0.8
0.6
0.4
0.2
T
A
= 12
5
o
C
0.9
0.8
0.7
T
A
= 25
o
C
−
50
−
25
0
25
50
75
100
125
150
0
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On
−
Resistance Variation with
Figure 4. On
−
Resistance Variation with
Gate
−
to
−
Source Voltage
Temperature
10
1
2
T
A
= 125
o
C
V
GS
= 0V
o
−
5
5
C
V
DS
= 5V
1.5
1
T
A
= 125
o
C
25
o
C
0.1
25
o
C
0.01
o
−
5
5
C
0.5
0
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0
1
2
3
4
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
3
FDG6317NZ
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
5
4
3
2
1
0
100
15V
I
D
= 0.7A
f = 1MHz
GS
= 0 V
V
DS
= 5V
V
75
10V
C
iss
50
C
oss
25
C
rss
0
0
0.2
0.4
0.6
0.8
1
0
5
10
15
20
Q
g
, GATE CHARGE (nC)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
10
10
8
SINGLE PULSE
R
DS(ON)
LIMIT
R
q
JA
= 415
°
C/W
100
m
s
T
A
= 25
°
C
1ms
10ms
1
0.1
100m
6
1s
DC
4
V
GS
= 10V
SINGLE PULSE
R
q
JA
= 41
5
C
/W
T
A
= 25
o
C
0.01
0.001
o
2
0
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
V
DS
, DRAIN
−
SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 10. Single Pulse Maximum Power
Dissipation
Figure 9. Maximum Safe Operating Area
1
D = 0.5
R
q
JA
(t) = r(t)*R
q
JA
R
θ
JA
= 415
°
C/W
0.2
0.1
P(pk
)
0.1
0.05
0.02
0.01
t
1
t
2
T
J
−
T =
P * R
θ
JA
(t)
A
SINGLE PULSE
Duty Cycle, D =
t
1
/ t
2
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 11. Transient Thermal Response Curve
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United
States and/or other countries.
4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING
AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING
DIMENSION: MILLIMETERS.
A
3. DIMENSIONS
D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS
D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS
A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS
b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TI
P
.
7. DIMENSION
b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM
MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOO
T
.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN
NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−−
0.043
−−−
0.004
6X
b
B
TOP VIEW
A
−−−
−−−
1.10
A1
0.00
A2
0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1
1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXM
G
6X
0.66
G
1
2.50
XXX =
Specific Device Code
M
= Date Code*
G
= Pb
−
Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb
−
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting
T
e
chniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb
−
Free indicator, “G” or microdot “
G
”,
may or may not be present.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
SC
−
88/SC70
−
6/SOT
−
363
CASE 419B
−
02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1.
EMITTER 2
2. BASE
2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1.
ANODE 2
2. N/C
PIN 1.
CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1.
ANODE
2. ANODE
3. COLLECTOR
1
4. EMITTER
1
5. BASE
1
3. COLLECTOR
3. CATHODE
1
4. ANODE
1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR
2
6. ANODE
6. CATHODE
6. CATHODE
2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1.
SOURCE 2
2. DRAIN
2
3. GATE
1
PIN 1.
EMITTER 2
2. EMITTER
1
3. COLLECTOR
1
4. BASE
1
PIN 1.
SOURCE 2
2. SOURCE
1
3. GATE
1
PIN 1.
CATHODE 2
2. CATHODE
2
3. ANODE
1
PIN 1.
ANODE 2
2. ANODE
2
3. CATHODE
1
4. ANODE
1
5. ANODE
1
6. CATHODE
2
4. SOURCE
1
5. DRAIN
1
6. GATE
2
4. DRAIN
1
5. DRAIN
2
6. GATE
2
4. CATHODE
1
5. CATHODE
1
6. ANODE
2
5. BASE
2
6. COLLECTOR
2
STYLE 13:
PIN 1.
ANODE
2. N/C
STYLE 14:
PIN 1.
VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1.
VIN1
2. VCC
PIN 1.
ANODE 1
2. ANODE
2
PIN 1.
BASE 1
2. EMITTER
2
3. COLLECTOR
2
4. BASE
2
PIN 1.
BASE 1
2. EMITTER
1
3. COLLECTOR
2
4. BASE
2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE
3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE
3
5. CATHODE
2
6. CATHODE
1
5. EMITTER
1
6. COLLECTOR
1
5. EMITTER
2
6. COLLECTOR
1
6. CATHODE
STYLE 19:
PIN 1.
I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1.
ANODE 1
2. N/C
STYLE 22:
PIN 1.
D1 (i)
2. GND
STYLE 23:
PIN 1.
Vn
2. CH1
3. Vp
STYLE 24:
PIN 1.
CATHODE
2. ANODE
PIN 1.
COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE
2
4. CATHODE
2
5. N/C
3. D2
(i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V
CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2
(c)
5. VBUS
6. D1
(c)
4. N/C
5. V
EN
5. CH2
6. N/C
6. V
REF
6. CATHODE
1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1.
SOURCE 1
2. GATE
1
STYLE 27:
PIN 1.
BASE 2
2. BASE
1
STYLE 28:
PIN 1.
DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1.
ANODE
2. ANODE
PIN 1.
SOURCE 1
2. DRAIN
2
3. DRAIN
2
4. SOURCE
2
5. GATE
1
PIN 1.
BASE 1
2. CATHODE
3. COLLECTOR
2
4. BASE
2
3. DRAIN
2
4. SOURCE
2
5. GATE
2
3. COLLECTOR
1
4. EMITTER
1
5. EMITTER
2
6. COLLECTOR
2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR
1
6. DRAIN
1
6. DRAIN
1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC
−
88/SC70
−
6/SOT
−
363
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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