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November 2016
FDMC007N08LC
N-Channel Shielded Gate PowerTrench
®
MOSFET
80 V, 66 A, 7.0 m
Features
General Description
Shielded Gate MOSFET
T
e
chnology
This N-Channel MV MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench
®
process that
incorporates Shielded Gate technology. This process has been
optimized to minimise on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
Max r
DS(on)
= 7.0 m
at V
GS
= 10 V, I
D
= 21 A
Max r
DS(on)
= 10.4 m
at V
GS
= 4.5 V, I
D
= 17 A
5V Drive Capable
50% lower Qrr than other MOSFET suppliers
Lowers switching noise/EMI
Applications
Primary DC-DC MOSFET
Synchronous Rectifier in DC-DC and AC-DC
Motor Drive
MSL1 robust package design
100% UIL tested
RoHS Compliant
Solar
Pin 1
Pin 1
S
S
S
S
D
D
S
G
S
D
D
D
D
D
D
G
Top
Bottom
Power 33
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
80
±20
V
V
T
C
= 25 °C
T
C
= 100 °C
T
A
= 25 °C
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
66
42
I
D
A
-Continuous
14
-Pulsed
330
E
AS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
150
mJ
W
T
C
= 25 °C
T
A
= 25 °C
57
P
D
(Note 1a)
2.4
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
JC
R
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
2.2
53
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMC007N08L
FDMC007N08LC
Power 33
3000 units
1
©2016 Fairchild Semiconductor Corporation
FDMC007N08LC Rev.1.0
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain to Source Breakdown Voltage
I
D
= 250
A, V
GS
= 0 V
80
V
BV
DSS
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
A, referenced to 25 °C
45
mV/°C
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 64 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
1
A
100
nA
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 120
A
1.0
1.5
2.5
V
V
GS(th)
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 120
A, referenced to 25 °C
-5.4
mV/°C
V
GS
= 10
V
,
I
D
= 21 A
5.7
8.3
9.9
80
7.0
r
DS(on)
Static Drain to Source On Resistance
Forward Transconductance
V
GS
= 4.5
V
,
I
D
= 17 A
10.4
12.2
m
V
GS
= 10
V
,
I
D
= 21 A, T
J
= 125 °C
V
DS
= 5
V
,
I
D
= 21 A
g
FS
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
2100
506
18
2940
710
30
pF
pF
pF
V
DS
= 40 V, V
GS
= 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
0.4
0.8
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
10
2.4
24
2.1
29
14
5
20
10
39
10
41
19
ns
ns
V
DD
= 40
V
, I
D
= 21 A,
V
GS
= 10 V, R
GEN
= 6
Turn-Off Delay Time
Fall Time
ns
ns
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Output Charge
V
GS
= 0 V to 10 V
V
GS
= 0 V to 4.5 V
nC
nC
nC
nC
nC
nC
Q
g
V
DD
= 40 V,
D
= 21 A
I
Q
gs
Q
gd
Q
oss
Q
sync
3
V
DD
= 40 V, V
GS
= 0 V
V
DS
= 0
V
,
I
D
= 21 A
30
27
T
o
tal Gate Charge Sync.
Drain-Source Diode Characteristics
V
GS
= 0 V, I
S
= 2 A
(Note 2)
(Note 2)
0.1
0.1
0.7
0.8
20
27
14
62
1.2
1.3
32
43
22
99
V
SD
Source to Drain Diode
Forward Voltage
V
V
GS
= 0 V, I
S
= 21 A
t
rr
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
ns
nC
ns
I
F
= 10 A, di/dt = 300 A/
s
Q
rr
t
rr
I
F
= 10 A, di/dt = 1000 A/
s
Q
rr
nC
Notes
:
2
1. R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is determined by
the user’s board design.
CA
JA
a.
53 °C/W when mounted
on a 1 in
pad of
2 oz
copper
b.
125 °C/W when mounted
on a
minimum pad of 2 oz
copper
2
2. Pulse Test: Pulse Width < 300
s, Duty cycle < 2.0%.
3. E
of 150 mJ is based on starting T
= 25
°
C, L = 3 mH, I
= 10 A, V
= 80 V, V
= 10 V,
100% test at L = 0.1 mH,
I =
33 A.
AS
J
AS
DD
GS
AS
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2016 Fairchild Semiconductor Corporation
FDMC007N08LC Rev.1.0
2
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
150
5
4
3
2
1
0
V
GS
= 10 V
V
GS
= 8 V
V
GS
= 3 V
120
V
GS
= 6 V
V
GS
= 4.5 V
V
GS
= 4.5 V
90
60
V
GS
= 6 V
V
GS
= 3 V
30
V
GS
= 10 V
V
GS
= 8 V
PULSE DURATION = 80
s
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
0
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
5
0
30
60
90
120
150
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
Figur
e
2
. N
o r m a li z e d On – R e s is ta n c e
vs. Drain Current and Gate Voltage
2.0
50
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
I
D
= 21 A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
GS
= 10 V
40
30
20
10
0
I
D
= 21 A
T
J
= 125
o
C
T
J
= 25
o
C
-75 -50 -25
0
25 50 75
100 125 150
2
3
4
5
6
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figur
e
4
. On-Resistance
vs. Gate to
Source Voltage
150
150
100
V
GS
= 0 V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
120
90
60
30
0
10
V
DS
= 5 V
T
J
= 150
o
C
1
T
J
= 25
o
C
0.1
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0.01
0.001
T
J
= -55
o
C
1
2
3
4
5
6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs. Source Current
©2016 Fairchild Semiconductor Corporation
FDMC007N08LC Rev.1.0
3
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
10
10000
1000
100
10
I
D
= 21 A
C
iss
8
V
DD
= 30 V
C
oss
6
V
DD
= 40 V
4
C
rss
V
DD
= 50 V
2
0
f = 1 MHz
GS
= 0 V
V
1
0
6
12
18
24
30
0.1
1
10
80
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s .
D r a i n
to Source Voltage
100
70
56
42
28
14
0
R
JC
= 2.2
o
C/W
V
GS
= 10 V
T
J
= 25
o
C
T
J
= 100
o
10
C
V
GS
= 4.5 V
T
J
= 125
o
C
1
0.001
0.01
0.1
1
10
100
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
F i g u r e 9 .
U n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum
Continuous Drain
Current vs
Case Temperature
500
100
10000
1000
100
SINGLE PULSE
R
JC
= 2.2
o
C/W
C
= 25
o
C
10
s
T
10
THIS AREA IS
LIMITED BY r
DS(on)
100
s
SINGLE PULSE
T
J
= MAX RATED
R
JC
= 2.2
o
C/W
1
1 ms
10 ms
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
100 ms/DC
100 500
0.1
0.1
10
10
-5
10
-4
10
-3
t, PULSE WIDTH (sec)
10
-2
10
-1
1
1
10
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse
Maximum
Power Dissipation
©2016 Fairchild Semiconductor Corporation
FDMC007N08LC Rev.1.0
4
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
P
DM
0.1
0.1
0.05
0.02
0.01
t
1
t
2
SINGLE PULSE
0.01
NOTES:
(t) = r(t) x R
Z
JC
JC
o
R
= 2.2
C/W
JC
Peak T
= P
x Z
(t) + T
J
DM
JC C
Duty Cycle, D = t
/ t
1
2
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13.
Junction-to-Case Transient Thermal Response Curve
©2016 Fairchild Semiconductor Corporation
FDMC007N08LC Rev.1.0
5
2.37 MIN
SYM
3.40
3.20
A
PKG
C
C
L
L
8
5
(0.45)
B
8
5
2.15 MIN
0.70 MIN
(0.40)
(0.65)
PKG
3.40
3.20
C
PKG
C
L
L
1
4
1
4
PIN 1
INDICATOR
0.42 MIN
(8X)
0.65
1.95
SEE
DETAIL A
LAND PATTERN
RECOMMENDATION
1.95
0.10 C A B
0.37
(8X)
0.27
0.65
0.50
0.30
1
4
C
PKG
L
2.05
1.85
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE
STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
8
5
(0.34)
(0.33) TYP
(0.52 TYP)
(2.27)
B) ALL
DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS
DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-1994.
0.10 C
E) DRAWING
FILE NAME: PQFN08HREV1
0.80
0.70
0.08 C
0.05
0.00
C
SEATING
PLANE
0.25
0.15
SCALE: 2X
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
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Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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