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August 2015
FDMC8097AC
Dual N & P-Channel PowerTrench
®
MOSFET
N-Channel: 150 V, 2.4 A, 155 m
Ω
P-Channel: -150 V, -0.9 A, 1200 m
Ω
Features
General Description
These dual N
and P-Channel
enhancement mode
Power
MOSFE
T
s
a
re produced using Fairchild Semiconductor’s
advanced PowerTrench
®
process that has been especially
tailored to minimize on-state resistance and yet maintain
superior switching performance. Shrinking the area needed for
implementation of active clamp topology; enabling best in class
power density.
Q1: N-Channel
Max r
DS(on)
= 155 m
Ω
at V
GS
= 10 V, I
D
= 2.4 A
Max r
DS(on)
= 212 m
Ω
at V
GS
= 6 V, I
D
= 2 A
Q2: P-Channel
Max r
DS(on)
= 1200 m
Ω
at V
GS
= -10
V
,
I
D
= -0.9 A
Applications
Max r
DS(on)
= 1400 m
Ω
at V
GS
= -6
V
,
I
D
= -0.8 A
Optimised for active clamp forward converters
RoHS Compliant
DC-DC Converter
Active Clamp
Top
Bottom
S1
Pin 1
G1 S1
S1
G2
S2
S2
G1
S1
D1
D2
S1
S1
S2
S2 S2
G2 S2
Power 33
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted.
Symbol
V
DS
V
GS
Parameter
Q1
150
±20
6.3
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-150
±25
V
V
T
C
= 25 °C
C
= 100 °C
(Note 5)
-2.0
T
(Note 5)
3.9
2.4
1a
-1.2
-0.9
1b
I
D
A
-Continuous
T
A
= 25 °C
-Pulsed
(Note 4)
(Note 3)
33
-8.8
E
AS
Single Pulse Avalanche Energy
24
6
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Power Dissipation for Single Operation
T
A
= 25 °C
T
A
= 25 °C
T
C
= 25 °C
1.9
1a
0.8
1c
14
1.9
1b
0.8
1d
10
P
D
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
θ
JA
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
65
1a
155
1c
8.9
65
1b
155
1d
12.5
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
FDMC8097AC
FDMC8097AC
Power 33
12 mm
3000 units
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Type
Min.
Typ.
Max. Units
Off Characteristics
I
I
D
= 250
μ
A, V
GS
= 0 V
D
= -250
μ
A, V
GS
= 0 V
Q1
Q2
150
-150
BV
DSS
Drain to Source Breakdown Voltage
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= -250
μ
A, referenced to 25 °C
Q1
Q2
98
122
mV/°C
I
V
V
DS
= 120 V,
V
GS
= 0 V
DS
= -120 V,
V
GS
= 0 V
Q1
Q2
1
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
μ
A
-1
V
V
GS
= ±20 V, V
DS
= 0 V
GS
= ±25 V, V
DS
= 0 V
Q1
Q2
±100
±100
nA
nA
On Characteristics
V
V
GS
= V
DS
, I
D
= 250
μ
A
GS
= V
DS
, I
D
= -250
μ
A
Q1
Q2
2.0
-2.0
3.1
-3.0
4.0
-4.0
V
GS(th)
Gate to Source Threshold Voltage
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= -250
μ
A, referenced to 25 °C
V
GS
= 10
V
,
I
D
= 2.4 A
Q1
Q2
-9
-6
mV/°C
I
124
155
245
155
212
306
V
V
GS
= 6
V
,
I
D
= 2 A
GS
= 10
V
,
I
D
= 2.4 A, T
J
= 125 °C
Q1
Q2
r
DS(on)
Static Drain to Source On Resistance
m
Ω
V
V
V
GS
= -10
V
,
I
D
= -0.9 A
GS
= -6 V,
I
D
= -0.8 A
GS
= -10 V,
I
D
= -0.9 A, T
J
= 125 °C
930
1030 1400
1682 2171
1200
V
V
DD
= 10
V
,
I
D
= 2.4 A
DD
= -10 V,
I
D
= -0.9 A
Q1
Q2
6.4
0.75
g
FS
Forward Transconductance
S
Dynamic Characteristics
Q1
Q2
279
162
395
230
Q1
C
iss
C
oss
C
rss
R
g
Input Capacitance
pF
pF
pF
Ω
V
DS
= 75
V
,
V
GS
= 0 V, f = 1 MHZ
Q1
Q2
26
13
40
25
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2
V
DS
= -75 V, V
GS
= 0 V, f = 1 MHZ
Q1
Q2
1.4
0.6
5
5
Q1
Q2
0.1
0.1
0.6
3.3
1.5
8.3
Switching Characteristics
Q1
Q2
5.4
5.2
11
11
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
ns
ns
Q1
V
V
DD
= 75 V, I
D
= 2.4 A,
GS
= 10 V, R
GEN
= 6
Ω
Q1
Q2
1.3
1.6
10
10
Q1
Q2
9.1
7.4
18
15
Q2
Turn-Off Delay Time
Fall Time
ns
V
DD
= -75 V, I
D
= -0.9 A,
Q1
Q2
2.2
6.3
10
13
V
GS
= -10
V
,
R
GEN
= 6
Ω
ns
V
V
GS
= 0 V to 10 V
GS
= 0 V to -10 V
Q1
Q2
4.4
2.8
6.2
4.0
Q
g(TOT)
Q
g(TOT)
Q
gs
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source
Charge
Gate to Drain “Miller” Charge
nC
nC
nC
nC
Q1
V
DD
= 75 V,
V
V
GS
= 0 V to 6 V
GS
= 0 V to -6 V
Q1
Q2
2.9
1.8
4.1
2.6
I
D
= 2.4 A
Q1
Q2
1.3
0.8
Q2
V
DD
= -75 V
Q1
Q2
1.0
0.7
I
D
= -0.9 A
Q
gd
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
2
Electrical Characteristics
T
J
= 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Type
Min.
Typ.
Max. Units
Drain-Source Diode Characteristics
V
V
GS
= 0 V, I
S
= 2.4 A
GS
= 0 V, I
S
= -0.9 A
(Note 2)
Q1
(Note 2)
Q2
0.8
-0.9
1.3
V
V
SD
t
rr
Source-Drain Diode
Forward Voltage
Reverse Recovery Time
-1.3
Q1
Q2
50
44
80
ns
71
Q1
I
F
= 2.4 A, di/dt = 100 A/s
Q2
I
F
= -0.9 A, di/dt = 100 A/s
Q1
Q2
43
68
69
nC
Q
rr
Reverse Recovery Charge
109
Notes:
2
1.
R
is determined with the device mounted on a 1in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined
θ
CA
θ
JA
θ
JC
by the
user’s board design.
b. 65 °C/W when mounted on
a 1 in
pad of
2 oz
copper
a. 65 °C/W when mounted on
a 1 in
pad of
2 oz
copper
2
2
d. 155 °C/W when mounted on
minimum pad of 2 oz copper
a
c. 155 °C/W when mounted on
a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300
μ
s, Duty cycle < 2.0%.
o
3. Q1: E
of 24 mJ is based on starting T
= 25
C, L = 3 mH, I
= 4 A, V
= 150 V, V
= 10 V. 100% test at L = 0.1 mH, I
= 14 A.
AS
J
AS
DD
GS
AS
o
Q2: E
of 6 mJ is based on starting T
= 25
C, L = 3 mH, I
= -2 A, V
= -150 V, V
= -10 V. 100% test at L = 0.1 mH, I
= -8 A.
AS
J
AS
DD
GS
AS
4. Q1: Pulsed Id please refer to Fig 11 SOA graph for more details.
Q2: Pulsed Id please refer to Fig 24 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
3
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted.
10
8
4
3
2
1
0
V
GS
= 10 V
V
GS
= 6 V
V
GS
= 4.5 V
V
GS
= 5 V
V
GS
= 5.5 V
V
GS
= 5.5 V
6
V
GS
= 6 V
4
V
GS
= 5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
2
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 4.5 V
0
0
1
2
3
4
5
0
2
4
6
8
10
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s ta n c e
vs. Drain Current and Gate Voltage
2.5
500
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 2.4 A
V
GS
= 10 V
I
D
= 2.4 A
400
300
200
100
0
2.0
1.5
1.0
0.5
T
J
= 125
o
C
T
J
= 25
o
C
-75 -50 -25
0
25 50 75
100 125 150
4
5
6
7
8
9
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figur
e
4
. On-Resistance
vs. Gate to
Source Voltage
10
20
10
V
GS
= 0 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
8
6
4
2
0
V
DS
= 5 V
1
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= 150
o
C
0.1
T
J
= 25
o
C
0.01
T
J
= -55
o
C
T
J
= -55
o
C
0.001
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
4
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted.
1000
100
10
10
8
I
D
= 2.4 A
C
iss
V
DD
= 50 V
V
DD
= 75 V
V
DD
= 100 V
C
oss
6
4
C
rss
2
f = 1 MHz
GS
= 0 V
V
1
0.1
0
0
1
2
3
4
5
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s . D r a i n
to Source Voltage
20
8
6
4
2
0
R
θ
JC
= 8.9
o
C/W
10
T
J
= 25
o
C
V
GS
= 10 V
T
J
= 100
o
C
V
GS
= 6 V
T
J
= 125
o
C
1
0.001
0.01
0.1
1
10
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figur
e
9
. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs.
Case Temperature
100
10
10000
SINGLE PULSE
R
θ
JC
= 8.9
o
C/W
C
= 25
o
C
10
μ
s
T
1000
100
10
100
μ
s
1
THIS AREA IS
LIMITED BY r
DS(on)
SINGLE PULSE
T
J
= MAX RATED
R
θ
JC
= 8.9
o
C/W
1 ms
0.1
0.01
10 ms
DC
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
10
-5
10
-4
10
-3
t, PULSE WIDTH (sec)
10
-2
10
-1
1
0.1
1
10 100
1000
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figur
e
1
1. Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse Maximum Power
Dissipation
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
5
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
P
DM
0.1
0.1
0.05
0.02
0.01
t
1
t
2
NOTES:
(t) = r(t) x R
θ
JC
0.01
Z
SINGLE PULSE
θ
JC
o
R
= 8.9
C/W
θ
JC
Peak T
= P
x Z
(t) + T
J
DM
θ
JC C
Duty Cycle, D = t
/ t
1
2
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13.
Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
6
Typical Characteristics (Q2 P-Channel)
T
J
= 25 °C unless otherwise noted
4
1.8
V
GS
= -10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= -5 V
V
GS
= -7 V
1.6
3
V
GS
= -6 V
V
GS
= -5.5 V
V
GS
= -5.5 V
V
GS
= -5 V
1.4
1.2
1.0
0.8
2
1
0
V
GS
= -10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= -7 V
V
GS
= -6 V
0
1
2
3
4
5
0
1
2
3
4
-V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
-I
D
,
DRAIN CURRENT (A)
Figure 14.
On- Region Characteristics
Figure 15. Normalized on-Resistance vs. Drain
Current and Gate
Voltage
3000
2.2
2.0
I
D
= -0.9 A
GS
= -10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
2500
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
I
D
= -0.9
A
2000
T
J
= 125
o
C
1500
1000
T
J
= 25
o
C
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75
100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
-V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs. Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs. Junction Temperature
4
5
V
GS
= 0 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
1
3
V
DS
= -5 V
T
J
= 150
o
C
0.1
0.01
T
J
= 25
o
C
2
T
J
= 150
o
C
T
J
= 25
o
C
1
0
T
J
= -55
o
C
T
J
= -55
o
C
0.001
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-V
GS
, GATE TO SOURCE VOLTAGE (V)
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
7
Typical Characteristics (Q2 P-Channel)
T
J
= 25°C unless otherwise noted
1000
100
10
10
8
I
D
= -0.9 A
C
iss
V
DD
= -75 V
V
DD
= -50 V
C
oss
6
V
DD
= -100 V
4
C
rss
1
f = 1 MHz
V
GS
= 0 V
2
0.1
0
0.1
1
10
100
150
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 21. Capacitance vs. Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
2.5
2.0
1.5
1.0
0.5
0.0
20
10
T
J
= 25
o
C
V
GS
= -10 V
T
J
= 100
o
C
V
GS
= -6 V
T
J
= 125
o
C
R
θ
JC
= 12.5
o
C/W
1
0.001
0.01
0.1
1
25
50
75
100
125
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figure 22. Unclamped Inductive
Switching Capability
F ig ure 23 . Ma ximum
C on tin uo us
D rain
Current vs.
Case Temperature
20
10
500
SINGLE PULSE
R
θ
JC
= 12.5
o
C/W
C
= 25
o
T
C
100
10
1
100
μ
s
1
0.1
THIS AREA IS
LIMITED BY r
DS(on)
1 ms
SINGLE PULSE
T
J
= MAX RATED
R
θ
JC
= 12.5
o
C/W
10 ms
DC
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
0.01
10
-4
10
-3
10
-2
10
-1
1
10
100
500
-V
DS
, DRAIN to SOURCE VOLTAGE (V)
t, PULSE WIDTH (sec)
Figure 24. Forward Bias Safe
Operating Area
Figure 25. Single Pulse
Maximum Power
Dissipation
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
8
Typical Characteristics (Q2 P-Channel)
T
J
= 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
P
DM
0.05
0.02
0.01
t
1
0.1
t
2
NOTES:
(t) = r(t) x R
SINGLE PULSE
Z
θ
JC
θ
JC
o
R
= 12.5
C/W
θ
JC
Peak T
= P
x Z
(t) + T
J
DM
θ
JC C
Duty Cycle, D = t
/ t
1
2
0.01
10
-4
10
-3
10
-2
10
-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
9
2.52
(0.20)
0.10 C
A
3.00
2X
B
5
8
0.75(2X)
(0.35)
3.30
3.00
2.26
PIN#1
IDENT AREA
(0.20)2X
0.52
0.45
0.10 C
1
4
1.75
TOP VIEW
2X
RECOMMENDED LAND PATTERN
0.80 MAX
0.10 C
0.08 C
(0.20)
NOTES:
0.05
0.00
C
A. DOES NOT FULLY CONFORM TO
JEDEC REGISTRATION, MO-229.
SEATING
PLANE
SIDE VIEW
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
ꢈꢁꢃꢀꢀꢁꢀꢃ
0.30 (2X)
PIN #1
IDENT
(1.65)
(0.35)
4X
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN
ONLY
A
1
4
ꢀꢁꢉꢃꢃꢀꢁꢀꢃꢄꢅꢈ;ꢇ
E. DRAWING FILE NAME: MKT-MLP08Xrev2.
0.163
(0.35)
(0.25) 2X
ꢀꢁꢂꢈꢀꢁꢀꢃꢄꢅꢆ;ꢇ
ꢀꢁꢂꢈꢀꢁꢀꢃ
(2X)
0.10
0.05
C A B
8
C
5
ꢀꢁꢂꢃꢀꢁꢀꢃ
(2X)
ꢀꢁꢂꢃꢀꢁꢀꢃꢄꢅꢆ;ꢇ
0.30 (4X)
0.65
BOTTOM VIEW
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