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2015
年
3
月
FDMC86160ET100
N
沟道屏蔽栅极
Power Trench
®
MOSFET
100 V
，
43 A
，
14 m
Ω
特性
概述
T
J
额定值扩展：
175°C
此
N
沟
道
MOSFET
采
用
Fairchild
带
屏蔽栅极技术的先进
PowerTrench
®
工艺生产。该工艺针对导通电阻进行了优化。此
器件非常适合需要在小空间内实现超低
R
D
S
（
on
）的应用，例如
高 性能
VRM
、
POL
和
Orring
功能。
屏蔽栅极
MOSFET
技术
最大
r
DS(on)
= 14 m
Ω
（
V
GS
= 10 V
，
I
D
= 9 A
）
最大
r
DS(on)
= 23 m
Ω
（
V
GS
= 6 V
，
I
D
= 7 A
）
高性能沟道技术可实现极低的
r
DS(on)
终端无引线且符合
RoHS
标准
应用
桥式拓扑
同步整流器
引脚
1
引脚
1
S
S
S
S
D
D
S
G
S
D
D
D
D
D
D
G
顶
底
Power 33
MOSFET
最大额定值
T
A
= 25 °C
除非另有说明
符号
参数
额定值
单位
V
DS
V
GS
100
V
漏极－源极电压
栅极－源极电压
漏极电流
±20
V
43
–
连续
–
连续
–
连续
–
脉冲
T
C
= 25 °C
（注
5
）
（注
5
）
（注
1a
）
（注
4
）
（注
3
）
31
T
C
= 100 °C
T
A
= 25 °C
I
D
A
9
204
E
AS
P
D
181
mJ
W
单脉冲雪崩能量
功耗
65
T
C
= 25 °C
T
A
= 25 °C
2.8
功耗
（注
1a
）
T
J
, T
STG
°C
工作和存储结温范围
-55
至
+175
热性能
R
θ
JC
R
θ
JA
2.3
53
结至外壳热阻
结至环境热阻
（注
1
）
°C/W
（注
1a
）
封装标识与定购信息
器件标识
器件
FDMC86160ET100
封装
卷尺寸
13 ’’
带宽
12 mm
数量
FDMC86160ET
Power33
3000
个
1
© 2015
飞兆半导体公司
FDMC86260ET150
修订版
C1
电气特性
T
J
= 25°C
除非另有说明
符号
参数
测试条件
最小值 典型值 最大值
单位
关断特性
BV
DSS
I
D
= 250
μ
A, V
GS
= 0 V
100
V
漏极－源极击穿电压
Δ
BV
DSS
Δ
T
J
I
D
= 250
μ
A,
参考温度为
25 °C
73
mV/°C
击穿电压温度系数
I
DSS
I
GSS
V
DS
= 80 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
1
μ
A
nA
零栅极电压漏极电流
栅极－源极漏电流
±100
导通特性
V
GS(th)
V
GS
= V
DS
, I
D
= 250
μ
A
2
2.9
-9
4
V
栅极－源极阈值电压
Δ
V
GS(th)
Δ
T
J
I
D
= 250
μ
A,
参考温度为
25 °C
mV/°C
栅极－源极阈值电压温度系数
V
GS
= 10 V,
I
D
= 9 A
11.2
16
14
23
26
r
DS(on)
V
GS
= 6 V,
I
D
= 7 A
m
Ω
漏极至源极静态导通电阻
正向跨导
V
GS
= 10 V,
I
D
= 9 A, T
J
= 125 °C
V
DD
= 10 V,
I
D
= 9 A
21
g
FS
43
S
动态特性
C
iss
C
oss
C
rss
R
g
968
241
11
1290
320
20
pF
pF
pF
Ω
输入电容
V
DS
= 50 V, V
GS
= 0 V,
f = 1 MHz
输出电容
反向传输电容
栅极阻抗
0.1
0.6
2.5
开关特性
t
d(on)
t
r
t
d(off)
t
f
9.7
3.6
16
19
10
30
10
22
15
ns
ns
导通延迟时间
上升时间
V
V
DD
= 50
V
,
I
D
= 9 A,
GS
= 10 V, R
GEN
= 6
Ω
ns
关断延迟时间
下降时间
3.4
15
ns
Q
g(TOT)
Q
g(TOT)
Q
gs
nC
nC
nC
nC
总栅极电荷
V
GS
= 0 V
至
10 V
V
GS
= 0 V
至
6 V
9.8
4.4
3.5
总栅极电荷
V
DD
= 50 V,
I
D
= 9 A
总栅极电荷
Q
gd
栅极－漏极
“
米勒
”
电荷
漏极
－
源极二极管特性
0.79
0.72
47
1.3
1.2
75
V
V
V
GS
= 0 V
，
I
S
= 9 A
（注
2
）
（注
2
）
V
SD
源极－漏极二极管正向电压
V
GS
= 0 V
，
I
S
= 1.9 A
t
rr
ns
nC
反向恢复时间
反向恢复电荷
I
F
= 9 A, di/dt = 100 A/
μ
s
Q
rr
注意：
45
73
1. R
取决于安装在一平方英寸衬垫，
2 oz
铜焊盘以及
FR-4
材质尺寸
1.5 x 1.5in.
的衬垫上的器件。
R
由用户的电路板设计确定。
θ
JA
θ
CA
2
53
安装在
2 oz
最小
1 in
焊盘上时的
°C/W
铜
125
安装在
2 oz
最小铜焊盘上
时的
°C/W
b.
a.
2.
脉冲测试：脉冲宽度：
<30
0
μ
s
，占空比：
< 2.0%
。
3. E
为
181 mJ
，根据起始
T =
25
°
C
、
L = 3 mH
、
I =
11 A
、
V =
100 V
、
V =
10 V
。 在
L = 0.1 mH
、
I =
35 A
时进行
100%
测试。
AS
J
AS
DD
GS
AS
4.
有关脉冲编号的更多详情，请参考图
11
中的
SOA
图形。
5.
计算得到的连续电流仅限于最大结温，实际连续电流将受限于散热以及电气机械应用的电路板设计。
© 2015
飞兆半导体公司
FDMC86260ET150
修订版
C1
2
典型特性
T
J
= 25°C
除非另有说明
80
5
4
3
2
1
0
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 4.5 V
V
GS
= 5 V
V
GS
= 10 V
V
GS
= 7 V
60
40
20
0
V
GS
= 6 V
V
GS
= 5.5 V
V
GS
= 6 V
V
GS
= 5.5 V
V
GS
= 5 V
V
GS
= 4.5 V
V
GS
= 7 V
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
5
0
20
40
60
80
I
D
,
DRAIN CURRENT (A)
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
图
1.
通态区域特性
图
2.
标准化导通电阻与漏极电流和栅极电压的关系
60
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 9 A
GS
= 10 V
I
D
= 9 A
V
50
40
30
T
J
= 150
o
C
20
10
0
T
J
= 25
o
C
-75 -50 -25
0
25 50 75
100 125 150 175
4
5
6
7
8
9
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
图
3.
标准化导通电阻与结温的关系
图
4.
导通电阻与栅极
–
源极电压的关系
100
80
60
40
20
0
V
GS
= 0 V
V
DS
= 5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
10
T
J
= 175
o
C
1
T
J
= 25
o
C
0.1
T
J
= 175
o
C
T
J
= 25
o
C
0.01
T
J
= -55
o
C
T
J
= -55
o
C
0.001
2
3
4
5
6
7
8
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
图
5.
转换特性
图
6.
源极
–
漏极二极管正向电压与源电流的关系
© 2015
飞兆半导体公司
FDMC86260ET150
修订版
C1
3
典型特性
T
J
= 25°C
除非另有说明
10
10000
1000
100
10
I
D
= 9 A
V
DD
= 50 V
C
iss
8
6
4
2
0
V
DD
= 25 V
V
DD
= 75 V
C
oss
C
rss
f = 1 MHz
GS
= 0 V
V
1
0
4
8
12
16
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
g
图
7.
栅极电荷特性
图
8.
电容与漏极
–
源极电压的关系
100
10
1
50
40
30
20
10
0
V
GS
= 10 V
T
J
= 25
o
C
T
J
= 100
o
C
V
GS
= 6 V
T
J
= 150
o
C
R
θ
JC
= 2.3
o
C/W
50
0.001
0.01
0.1
1
10
100
25
75
100
125
150
175
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
图
9.
非箝位电感开关能力
图
10.
最大连续漏极电流与壳温的关系
10000
1000
100
500
100
10
μ
s
10
1
THIS AREA IS
LIMITED BY r
DS(on)
100
μ
s
SINGLE PULSE
T
J
= MAX RATED
SINGLE PULSE
R
θ
JC
= 2.3
o
C/W
T
C
= 25
o
C
1 ms
R
θ
JC
= 2.3
o
C/W
10 ms
DC
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
10
0.1
0.1
10
-5
10
-4
10
-3
10
-2
10
-1
1
1
10
100
500
V
DS
, DRAIN to SOURCE VOLTAGE (V)
t, PULSE WIDTH (sec)
图
11.
正向偏压安全工作区
图
12.
单个脉冲最大功耗
© 2015
飞兆半导体公司
FDMC86260ET150
修订版
C1
4
典型特性
T
J
= 25°C
除非另有说明
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
P
0.05
0.02
0.01
DM
0.1
t
1
t
2
注：
0.01
0.001
SINGLE PULSE
Z
(t) = r(t) x R
θ
JC
θ
JC
R
= 2.3
°C/W
θ
JC
峰值
T
= P
占空比
D = t
/ t
x Z
(t) + T
θ
JC
C
J
DM
1
2
10
-5
10
-4
10
-3
10
-2
10
-1
1
t, RECTANGULAR PULSE DURATION (sec)
图
13.
结至外壳瞬态热响应曲线
© 2015
飞兆半导体公司
FDMC86260ET150
修订版
C1
5
2.37 MIN
SYM
3.40
3.20
A
PKG
C
C
L
L
8
5
(0.45)
B
8
5
2.15 MIN
0.70 MIN
(0.40)
(0.65)
PKG
3.40
3.20
C
PKG
C
L
L
1
4
1
4
PIN 1
INDICATOR
0.42 MIN
(8X)
0.65
1.95
SEE
DETAIL A
LAND PATTERN
RECOMMENDATION
1.95
0.10 C A B
0.37
(8X)
0.27
0.65
0.50
0.30
1
4
C
PKG
L
2.05
1.85
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE
STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
8
5
(0.34)
(0.33) TYP
(0.52 TYP)
(2.27)
B) ALL
DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS
DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-1994.
0.10 C
E) DRAWING
FILE NAME: PQFN08HREV1
0.80
0.70
0.08 C
0.05
0.00
C
SEATING
PLANE
0.25
0.15
SCALE: 2X
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
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−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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