onsemi-FDMC8878

Part #onsemi-FDMC8878
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onsemi-FDMC8878
November 2013  
FDMC8878  
N-Channel Power Trench

®

MOSFET
ꢀ
 
30V, 16.5A, 14m
ꢁ
 
Features  
General Description  
 
 
Max r

DS(on)

= 14m
ꢁ
at V

GS

= 10V, I

D

= 9.6A  
This N-Channel MOSFET is  
Fairchild Semiconductor‘s  
process. It has been optimized for power management  
applications.  
a
rugged gate version
 
of  
advanced  
Power  
Trench  
 
 
Max r

DS(on)

= 17m
ꢁ
at V

GS

= 4.5V, I

D

= 8.7A  
 
 
Low Profile – 0.8 mm max in  
 
 
RoHS Compliant  
MLP 3.3
X
3.3  
Application  
 
 
DC – DC Conversion  
Bottom  
D D  
Top  
D
D
5
8
7
6
G
S
D
D
D
D
5
6
7
8
4
3
2
1
S
S
G S  
S
Pin 1  
S
1
2
3
4
MLP 3.3×3.3  
MOSFET Maximum Ratings
T

A

= 25°C unless otherwise noted  
Symbol  
V

DS  

V

GS  

Parameter  
Ratings  
Units  
V
V
Drain to Source Voltage  
Gate to Source Voltage  
30  
20  
Drain Current
 
-Continuous (Package limited)  
-Continuous (Silicon limited)  
-Continuous  
-Pulsed  
Power Dissipation  
T

C

= 25°C  
T

C

= 25°C  
T

A

= 25°C  
16.5  
38  
9.6  
60  
31  
I

D  

A
(Note 1a)  
(Note 1a)  
T

C

= 25°C  
T

A

= 25°C  
P

D  

W
Power Dissipation  
2.1  
T

J

, T

STG  

Operating and Storage Junction
T
e
mperature Range  
-55 to +150  
°
C  
Thermal Characteristics  
R

ꢂ
JC  

R

ꢂ
JA  

Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
4
°C/W  
(Note 1a)  
60  
Package Marking and Ordering Information  
Device Marking  
FDMC8878  
Device  
FDMC8878  
Package  
MLP 3.3
X
3.3  
Reel Size  
13
”  
Tape Width  
12
m
m  
Quantity  
3
000 units  
1
©20
1
2
Fairchild Semiconductor Corporation  
FDMC8878 Rev.
D
5  

Electrical Characteristics
T

J

= 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BV

DSS  

Drain to Source Breakdown Voltage  
I

D

= 250
ꢃ
A, V

GS

= 0V  
I

D

= 250
ꢃ
A, referenced to 25°C  
V

DS

= 24V,  
30  
V
ꢄ
BV

DSS  

ꢀꢀꢀꢄ
T

J  

Breakdown Voltage
T
e
mperature  
Coefficient  
20  
mV/°
C  
1
100  
100  
I

DSS  

I

GSS  

Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
ꢃ
A  
V

GS

= 0V  
T

J

= 125°C  
V

GS

20V, V

DS

= 0V  
=
nA  
On Characteristics  
V

GS(th)  

Gate to Source Threshold Voltage  
V

GS

= V

DS

, I

D

= 250
ꢃ
A  
1
1.7  
3
V
ꢀꢄ
V

GS(th)  

ꢀꢀꢀꢄ
T

J  

Gate to Source Threshold Voltage  
T
e
mperature Coefficient  
I

D

= 250
ꢃ
A, referenced to 25°C  
-5.7  
mV/°C  
V
V

GS

= 10V,
 
I

D

= 9.6A  

GS

= 4.5V,
 
I

D

= 8.7A  
9.6  
12.1  
13.5  
35  
14.0  
17.0  
20.0  
r

DS(on)  

Drain to Source On Resistance  
m
ꢁ  
V

GS

= 10
V
,
 
I

D

= 9.6A , T

J

= 125°C  
V

DS

= 5V,
 
I

D

= 9.6A  
g

FS  

Forward Transconductance  
S
Dynamic Characteristics  
C

iss  

C

oss  

C

rss  

R

g  

Input Capacitance  
1000  
183  
118  
1.1  
1230  
255  
180  
pF  
pF  
pF  
ꢁ
V

DS

= 15V, V

GS

= 0V,  
f = 1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
f = 1MHz  
Switching Characteristics  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn-On Delay Time  
Rise Time  
Turn-Off Delay Time  
Fall Time  
8
4
20  
3
18  
2.8  
3.9  
16  
10  
36  
10  
26  
ns  
ns  
ns  
V

DD

= 15
V
,
I

D

= 9.6A  
V

GS

= 10V, R

GEN

= 6
ꢁ  
ns  
Q

g(TOT)  

Q

gs  

Q

gd  

T
o
tal Gate Charge  
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
nC  
nC  
nC  
V

GS

= 10V , V

DD

= 15V ,  
I

D

= 9.6A  
Drain-Source Diode Characteristics  
V

SD  

Source to Drain Diode
 
Forward Voltage  
V

GS

= 0V, I

S

= 9.6A
 
(Note 2)  
0.8  
23  
14  
1.2  
35  
21  
V
ns  
nC  
t

rr  

Reverse Recovery Time  
I

F

= 9.6A, di/dt = 100A/
ꢃ
s  
Q

rr  

Reverse Recovery Charge  
Notes:  
2
1:  
R
is determined with the device mounted on a 1in
 
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R  
is guaranteed by design while
R
is determined by  
ꢂ
CA  
ꢂ
JA  
ꢂ
JC  
the user’s board design.  
b. 135°C/W when mounted on  
minimum pad of 2 oz copper  
a
a. 60°C/W when mounted
 
on  
2
a 1 in
 
pad of
 
2 oz
 
copper  
2:
Pulse
T
e
st: Pulse Width < 30
0
ꢃ
s, Duty cycle < 2.0%.  
©20
1
2
Fairchild Semiconductor Corporation  
2
FDMC8878 Rev.  
D
5  

Typical Characteristics

T

J

= 25°C unless otherwise noted  

2.5  
2.0  
1.5  
1.0  
0.5  
60  
PULSE DURATION = 80
ꢃ
s  
DUTY CYCLE = 0.5%MAX  
V
= 10V  
50  
40  
30  
20  
10  
0
GS  
V
= 3.5V  
GS  
V

GS

= 3V  
V

GS

= 4V  
V

GS

= 4.5V  
V
= 4.5V  
= 4V  
GS  
V
GS  
V

GS

= 3.5V  
V
= 3V  
GS  
V

GS

= 10V  
PULSE DURATION = 80
ꢃ
s  
DUTY CYCLE = 0.5%MAX  
0
10  
20  
30  
40  
50  
60  
0
1
2
3
4
V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
I ,
 
DRAIN CURRENT(A)  
D
Figure 1.
 
On-Region Characteristics  
Figur
e
2
. No
 
r m a l i z e d O n – R e s i s ta n c e  
vs Drain Current and Gate Voltage  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
30  
PULSE DURATION = 80
ꢃ
s  
I
V
= 9.6A  
D
I
D
= 9.6A  
DUTY CYCLE = 0.5%MAX  
= 10V  
GS  
25  
20  
15  
10  
5
T
J
= 125

o

C  
T
J
= 25

o

C  
7
-75 -50 -25  
0
25 50 75
 
100 125 150  
3
4
5
6
8
9
10  
T

J

, JUNCTION TEMPERATURE
(

o

C
)  
V

GS

, GATE TO SOURCE VOLTAGE (V)  
F i gu re 3 .
 
N orma li zed
 
On – Res is ta nc e  
vs Junction Temperature  
Figur
e
4
. On-Resistance
 
vs Gate to  
Source Voltage  
60  
100  
10  
PULSE DURATION = 80
ꢃ
s  
V
GS  
= 0V  
DUTY CYCLE = 0.5%MAX  
50  
40  
30  
20  
10  
0
V
= 5V  
DD  
1
T
J
= 25

o

C  
T =
 
150

o

C  
J
T
= 25

o

C  
J
0.1  
T
J
= -55

o

C  
T
J
= -55

o

C  
T =
 
150

o

C  
J
0.01  
0.001  
0
1
2
3
4
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
SD  
, BODY DIODE FORWARD VOLTAGE (V)  
V

GS

, GATE TO SOURCE VOLTAGE (V)  
Figure 5.
 
Transfer Characteristics  
Figur
e
6
. Source
 
to Drain Diode  
Forward Voltage vs Source Current  
3
©20
1
2
Fairchild Semiconductor Corporation  
FDMC8878 Rev.  
D
5  

Typical Characteristics
T

J

= 25°C unless otherwise noted  
10  
3000  
1000  
I
= 9.6A  
D
V
= 15V  
DD  
C
iss  
8
6
4
2
0
V
DD  
= 10V  
C
oss  
V
DD  
= 20V  
C
rss  
f = 1MHz  
= 0V  
100  
50  
V
GS  
30  
0.1  
1
10  
0
5
10  
15  
20  
V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
Q ,
 
GATE CHARGE(nC)  
g
Figure 7.
 
Gate Charge Characteristics  
Figur
e
8
. Ca
 
p a c i t a n c e v s D r a i n  
to Source Voltage  
12  
10  
8
20  
10  
V
GS  
= 10V  
T
J
= 25

o

C  
6
V
GS  
= 4.5V  
T
J
= 125

o

C  
4
2
R
ꢂ
JA  
= 60

o

C/W  
50  
1
0
80  
0.01  
0.1  
1
10  
25  
75  
100  
125  
150  
T

A

, AMBIENT TEMPERATURE
(

o

C
)  
t

AV

, TIME IN AVALANCHE(ms)  
Figur
e
9
. U
 
n c l a m p e d I n d u c t i v e  
Switching Capability  
Figur
e
1
0. Maximum Continuous Drain  
Current vs
 
Ambient Temperature  
300  
80  
o
T
= 25
 
C  
V

GS

= 10V  
A
100us  
FOR TEMPERATURES  
ABOVE 25
 
C DERATE PEAK  
CURRENT AS FOLLOWS:  
100  
10  
10  
1
o
1ms  
150
–
T  
10ms  
A
———————-  
I = I  
25  
125  
100ms  
1s  
10s  
DC  
OPERATION IN THIS  
AREA MAY BE  
LIMITED BY r

DS(on)  

0.1  
SINGLE PULSE  
0.01  
T
= MAX RATED  
J
SINGLE PULSE  
T
= 25

o

C  
1
A
0.5  
0.001  
10

-3  

10

-2  

10

-1  

t, PULSE WIDTH (s)  
10

0  

10

1  

10

2  

10

3  

0.1  
1
10  
80  
V
DS  
, DRAIN to SOURCE VOLTAGE (V)  
Figure 11.
 
Forward Bias Safe  
Operating Area  
Figur
e
1
2. Single Pulse
 
Maximum  
Power Dissipation  
4
©20
1
2
Fairchild Semiconductor Corporation  
FDMC8878 Rev.  
D
5  

Typical Characteristics
T

J

= 25°C unless otherwise noted  
2
DUTY CYCLE-DESCENDING ORDER  
1
D = 0.5  
0.2  
0.1  
0.05  
0.02  
0.1  
P
0.01  
DM  
t
1
t
2
0.01  
NOTES:  
DUTY FACTOR: D = t
 
/t  
1
2
SINGLE PULSE  
0.003  
PEAK T
 
= P  
x Z  
x R  
+ T  
J
DM  
ꢂ
JA  
ꢂ
JA
A  
10

-3  

10

-2  

10

-1  

10

0  

10

1  

10

2  

10

3  

t, RECTANGULAR PULSE DURATION (s)  
Figure 13.
 
Transient Thermal Response Curve  
5
©20
1
2
Fairchild Semiconductor Corporation  
FDMC8878 Rev.  
D
5  

(3.40)  
2.37  
0.05 C  
B
3.30  
A
8
5
2X  
0.45(4X)  
(0.40)  
2.15  
(1.70)  
3.30  
KEEP OUT  
AREA  
(0.65)  
0.70(4X)  
0.05 C  
PIN#1 IDENT  
1
4
TOP VIEW  
SIDE VIEW  
0.65  
0.42(8X)  
2X  
1.95  
ꢀꢁꢅꢃ“ꢀꢁꢀꢃ  
RECOMMENDED LAND PATTERN  
0.10 C  
0.08 C  
ꢀꢁꢂꢃ“ꢀꢁꢀꢃ  
ꢀꢁꢀꢄꢃ“ꢀꢁꢀꢄꢃ  
NOTES:  
C
SEATING  
A. DOES NOT CONFORM TO JEDEC  
REGISTRATION MO-229  
PLANE  
B. DIMENSIONS
 
ARE IN MILLIMETERS.  
ꢆꢁꢆꢀ“ꢀꢁꢀꢃ  
C. DIMENSIONS
 
AND TOLERANCES PER  
ASME Y14.5M, 2009.  
2.27+0.05  
(0.50)4X  
PIN #1 IDENT  
(0.79)  
D. LAND
 
PATTERN RECOMMENDATION IS  
EXISTING INDUSTRY LAND PATTERN.  
1
4
ꢀꢁꢃꢀ“ꢀꢁꢀꢃꢇꢊ;ꢉ  
E. DRAWING
 
FILENAME: MKT-MLP08Srev3.  
(0.35)  
(1.15)  
ꢆꢁꢆꢀ“ꢀꢁꢀꢃ  
R0.15  
ꢄꢁꢀꢀ“ꢀꢁꢀꢃ  
ꢀꢁꢆꢀ“ꢀꢁꢀꢃꢇꢆ;ꢉ  
8
5
ꢀꢁꢆꢃ“ꢀꢁꢀꢃꢇꢈ;ꢉ  
0.65  
0.10  
C A B  
1.95  
0.05  
C
BOTTOM VIEW  

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Definition of Terms  
Datasheet Identification  
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Definition  
Datasheet contains the design specifications for product development. Specifications may change  
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Advance Information  
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Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild  
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Rev. I77  
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