onsemi-FDMF2011
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DATA SHEET
High Performance 100 V
Smart Power Stage Module
FDMF2011
PQFN36 6X7.5, 0.5P
CASE 483BB
General Description
The FDMF2011 is a compact 100 V Smart Power Stage (SPS)
module that is a fully optimized for use in high current switching
applications. The FDMF2011 module integrates a driver IC plus two
N−channel Power MOSFETs into a thermally enhanced, 6.0 mm x
7.5 mm
PQFN package. The PQFN packaging provides very low
package inductance and resistance improving the current handling
capability and performance of the part. With an integrated approach,
the complete switching power stage is optimized with regards to driver
and MOSFET dynamic performance, system parasitic inductance, and
MARKING DIAGRAM
$Y&Z&3&K
FDMF
2011
$Y
&Z
&3
&K
= Logo
Power MOSFET R
. The FDMF2011 uses
onsemi
’s high
DS(ON)
®
= Assembly Plant Code
= 3−Digit Date Code Format
= 2−Digits Lot Run Traceability Code
performance POWERTRENCH
MOSFET technology, which
reduces high voltage and current stresses in switching applications.
The driver IC features a low delay times and matched PWM input
propagation delays, which further enhance the performance of the
part.
FDMF2011 =
Device Code
Features
ORDERING INFORMATION
•
Compact Size – 6.0 mm x 7.5 mm PQFN
•
High Current Handling: 20 A
•
Next Generation 100 V Power MOSFETs:
this data sheet.
♦
Typ. R
= 7.7 (HS) / 7.3 (LS) m
W
at V
= 10
V
, I
=
2
0 A
GS D
DS(ON)
•
Wide Driver Power Supply
V
o
ltage Range: 10 V to 20 V
•
Internal Pull−down Resistors for PWM Inputs (HI, LI)
•
Short PWM Propagation Delays
•
Under−voltage Lockout (UVLO)
•
Fully Optimized System Efficiency
•
High Performance Low Profile Package
•
Integrated 100 V Half−Bridge Gate Driver
•
onsemi
100 V POWERTRENCH MOSFETs for Clean Switching
Waveforms and Reduced Ringing
•
Low Inductance and Low Resistance Packaging for Minimal
Operating Power Losses
•
onsemi
Green Packaging and RoHS Compliant
•
Reduced EMI due to Low Side Flip−chip MOSFET
Applications
•
Motor Drives (Power Tools & Drowns etc.)
•
Telecom Half / Full − Bridge DC−DC Converters
•
Buck−Boost Converters
•
High−current DC−DC Point of Load (POL) Converters
©
Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
March
, 2022 − Rev. 2
FDMF2011/D
FDMF2011
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
PIN CONFIGURATION
Figure 2. Pin Configur
tion (
.0 mm x 7.5 mm Package)
2
FDMF2011
Table 1. PIN FUNCTION DESCRIPTION
Pin
1, 29, 32, 34
2
Name
N/C
Function
No connect
VDD
Power supply input for low−side gate drive and bootstrap diode. Bypass this pin to VSS with a low
impedance capacitor.
3
4
HI
LI
High−side PWM input.
Low−side PWM input.
5, 10, 11, 22, 23,
33, 37
PGND
Power return for the power stage. Package header, pin 37 and PGND are internally fused (shorted).
6
7, 9
8
VSS
LG
Analog ground for driver IC analog circuits.
Low−side MOSFET gate.
LO
Low−side gate drive output.
12 − 21
24 − 28
30
SW
VIN
HG
PH
HB
HO
Switching node junction between high−side and low−side MOSFE
T
s
.
Power input for the power stage. Bypass this pin to PGND with low impedance capacitor.
High−side MOSFET gate.
31
High−side source connection (SW node) for the bootstrap capacitor.
Bootstrap supply for high−side driver. Bypass this pin to PH with low impedance capacitor.
High−side gate drive output.
35
36
3
FDMF2011
TYPICAL APPLICATION DIAGRAM
Figure 3. Half−Bridge DC Motor
Figure 4. Full−Bridge DC Motor
4
FDMF2011
TYPICAL APPLICATION DIAGRAM
C
BOOT1
D
BOOT1
R
BOOT1
VDD
VIN
HB
PH
VIN
SW
VDD
C
VIN1
C
VDD1
HI
LI
FDMF2011
HO
R
GH1
HG
LO
R
GL1
LG
VSS
PGND
C
BOOT2
D
BOOT2
R
BOOT2
VDD
VIN
HB
PH
VIN
SW
VDD
C
VIN2
C
VDD2
HI
LI
FDMF2011
MCU
M
HO
R
GH2
HG
LO
R
GL2
LG
VSS
PGND
C
BOOT3
D
BOOT3
R
BOOT3
VDD
VIN
HB
PH
VIN
SW
VDD
C
VDD3
C
VIN3
HI
LI
FDMF2011
HO
R
GH3
HG
LO
R
GL3
LG
VSS
PGND
Figure 5. 3−Phase DC Motor
5
FDMF2011
TYPICAL APPLICATION DIAGRAM
Figure 6. Buck Converter
Figure 7. Half−Bridge Converter
6
FDMF2011
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Referenced to VSS
Min
Max
Unit
V
V
Power Stage Supply Voltage
PH Voltage
−0.3
100
IN
V
PH
V
DD
V
HB
Referenced to VSS
Referenced to VSS
Referenced to VSS
Referenced to VSS
Referenced to PHASE
Referenced to VSS
Referenced to PHASE
Referenced to VSS
V
− 25
V +
0.3
HB
V
HB
Driver Supply Voltage
Bootstrap to VSS
−0.3
−0.3
−0.3
25
V
125
V
V
V
Gate Drive Input Signals
High Side Driver Output
Low Side Driver Output
High Side MOSFET Gate
Low Side MOSFET Gate
V
+ 0.3 V
V
LI, HI
DD
V
V
− 0.3 V
V
+ 0.3 V
+ 0.3 V
28
V
HO
PH
BOOT
V
− 0.3
V
V
LO
DD
V
−28
−28
−
V
HG
V
28
V
LG
Q
Junction
T
e
mperature
17
°
C/W
°
C/W
°
C
°
C
JA
−
15
T
−
150
J
T
STG
Storage
T
e
mperature
−40
150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Thermal
resistance rating is measured under board mounted and still air conditions.
2
Mounted on a multi−layer FR4 PCB with a dissipating copper surface on the top side of 49 cm
, 2 oz.
Table 3. RECOMMENDED OPERATING RANGES
Symbol
Parameter
Power Stage Supply Voltage
Driver Supply Voltage
SW or PHASE
Test Condition
Min
3
Max
80
Unit
V
V
IN
V
DD
10
20
V
V ,
V
SW PH
DC
−0.3
100
100
V
Repetitive Pulse (<20 ns, 10
m
J)
6 − V
V
DD
V
HB
Voltage on HB
Reference to PH
V
PH
+ 10
V +
20
PH
V
dV /dt
Voltage Slew Rate on SW
Operating
T
e
mperature
−
50
V/ns
°
C
SW
T
J
−40
125
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
8
FDMF2011
Table 4. ELECTRICAL CHARACTERISTICS
(V =
V =
15
V
, V
= V
= 0 V, V
= 50 V, T
= +25
°
C unless otherwise noted.)
DD
HB
SW
SS
IN
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
SUPP
L
Y
C
URRENTS
I
Power Stage Quiescent Current
Driver Quiescent Current
VDD Operating Current
LI = HI = 0 V
LI = HI = 0 V
−
−
−
−
−
−
−
−
1
m
A
m
A
INQ
I
I
77
180
0.6
4.3
120
0.6
4.8
DDQ
DDO
F
SW
F
SW
= 20 kHz
0.3
2.1
45
mA
mA
m
A
= 200 kHz
I
I
BOOT Quiescent Current
BOOT Operating Current
LI = HI = 0 V
HBQ
F
= 20 kHz
0.3
2.4
mA
mA
HBO
SW
SW
F
= 200 kHz
UNDER−VOLTAGE PROTECTION
V
V
UVLO Rising Threshold
UVLO Falling Threshold
UVLO Hysteresis
V
V
V
or V
−V rising
threshold
8.2
7.6
−
9.4
8.8
0.6
−
10.0
9.6
−
V
V
DDR, HBR
DD
DD
DD
HB
PH
V
V
or V
−V falling
threshold
HB PH
DD
F
,
H
BF
V
Hysterisis
V
DDH
t
POR Delay to Enable IC
UVLO rising to internal PWM enable
−
10
m
s
D_POR
CONTROL INPUTS (TTL: LI, HI)
V
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
Input Pull−Down Resistance
V
DD
= 10 V to 20 V
1.2
−
−
−
−
2.9
−
V
V
IL
V
IH
V
HYS
−
1.0
475
V
R
−
−
k
W
IN
PWM INPUT (HI, LI)
t
LI to LO Propagation Delays
LI
Low
”
HIGH
to LO
Low
”
HIGH
,
100
100
100
100
160
212
177
211
300
300
300
300
ns
ns
ns
ns
LPLH
V
IH
to 10% LG
t
LI
High
”
Low
to LO
High
”
Low
,
LPHL
V
IL
to 90% LG
t
t
HI to HO Propagation Delays
HI
Low
”
HIGH
to HO
Low
”
HIGH
,
HPLH
V
IH
to 10% HG−PH
HI
High
”
Low
to HO
High
”
Low
,
HPHL
V
IL
to 90% HG−PH
MT
Delay Matching, HS and LS Turn−on/off
−
−
−
50
−
ns
ns
t
Minimum Input Pulse Width that
Changes the Output
LI/HI Rising to Vth of Q1, Q2
= 0
W
60
PW
R
G
LI/HI Falling to Vth of Q1, Q2
−
100
−
ns
R
= 0
W
G
HIGH−SIDE DRIVER (HDRV) (VDD = VHB = 15 V)
I
Output Sourcing Peak Current
Output Sinking Peak Current
Rise Time
V
V
= 0 V
250
500
−
350
650
170
70
−
mA
mA
ns
SOURCE_HO
HO
I
= 15 V
−
SINK_HO
HO
t
GH = 10% to 90%, R
= 0
W
339
140
R_HG
GH
t
Fall Time
GH = 90% to 10%, R
= 0
W
−
ns
F_HG
GH
LOW−SIDE DRIVER (LDRV) (VDD = VHB = 15 V)
I
Output Sourcing Peak Current
Output Sinking Peak Current
Rise Time
V
V
= 0 V
250
500
−
350
650
171
71
−
mA
mA
ns
SOURCE_LO
LO
I
= 15 V
−
SINK_LO
LO
t
GL = 10% to 90%, R
= 0
W
342
142
R_LG
GL
t
Fall Time
GL = 90% to 10%, R
= 0
W
−
ns
F_LG
GL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9
FDMF2011
Table 5. MOSFET ELECTRICAL CHARACTERISTICS
(T =
+25
°
C unless otherwise noted.)
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
HIGH SIDE MOSFE
T
,
Q
1
BV
Drain−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−Source Leakage Current
Gate−Source Threshold Voltage
Drain –Source On−Resistance
T
o
tal Gate Charge
I
= 250
m
A, V
= 0 V
100
−
−
−
−
1
V
m
A
nA
V
DSS
DS
GS
I
V
V
V
V
V
= 80 V, V
= 0 V
GS
DSS
DS
DS
DS
GS
GS
I
= 0
V
, V
=
20 V
−
−
100
4
GSS
GS
V
GS(th)
= V
, I
= 250
m
A
2
3.1
7.7
25
GS DS
R
= 10 V, I
= 20 A
−
8.9
−
m
W
nC
nC
nC
nC
W
DS(ON)
DS
Q
= 0 V to 10
V
, V
=
5
0 V,
−
G
DD
I
= 20 A
DS
Q
GS
Q
GD
Gate−Source Charge
−
8.5
5.2
31.3
0.7
−
Gate−Drain “Miller” Charge
T
o
tal Output Charge
−
−
Q
−
−
OSS
R
Series Gate Resistance
−
−
G
Q1 DRAIN−SOURCE DIODE
V
Source to Drain Forward Voltage
V
V
− V
= 0
V
, I
= 2 A
−
−
−
−
−
−
0.7
0.8
59
1.2
1.3
95
V
SD
HG
PH
SD
− V
= 0
V
, I
= 20 A
HG
PH
SD
t
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
I =
20 A, di
/dt = 100 A/
m
s
F
ns
nC
ns
RR
F
Q
77
123
80
RR
RR
t
I =
20 A, di
/dt = 300 A/
m
s
F
50
F
Q
140
224
nC
RR
LOW SIDE MOSFE
T
,
Q
2
BV
Drain−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−Source Leakage Current
Gate−Source Threshold Voltage
Drain –Source On−Resistance
T
o
tal Gate Charge
I
= 250
m
A, V
= 0 V
100
−
−
−
−
1
V
m
A
nA
V
DSS
DS
GS
I
V
V
V
V
V
= 80 V, V
= 0 V
GS
DSS
DS
DS
DS
GS
GS
I
= 0
V
, V
=
20 V
−
−
100
4
GSS
GS
V
GS(th)
= V
, I
= 250
m
A
2
3.3
7.3
25
8.9
6
GS DS
R
= 10 V, I
= 20 A
−
8.9
33
−
m
W
nC
nC
nC
nC
W
DS(ON)
DS
Q
= 0 V to 10
V
, V
=
5
0 V,
−
G
DD
I
= 20 A
DS
Q
Q
Gate−Source Charge
−
GS
GD
Gate−Drain “Miller” Charge
T
o
tal Output Charge
−
−
Q
−
31.3
0.9
−
OSS
R
Series Gate Resistance
−
−
G
Q2 DRAIN−SOURCE DIODE
V
Source to Drain Forward Voltage
V
V
− V
= 0
V
, I
= 2 A
−
−
−
−
−
−
0.7
0.8
58
1.2
1.3
93
V
SD
HG
PH
SD
− V
= 0
V
, I
= 20 A
HG
PH
SD
t
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
I =
20 A, di
/dt = 100 A/
m
s
F
ns
nC
ns
RR
F
Q
86
137
77
RR
RR
t
I =
20 A, di
/dt = 300 A/
m
s
F
48
F
Q
146
234
nC
RR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS
(T =
25
°
C unless otherwise noted.)
J
95
90
85
80
75
70
65
60
55
50
45
100
90
80
70
60
50
40
30
20
10
0
V
V
V
= V
= 15 V
= 0 V
DD
HB
V
HB
V
SS
V
IH
= 15 V
= 0 V
SS
= V
= 0 V
IH
IL
= V
= 0 V
IL
0
5
10
15
20
−40 −20
0
20
40
60
80 100 120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 9. I
DDQ
vs. Supply Voltage (V
DD
)
Figure 10. I
DDQ
vs. Temp.
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
100
90
80
70
60
50
40
30
20
10
0
V
= 15 V
= 0 V
DD
V
V
V
= 15 V
= 0 V
DD
V
V
SS
SS
= V
= 0 V
IH
IL
= V
= 0 V
IH
IL
0
5
10
15
20
−40 −20
0
20
40
60
80 100 120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 11. I
HBQ
vs. Supply Voltage (V
DD
)
Figure 12. I
HBQ
vs. Temp.
300
275
250
225
200
175
150
125
100
75
300
275
250
225
200
175
150
125
100
V
= V
= 15 V
HB
= 0 V
= 0
W
V
V
R
= V
HB
= 0 V
= 0
W
DD
DD
V
SS
SS
R
G
G
t
HPLH
t
HPLH
t
LPLH
t
LPLH
50
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 13. Turn−On Propagation Delay vs.
Supply Voltage (V
DD
Figure 14. Turn−On Propagation Delay vs. Temp.
)
11
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS
(T =
25
°
C unless otherwise noted.)
J
300
300
275
250
225
200
175
150
125
100
V
V
R
= V
= 15 V
= 0 V
= 0
W
V
V
R
= V
HB
= 0 V
= 0
W
DD
HB
DD
275
250
225
200
175
150
125
SS
SS
G
G
t
HPHL
t
t
HPHL
LPHL
t
LPHL
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 15. Turn−Off Propagation Delay vs.
Supply Voltage (V
DD
Figure 16. Turn−Off Propagation Delay vs. Temp.
)
200
180
160
140
120
100
240
V
V
R
= V
= 15 V
= 0 V
= 0
W
DD
HB
SS
220
200
180
160
140
120
G
t
R_HG
t
R_LG
t
R_LG
t
R_HG
V
V
R
= V
HB
= 0 V
= 0
W
DD
SS
G
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 17. Turn−On Rising Time vs.
Figure 18. Turn−On Rising Time vs. Temp.
Supply Voltage (V
DD
)
200
180
160
140
120
100
80
120
V
V
R
= V
HB
= 0 V
= 0
W
115
110
105
100
95
90
85
80
75
70
65
60
55
DD
SS
G
t
F_HG
t
t
F_HG
F_LG
t
F_LG
60
V
V
R
= V
= 15 V
DD
HB
= 0 V
SS
40
= 0
W
G
20
50
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 19. Turn−Off Falling Time vs.
Supply Voltage (V
DD
Figure 20. Turn−Off Falling Time vs. Temp.
)
12
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS
(T =
25
°
C unless otherwise noted.)
J
500
480
460
440
420
400
380
360
340
320
300
280
260
240
220
200
180
440
420
400
380
V
DD
V
SS
V
HO
= V
= 0 V
= V
= 0 V
V
V
V
= V
= 15 V
= 0 V
= V
= 0 V
LO
HB
DD
SS
HO
HB
LO
I
360
SOURCE_LO
I
SOURCE_LO
I
340
320
300
280
260
SOURCE_HO
I
SOURCE_HO
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 21. Output Sourcing Current vs.
Figure 22. Output Sourcing Current vs. Temp.
Supply Voltage (V
DD
)
700
675
650
625
600
575
550
525
500
475
450
425
400
375
350
325
300
800
V
V
V
= V
= 15 V
= 0 V
DD
SS
LO
HB
750
700
650
600
550
500
450
400
= V
, V
= V
HB
DD
HO
I
SINK_HO
I
SINK_LO
I
SINK_HO
I
SINK_LO
V
DD
V
SS
V
LO
= V
HB
= 0 V
= V
, V
= V
HB
DD
HO
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 23. Output Sinking vs. Supply
Voltage (V
DD
Figure 24. Output Sinking Current vs. Temp.
)
600
575
550
525
500
475
450
425
400
375
350
325
300
600
550
500
450
400
350
300
250
V
V
V
V
= V
V
V
V
V
= V
= 15 V
HB
= V
= 0 V
PH
= V
= 5 V
IL
DD
HB
DD
= V
= 0 V
SS
PH
SS
= V
= 5 V
IH
IL
IH
= V
− V
(V −
V
)
LO
= V
− V
(V −
V
)
OH
HB
HO,
DD
OH
HB
HO,
DD
LO
I =
20 mA
L
I =
20 mA
L
High−Side
High−Side
Low−Side
Low−Side
10
12
14
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 25. High−Level Output Voltage Deviation
from the V
BH
(V
DD
) vs. Supply Voltage (V
DD
Figure 26. High−Level Output Voltage Deviation
from the V
BH
(V
DD
) vs. Temp.
)
13
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS
(T =
25
°
C unless otherwise noted.)
J
200
190
180
170
160
150
140
130
120
230
V
V
V
V
= V
V
V
V
V
= V
= 15 V
HB
= V
= 0 V
PH
DD
HB
DD
= V
= 0 V
SS
PH
SS
210
190
170
150
130
110
90
= V
= 0 V
= V
= 0 V
IH
IL
IH
IL
= V
− V
(V −
V
)
= V
− V
(V −
V
)
OL
HO
PH,
LO
SS
OL
HO
PH,
LO
SS
I =
20 mA
L
I =
20 mA
L
High−Side
High−Side
Low−Side
Low−Side
14
10
12
16
18
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 27. Low−Level Output Voltage Deviation
from the V
PH
(V
SS
) vs. Supply Voltage (V
DD
Figure 28. Low−Level Output Voltage Deviation
from the V
PH
(V
SS
) vs. Temp.
)
10
10
9.8
9.6
9.4
9.8
9.6
9.4
9.2
9
V
DDR
V
HBR
9.2
9
V
DDF
V
HBF
8.8
8.6
8.4
8.2
8
8.8
8.6
8.4
8.2
8
−40 −20
0
20
40
60
80 100
120
−40 −20
0
20
40
60
80 100
120
T
e
mperature (
°
C)
T
e
mperature (
°
C)
Figure 29. V
DD
UVLO Threshold Voltage vs. Temp.
Figure 30. V
HB
UVLO Threshold Voltage vs. Temp.
27
25
23
21
19
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
VIH_HI & VIH_LI
VIL_HI & VIL_LI
IN+
17
15
13
11
9
7
0.8
0.6
0.4
0.2
0
5
3
1
−1
IN−
0
5
10
15
20
−40 −20
0
20
40
60
80 100
120
Supply Voltage (V)
T
e
mperature (
°
C)
Figure 31. IN+ IN− vs. Supply Voltage (V
DD
)
Figure 32. Input Logic Threshold Voltage vs. Temp.
14
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS
(T =
25
°
C unless otherwise noted.)
J
30
25
20
15
10
5
30
V
= 80 V, V
= 10 V/16 V, V
= 40 V,
IN
DD
OUT
V
= 60 V, V
= 10 V/16 V, V
= 30 V,
IN
DD
OUT
Tj
≤
125
°
C
Tj
≤
125
°
C
25
20
15
10
5
80Vi40Vo10Vg
80Vi40Vo16Vg
60Vi30Vo10Vg
60Vi30Vo16Vg
0
0
20 40 60 80
100 120 140 160 180 200
, Switching Frequency (kHz)
20 40 60 80
100 120 140 160 180 200
, Switching Frequency (kHz)
F
SW
F
SW
Figure 33. Static SOA, V
IN
= 80 V
Figure 34. Static SOA, V
IN
= 60 V
8.6
8.4
8.2
8
12
10
8
V
V
= 80 V, V
= 10 V,
DD
IN
V
= 80 V, V
= 24 V,
IN
OUT
= 24 V, I
= 13 A
OUT
OUT
FSW = 100 kHz, I
= 13 A
OUT
7.8
7.6
7.4
7.2
7
6
4
2
0
0
20
40
60
80
100
120
10
12
14
16
18
20
Dead Time (ns)
V
GS
, Gate Voltage (V)
Figure 35. Module Power Loss vs. T
DEAD
Figure 36. Module Power Loss vs. V
GS
26
25
24
23
22
21
20
19
18
V
= 72 V, V
= 13 V,
DD
IN
T =
125
°
C, T
= 25
°
C, PF = 0.78
J
A
Sine−Triangle Comparison,
DM = 1
0
10
100
Carrier Frequency (kHz)
Figure 37. Output Current vs. Carrier or
Modulation Frequency
15
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q1 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
6
150
120
90
60
30
0
V
GS
= 5 V
V
GS
= 10 V
5
4
3
2
1
0
V
GS
= 6 V
V
GS
= 8 V
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
V
GS
= 8 V
V
GS
= 6 V
V
GS
= 10 V
V
GS
= 5 V
0
1
2
3
4
5
0
30
60
90
120
150
V
DS
, Drain to Source Voltage (V)
I ,
Drain Current (A)
D
Figure 38. On Region Characteristics
Figure 39. Normalized On−Resistance vs.
Drain Current and Gate Voltage
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
100
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
I
V
= 20 A
D
= 10 V
GS
80
60
40
20
0
I
D
= 20 A
T =
125
°
C
J
T =
25
°
C
J
−75 −50 −25
0
25 50 75
100 125 150
4
5
6
7
8
9
10
T , Junction
T
e
mperature (
°
C)
J
V
GS
, Gate to Source Voltage (V)
Figure 40. Normalized On Resistance vs.
Junction Temperature
Figure 41. On−Resistance vs. Gate to Source
Voltage
150
100
150
Pulse Duration = 80
m
s
V
GS
= 0 V
Duty Cycle = 0.5% Max
120
90
60
30
0
10
1
V
DS
= 5 V
T =
150
°
C
J
T =
25
°
C
T =
150
°
C
J
J
0.1
T =
25
°
C
J
T =
−55
°
C
J
0.01
0.001
T =
−55
°
C
J
3
4
5
6
7
8
9
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, Gate to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 42. Transfer Characteristics
Figure 43. Source to Drain Diode Forward
Voltage vs. Source Current
16
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q1 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
10000
10
8
I
D
= 20 A
C
C
iss
V
DD
= 25 V
1000
100
10
V
= 50 V
DD
oss
6
V
DD
= 75 V
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
1
0.1
0
1
10
, Drain to Source Voltage (V)
DS
100
0
5
10
15
20
25
30
Q ,
Gate Charge (nC)
g
V
Figure 44. Gate Charge Characteristics
Figure 45. Capacitance vs. Drain to Source
Voltage
1000
50
R
= 3.44
°
C/W
q
JC
40
30
20
10
0
10
m
s
100
10
1
V
GS
= 10 V
This area is
limited by R
100
m
s
DS(ON)
Single Pulse
1 ms
10 ms
100 ms/DC
T =
Max Rated
J
R
T
= 3.44
°
C/W Curve
bent to
= 25
°
C
q
JC
measurement data
C
0.1
0.1
25
50
75
100
125
150
1
10
100 600
T ,
Case
T
e
mperature (
°
C)
C
V
DS
, Drain to Source Voltage (V)
Figure 46. Maximum Continuous Drain
Current vs. Case Temperature
Figure 47. Forward Bias Safe Operating Area
100000
10000
1000
100
Single Pulse
R
T
= 3.44
°
C/W
= 25
°
C
q
JC
C
10
1
0
−5
1
0
−4
1
0
−3
1
0
−2
1
0
−1
1
0
0
t, Pulse Width (s)
Figure 48. Single Pulse Maximum Power Dissipation
17
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q1 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
2
1
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
Single Pulse
10
−4
0.001
10
−5
10
−3
t, Rectangular
Pulse Duration (s)
10
−2
10
−1
1
Figure 49. Junction−to−Case Transient Thermal Response Curve
18
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q2 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
10
150
120
90
60
30
0
V
GS
= 10 V
V
GS
= 5 V
8
6
4
2
0
V
GS
= 8 V
V
GS
= 6 V
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
V
V
= 6 V
= 5 V
GS
V
GS
= 8 V
GS
V
GS
= 10 V
0
1
2
3
4
5
0
30
60
90
120
150
V
DS
, Drain to Source Voltage (V)
I ,
Drain Current (A)
D
Figure 50. On Region Characteristics
Figure 51. Normalized On−Resistance vs.
Drain Current and Gate Voltage
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
100
Pulse Duration = 80
m
s
Duty Cycle = 0.5% Max
I
V
= 20 A
D
= 10 V
GS
80
60
40
20
0
I
D
= 20 A
T =
125
°
C
J
T =
25
°
C
J
−75 −50 −25
0
25 50 75
100 125 150
4
5
6
7
8
9
10
T , Junction
T
e
mperature (
°
C)
J
V
GS
, Gate to Source Voltage (V)
Figure 52. Normalized On Resistance vs.
Junction Temperature
Figure 53. On−Resistance vs. Gate to Source
Voltage
150
100
150
Pulse Duration = 80
m
s
V
GS
= 0 V
Duty Cycle = 0.5% Max
120
90
60
30
0
10
1
V
DS
= 5 V
T =
150
°
C
J
T =
150
°
C
T =
25
°
C
J
J
0.1
T =
25
°
C
J
T =
−55
°
C
J
0.01
0.001
T =
−55
°
C
J
3
4
5
6
7
8
9
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, Gate to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 54. Transfer Characteristics
Figure 55. Source to Drain Diode Forward
Voltage vs. Source Current
19
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q2 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
10000
10
8
I
D
= 20 A
C
C
iss
V
DD
= 25 V
1000
100
10
V
= 50 V
DD
oss
6
V
DD
= 75 V
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
1
0.1
0
1
10
100
0
5
10
15
20
25
30
Q ,
Gate Charge (nC)
g
V
DS
, Drain to Source Voltage (V)
Figure 56. Gate Charge Characteristics
Figure 57. Capacitance vs. Drain to Source
Voltage
50
500
R
= 3.57
°
C/W
q
JC
40
30
20
10
0
10
m
s
100
10
1
V
GS
= 10 V
This area is
limited by R
100
m
s
DS(ON)
Single Pulse
1 ms
10 ms
100 ms/DC
T =
Max Rated
J
R
T
= 3.57
°
C/W Curve
bent to
= 25
°
C
q
JC
measurement data
C
0.1
0.1
25
50
75
100
125
150
1
10
100 600
T ,
Case
T
e
mperature (
°
C)
C
V
DS
, Drain to Source Voltage (V)
Figure 58. Maximum Continuous Drain
Current vs. Case Temperature
Figure 59. Forward Bias Safe Operating Area
100000
10000
1000
100
Single Pulse
R
T
= 3.57
°
C/W
= 25
°
C
q
JC
C
10
1
0
−5
1
0
−4
1
0
−3
1
0
−2
1
0
−1
1
t, Pulse Width (s)
Figure 60. Single Pulse Maximum Power Dissipation
20
FDMF2011
TYPICAL PERFORMANCE CHARACTERISTICS (Q2 N−Channel)
(T =
25
°
C unless otherwise noted.)
J
2
1
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
Single Pulse
10
−4
0.001
10
−5
10
−3
t, Rectangular
Pulse Duration (s)
10
−2
10
−1
1
Figure 61. Junction−to−Case Transient Thermal Response Curve
21
FDMF2011
FUNCTIONAL DESCRIPTION
PWM Input Stage
The FDMF2011 is a non−inverting 100 V half−bridge
Smart Power Stage (SPS) module. The module packages a
driver IC die along with pair of equally sized (matched
The FDMF2011 incorporates a PWM input gate drive
design, where the low side drive output (LO) and high side
drive output (HO) are controlled through independent PWM
inputs (LI and HI, respectively).
R )
100 V POWERTRENCH N−Channel MOSFETs
DS(ON)
The module (driver IC) can be used with TTL compatible
input signals. The input signals can also be driven with
voltage levels that are lower than the VDD supply level. The
VDD supply level does NOT affect the input threshold
levels (VIH and VIL).
The FDMF2011 module provides separate power input
pins; the power stage input (VIN) and the gate driver input
(VDD). The power stage input (VIN) accepts a wide
operating from 3 V to 80
V
,
w
hile the gate driver input
(VDD) requires 10 V to 20
V
.
T
he module accepts TTL
compatible inputs (HI/LI) along with anti−cross conduction
circuitry to protect against over−lapping PWM (HI/LI)
pulses. The module (driver IC) also implements UVLO
circuitry in both the VDD−VSS and BOOT−PH power
domains.
Power−Up and UVLO Operation
UVLO circuits are implemented in both the VDD−VSS
and HB−PH power domains. During power−up, the
VDD−VSS UVLO circuit forces HO and LO low until the
VDD supply voltage exceeds the UVLO rising threshold
(9.4 V typ.). The module (driver IC) will begin responding
to PWM pulses once VDD exceeds the UVLO threshold.
The UVLO circuit does contain hysteresis (~0.6 V) to
prevent noise from interfering with normal operation.
An additional UVLO circuit is implemented on the HB−PH
pins which will hold HO low until HB−PH > 9.4 V (typ.).
The HB−PH UVLO also incorporates hysteresis (~0.6 V).
Figure 63. PWM Threshold Definitions
•
V =
PWM trip level to flip state from LOW to HIGH.
•
V =
PWM trip level to flip state from HIGH to LOW.
IH
IL
Table 6. UVLO TRUTH TABLE
Driver Output Stage
VDD UVLO
BOOT UVLO
Driver State
The driver IC output stage is designed to drive a pair of
N−channel MOSFETs. The driver outputs (LO, HO) are
non−inverting and will follow the PWM input commands
(LI, HI respectively). The LO and HO outputs are capable
of sinking and sourcing up to 0.65/0.35
A peak current
respectively.
0
1
1
X
0
1
Disabled (GH, GL = 0)
GL follows PWM , GH = 0)
Enabled (GH/GL follow PWM)
The driver output stage is also capable of providing a rail
(VDD) to rail (VSS) output voltage level when driving the
Power MOSFETs. Depending on the end application, the
output voltage level can be set to aide in optimizing
MOSFET and driver IC power losses. The driver output
voltage level can also be used to help adjust SW node edge
rates.
Figure 62. Min/Max UVLO Thresholds
22
FDMF2011
APPLICATION INFORMATION
The FDMF2011 is designed as a non−inverting power
stage, where the Power MOSFET response (SW node) is
designed to follow to HI/LI commands. The device is
well−suited to be used in a wide variety of applications, such
as: Half and Full−Bridge DC−DC converters, Active Clamp
Forward converters, rectifier circuits, and motor drive
power stages. However, various applications and topologies
can place unique stresses on the module. There are a few
basic power−stage requirements needed to ensure proper
operation.
Module Power Dissipation
As previously mentioned, the FDMF2011 is a multi−chip
module (MCM). The module consists of three die (HS
MOSFET, LS MOSFET and driver IC). Each die dissipates
heat in normal operation resulting from power loss. The
power MOSFETs can generate power loss from conduction
and switching losses while the driver IC dissipated loss from
bias, boot diode conduction and from the driver output stage
sinking and sourcing power MOSFET gate currents and
operating frequency. The amount of heat dissipated by any
die is largely dependent on the operating conditions. The
close physical placement of the three die inside of the
package translates into strong thermal coupling between die.
Ideally, a thermal camera should be used to monitor the
FDMF2011 during the engineering development phase.
This can help ensure the module operates within the absolute
maximum ratings specified in this datasheet.
Figure 65. H−bridge Motor Drive
FDMF2011 Power Dissipation
The maximum motor drive current can be obtained from
estimating total power dissipation of motor driver. There are
a number of factors which limit actual current level such as
motor ratting, driver IC, PCB construction, ambient
temperature and given application. All of power dissipation
components must be considered to get reliable operation at
the specific application. There is obvious power dissipations
listed below in single H−bridge motor application.
•
Conduction loss – Generally biggest power loss which is
dissipated due to the R
and its temperature
DS(ON)
coefficient must be considered in the calculation
Operating Modes
2
P
COND
+
(R
DS(ON)
*
HS_temp
)
R
DS(ON)
*
LS_temp
)
@
I
OUT
The FDMF2011 can reliably operate while driving
various load impedances. However, the relatively large
number of applications can result in the module operating in
various modes. Common applications such as switching
power converters and motor drives can place the FDMF2011
into different operating modes. The various operating
modes will change the response of the MOSFET voltage and
current stresses and power losses as well as the gate driver
dead time response. A few operating modes are
listed
below.
(eq. 1)
•
Switching losses − Rising and falling time by parasitic
inductance can be measured in the application, listed
below assumed zero inductance.
Switching OFF loss
V
IN
@
I
DS(OFF)
@
t
OFF
+
ǒ
Ǔ
P
SW(OFF)
@
F
SW
(eq. 2)
2
where:
t
OFF
+
(Q
GS2
)
Q
GD
)
ń
i
G(OFF)
;
H−bridge Motor Drive
In this operating mode, it allows bi−directional current
flow through motor by enabling diagonal MOSFETs to
make current flow in one or the other direction. Inductor
current will not tolerate abrupt changes either when charged
or discharged and alternate path is required to protect
switches during dead−time. The path can be made either
MOSFET body−diode conducting as soon as switches are
disabled or enabling opposite high−side or low−side switch
to carry the recirculation current while avoiding
shoot−through. Utilizing MOSFET channel is often much
more efficient way to handle the decaying current due to
lower conduction power loss than body−diode forward drop
loss.
i
G(OFF)
+
V
PLATEAU
ń
(R
GH
)
R
DRV_OFF
)
Switching ON loss
V
IN
@
I
DS(ON)
@
t
ON
Qoss
@
V
IN
+
ǒ
Ǔ
P
SW(ON)
)
@
F
SW
(eq. 3)
2
2
where:
t
ON
+
(Q
GS2
)
Q
GD
)
ń
i
G(ON)
;
i
G(ON)
+
V
PLATEAU
ń
(R
G
)
R
DRV_ON
)
Qoss
+
Output Charge
•
Gate drive loss
P
GATE
+
Q
G
@
V
DRV
@
F
SW
(eq. 4)
24
FDMF2011
During this operating mode, the HS MOSFET (Q1) will
•
Quiescent current power loss – Current is still drawn from
undergo hard−switched inductive turn−on and turn−off
events, while LS MOSFET (Q2) will undergo soft switching
and body diode recovery. Hard−switching often results in
the VDD and HB pins for internal and level shifting
circuitry without load (R
= Open). Power loss by
G
quiescent current is
large switching spikes on Q1 and Q2 V
as well as PH to
DS
P
Quiescent
+
V
DD
@
I
DDQ
)
V
HB
@
I
HBQ
(eq. 5)
VSS and BOOT to VSS pins.
Peak switching spikes are
often positively correlated to load current.
•
Supply current power loss (R
= 0
W
) is
G
P
supply
+
V
DD
@
I
DDO
)
V
HB
@
I
HBO
Continuous Current Flowing into SW Node
(eq. 6)
Continuous current flowing into the module SW node is
typical of a heavily loaded switched−mode power stage that
is operating in a synchronous boost converter topology.
Continuous inductor current flowing in to the module SW
node is typical operation of a synchronous boost converter,
•
Total power loss in the FDMF2011 is equal to the power
dissipation caused by gate driver and Power MOSFETs,
P
total
+
P
Cond
)
P
SW
)
P
Gate
)
P
supply
(eq. 7)
Once the designer estimates power dissipation in the gate
driver and MOSFETs, junction temperature can be
calculated using thermal resistance (
Q
) and ambient
JA
temperature as followings and also can calculate maximum
allowable motor current:
T
j
+
T
A
)
(
Q
JA
@
P
total
)
(eq. 8)
Continuous Current Flowing Out of SW Node
Continuous current flowing out of the module SW node
is typical of a heavily loaded switched−mode power stage
that is operating in a synchronous buck converter topology.
In this mode, the power stage is supplying current from VIN
a synchronous buck convert operating in CCM with positive
inductor current.
Figure 67. Synchronous Boost Converter
Operating in CCM
From a module perspective, the main difference here
versus the previous (buck) operating mode is that this
situation will cause the LS FET (Q2) to act as the control
MOSFET and hard switch while the HS FET (Q1) acts as a
synchronous rectifier and undergoes soft switching with
body diode recovery. This type of operation can drastically
change power losses dissipated in Q1 and Q2 versus buck
operating mode.
dV
DS
/dt Control Using External Gate Resistors
The FDMF2011 also provides module pins for placing
external gate resistors. The module provides pins for the HO
and LO signals (driver output signals) and the HG and LG
(Power MOSFET gate pins). Resistors can be placed in
series with the MOSFET gate to control the SW node edge
rates.
Figure 66. Synchronous Buck Operating in CCM
with Positive Inductor Current
25
FDMF2011
Independently controlling MOSFET (slower) turn−on
Typically, a C
x dV
/dt “shoot−through” condition
GD DS
and (faster) turn−off slew rates can also be accomplished by
arises from capacitive feedback current flowing through
C into
C inducing
a gate−bounce−induced channel
GD
GS
turn−on of the MOSFET. Holding the gate below threshold
can become challenging because the high−frequency
capacitive displacement current from C
(due to dV
/dt)
GD
DS
couples back to circuit ground through the gate electrode.
Ld_LS
C
GD
R _LS
DRIVE
L
L
G_brd G_pack
R
G
C
GS
Q2
Z
~ R +
w
L
Gate_Drv
Ls_LS
Z
~ 1/
w
C
MOS_Gate
Figure 69. C
GD
x dV
DS
/dt Current Flow
The gate−to−ground impedance is the parallel
combination of the gate drive (Z
) and the MOSFET
Figure 68. Gate Drive Resistor−diode Circuit
C
GD
x dV
DS
/dt Turn−on
G_DRV
gate−to−source (Z
) paths. As dV
/dt increases,
MOS_Gate
DS
the more favorable path for displacement current is through
C
GD
x dV
/dt turn−on is a false (unwanted) turn−on
DS
the capacitive gate−source (C
) path versus the highly
GS
event that often creates a brief and uncontrolled shoot
through current between the HS (Q1) and LS (Q2)
MOSFETs.
inductive and resistive gate drive loop. So impedence
through gate driver should be minimized. The severity of the
shoot through current is difficult to predict.
ORDERING INFORMATION
Current Rating
(A)
Input Voltage
Frequency Max
†
(V)
(kHz)
Part Number
Device Marking
Package Type
Shipping
FDMF2011
FDMF2011
20
100
200
PQFN36 6X7.5, 0.5P
3000 /
T
a
pe & Reel
†For Information On
T
a
pe And Reel Specifications, Including Part Orientation And
T
a
pe Sizes, Please Refer
T
o
O
ur
T
a
pe And Reel Packaging
Specifications Brochure, Brd8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “
onsemi
” or its affiliates and/or subsidiaries in the United
States and/or other countries.
26
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN36 6X7.5, 0.5P
CASE 483BB
ISSUE A
DATE 07 JUN 2021
(k4)
D2
D3
0.10
0.05
C
C
A B
b1
2X
e
23X
e/2
b
27X
e1
2X
(z)
2X
27 28 29 30 31 32 33 34
35 36
(z2)
(k1)
L
18X
1
2
26
(2X)
e2
3
4
37
E3
25
E2
5
6
7
E6
(7X)
C.L.
24
23
8
(k2)
(k3)
e3
E5
9
L5
10
11
E4
22
(k)
L1
L4
21
141
5
1
1
3
6
1
7
112
8
1920
C.L.
D4
(z1)
D5
7X
D5
SCALE: 2:1
SEE DETAIL ”A”
e4
0.10
0.08
C
A1
A
FRONT VIEW
C
C
(A3)
0.10
C
B
A
D
2X
C.L.
SEATING
PLANE
36
27
SCALE: 2:1
1
26
PIN#1
INDICATOR
E
C.L.
11
22
0.10
C
12
21
2X
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13678G
PQFN36 6X7.5, 0.5P
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PQFN36 6X7.5, 0.5P
CASE 483BB
ISSUE A
DATE 07 JUN 202
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions
are uncontrolled
except when stamped
“CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13678G
PQFN36 6X7.5, 0.5P
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
©
Semiconductor Components Industries, LLC, 2019
onsemi
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