onsemi-FDMF5821

Part #	onsemi-FDMF5821
Download	onsemi-FDMF5821

Is Now Part of

To learn more about ON Semiconductor, please visit our website at

www.onsemi.com

Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers

will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor

product management systems do not have the ability to manage part nomenclature that utilizes an underscore

(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain

device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated

device numbers. The most

current and up-to-date ordering information can be found at

www.onsemi.com

. Please

email any questions regarding the system integration to

Fairchild_questions@onsemi.com

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number

of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right

to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON

Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON

Semiconductor data sheets and/or speciﬁcations can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s

technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA

Class 3 medical devices or medical devices with a same or similar classiﬁcation in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended

or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its ofﬁcers, employees, subsidiaries, afﬁliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out

of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor

is an Equal Opportunity/Afﬁrmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

October 2016

FDMF5821

–

Smart Power Stage (SPS) Module

with Integrated Temperature Monitor

Features

Description

The SPS family is ON

’

s next-generation, fully optimized,

ultra-compact, integrated MOSFET plus driver power

stage solution for high-current, high-frequency,

synchronous buck, DC-DC applications. The FDMF5821

integrates a driver IC with a bootstrap Schottky diode,

two power MOSFETs, and a thermal monitor into a

thermally enhanced, ultra-compact, 5

mm x 5

package.

Ultra-Compact 5 mm x 5 mm PQFN Copper-Clip

Package with Flip Chip Low-Side MOSFET

High Current Handling: 60 A

3-State 5 V PWM Input Gate Driver

Dynamic Resistance Mode for Low-Side Drive

(LDRV) Slows Low-Side MOSFET during Negative

Inductor Current Switching

With an integrated approach, the SPS switching power

stage is optimized for driver and MOSFET dynamic

performance, minimized system inductance, and power

MOSFET R

DS(ON)

. The SPS family uses Fairchild’s high-

performance PowerTrench

MOSFET technology,

which reduces switch ringing, eliminating the need for a

snubber circuit in most buck converter applications.

Auto DCM (Low-Side Gate Turn Off) Using

ZCD# Input

Thermal Monitor for Module Temperature Reporting

Programmable Thermal Shutdown (P_THDN)

HS-Short Detect Fault# / Shutdown

A driver IC with reduced dead times and propagation

delays further enhances the performance. A thermal

monitor function warns of a potential over-temperature

situation. A programmable thermal shutdown function

turns off the driver if an over-temperature condition

occurs. The FDMF5821 incorporates an Auto-DCM

Mode (ZCD#) for improved light-load efficiency. The

FDMF5821 also provides a 3-state 5 V PWM input for

compatibility with a wide range of PWM controllers.

Dual Mode Enable / Fault# Pin

Internal Pull-Up and Pull-Down for ZCD# and

EN Inputs, respectively

ON’s

PowerTrench

MOSFETs for Clean Voltage

Waveforms and Reduced Ringing

ON’s

SyncFE

T™

Technology (Integrated Schottky

Diode) in Low-Side MOSFET

Integrated Bootstrap Schottky Diode

Applications

Optimized / Extremely Short Dead-Times

Under-Voltage Lockout (UVLO) on VCC

Optimized for Switching Frequencies up to 1.5 MHz

PWM Minimum Controllable On-Time: 30 ns

Low Shutdown Current: < 3 µA

Servers and Workstations, V-Core and Non-V-Core

DC-DC Converters

Desktop and All-in-One Computers, V-Core and

Non-V-Core DC-DC Converters

High-Performance Gaming Motherboards

Optimized FET Pair for Highest Efficiency:

10 ~ 15% Duty Cycle

High-Current DC-DC Point-of-Load Converters

Networking and Telecom Microprocessor Voltage

Regulators

Operating Junction Temperature Range:

-40°C to +125°C

Small Form-Factor Voltage Regulator Modules

’

s Green Packaging and RoHS Compliance

Ordering Information

Part Number

Current Rating

Package

31-Lead, Clip Bond PQFN SPS, 5.0 mm x 5.0 mm Package

Top Mark

FDMF5821

60 A

5821

www.onsemi.com

FDMF5821 • Rev.

1.0

Application Diagram

VCC

VIN

VCC

PVCC

VCC

VIN

EN/FAULT#

PWM

BOOT

PHASE

PWM Input

BOOT

FDMF5821

OFF

ZCD#

OUT

TMON

OUT

TMON

AGND

PGND

OUT

Figure 1.

Typical Application Diagram

Functional Block Diagram

EN/

PVCC

FAULT#

BOOT

VIN

VCC

TMON

THERMAL

MONITOR

TMON

←

0.8V/2.0V

1.5V

FAULT

LATCH

FAULT

PHASE

VCC

LEVEL

SHIFT

EN/UVLO

HDRV

POR

PVCC

PWM CONTROL

LOGIC

PWM

PWM INPUT

LDRV1

PVCC

POR

VCC

LDRV2

10uA

↓

ZCD/CCM/DCM

LOGIC

ZCD#

0.8V/2.0V

AGND

PGND

Figure 2.

Functional Block Diagram

www.onsemi.com

FDMF5821 • Rev.

1.0

Pin Configuration

EN/

FAULT#

VIN

TMON

PVCC

PGND

AGND

PGND

Figure 3.

Pin Configuration – Top View and Transparent View

Pin Definitions

Pin #

Name

Description

PWM

ZCD#

VCC

PWM input to the gate driver IC

Enable input for the ZCD (Auto DCM) comparator

Power supply input for all analog control functions; this is the

“

quiet

”

4, 32

AGND

Analog ground for analog portions of the IC and for substrate, internally tied to PGND

Supply for the high-side MOSFET gate driver. A capacitor from BOOT to PHASE supplies

the charge to turn on the N-channel high-side MOSFET

BOOT

PHASE

VIN

No connect

Return connection for the boot capacitor, internally tied to SW node

Power input for the power stage

8~11

12~15, 28

PGND

Power return for the power stage

Switching node junction between high-side and low-side MOSFETs; also input to the gate

driver SW node comparator and input into the ZCD comparator

16~26

27, 33

Gate Low, Low-side MOSFET gate monitor

Power supply input for LS

(1)

gate driver and boot diode

PVCC

TMON

Temperature monitoring & reporting / programmable thermal shutdown pin

Dual-functionality: enable input to the gate driver IC; FAULT# – internal pull-down

physically pulls this pin LOW upon detection of fault condition (HS

(2)

MOSFET short or

TMON signal exceeding 1.5 V)

EN /

FAULT#

Notes:

1. LS

= Low Side.

2. HS

= High Side.

www.onsemi.com

FDMF5821 • Rev.

1.0

Absolute Maximum Ratings

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only. T

= T

= 25°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

Drive Voltage

Referenced to AGND

-0.3

-3.0

-0.3

-7.0

-0.3

-7.0

-0.3

-5.0

-0.3

6.0

Referenced to AGND

EN/FAULT#

Output Enable / Disable

Referenced to AGND

6.0

PWM

ZCD#

PWM Signal Input

ZCD Mode Input

Referenced to AGND

6.0

Referenced to AGND

6.0

Referenced to AGND (DC only)

Referenced to AGND, AC<20 nS

Referenced to AGND

6.0

Low Gate Manufacturing Test Pin

6.0

TMON

Thermal Monitor

Power Input

6.0

Referenced to PGND, AGND

Referenced to PGND, AGND (DC Only)

Referenced to PGND, AC < 20 ns

Referenced to PGND, AGND (DC Only)

Referenced to PGND, AC < 20 ns

Referenced to AGND (DC Only)

Referenced to AGND, AC < 20 ns

Referenced to PVCC

25.0

30.0

25.0

30.0

35.0

6.0

PHASE

Switch Node Input

Bootstrap Supply

BOOT

BOOT-PHASE

Boot to PHASE Voltage

= 300 kHz, V

=12 V, V

OUT

=1.8 V

= 1 MHz, V

=12 V, V

OUT

=1.8 V

(3)

O(AV)

Output Current

FAULT

J-A

J-PCB

EN / FAULT# Sink Current

-0.1

-40

7.0

°C/W

°C

Junction-to-Ambient Thermal Resistance

Junction-to-PCB Thermal Resistance (under ON

’

s SPS Thermal Board)

Ambient Temperature Range

12.4

1.8

+125

+150

Maximum Junction Temperature

°C

STG

Storage Temperature Range

-55

°C

Human Body Model,

ANSI/ESDA/JEDEC

3000

2500

Electrostatic Discharge

JS-001-2012

ESD

Protection

Charged Device Model, JESD22-C101

Note:

3. I

O(AV)

is rated with testing ON

’s

SPS evaluation board at T

= 25°C with natural convection cooling. This rating is

limited by the peak SPS temperature, T

= 150°C, and varies depending on operating conditions and PCB layout.

This rating may be changed with different application settings

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

Operating Conditions are specified to ensure optimal performance to the datasheet specifications. On does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Control Circuit Supply Voltage

Min.

Typ.

Max.

Unit

4.5

(4)

5.0

5.5

16.0

(5)

Gate Drive Circuit Supply Voltage

Output Stage Supply Voltage

Operating Junction Temperature

12.0

-40

+125

°C

Notes:

4. 3.0

V V

is possible according to the application condition.

5. Operating

at high V

can create excessive AC voltage overshoots on the SW-to-GND and BOOT-to-GND nodes during

MOSFET switching transient. For reliable SPS operation, SW to GND and BOOT to GND must remain at or below the Absolute

Maximum Ratings in the table above.

www.onsemi.com

FDMF5821 • Rev.

1.0

Electrical Characteristics

Typical value is under V

=12 V, V

=PV

=5 V and T

=+ 25°C unless otherwise noted. Minimum / Maximum

values are under V

=12 V, V

=PV

=5 V ± 10% and T

=-40 ~ 125°C unless otherwise noted.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

Basic Operation

VCC

+ I

PVCC

, EN=HIGH, PWM=LOW or

HIGH or Float (Non-Switching)

Quiescent Current

SHDN

Shutdown Current

UVLO Threshold

SHDN

VCC

+ I

PVCC

, EN=GND

Rising

µA

UVLO

3.5

2.0

3.8

0.4

4.1

UVLO_HYST

UVLO Hysteresis

D_POR

EN Input

IH_EN

POR Delay to Enable IC

UVLO Rising to Internal PWM Enable

µs

High-Level Input Voltage

Low-Level Input Voltage

Pull-Down Resistance

IL_EN

0.8

PLD_EN

250

PWM=GND, EN Going LOW to GL Going

LOW

PD_ENL

PD_ENH

EN LOW Propagation Delay

EN HIGH Propagation Delay

µs

PWM=GND, EN Going HIGH to GL

Going HIGH

ZCD# Input

IH_ZCD#

High-Level Input Voltage

Low-Level Input Voltage

Pull-Up Current

2.0

IL_ZCD#

0.8

PLU_ZCD#

µA

PWM=GND, ZCD# Going LOW to GL

Going LOW (assume I

<=0)

PD_ZLGLL

PD_ZHGLH

ZCD# LOW Propagation Delay

ZCD# HIGH Propagation Delay

PWM=GND, ZCD# Going HIGH to GL

Going HIGH

PWM Input

UP_PWM

Pull-Up Impedance

kΩ

DN_PWM

IH_PWM

Pull-Down Impedance

PWM High Level Voltage

Typical Values: T

=25°C,

=PV

=5 V,

Min. / Max. Values:

=-40°C to 125°C,

=PV

=5 V ±10%

3.8

1.2

TRI_Window

3-State Window

3.1

0.8

130

2.9

IL_PWM

PWM Low Level Voltage

D_HOLD-OFF

3-State Shut-Off Time

HIZ_PWM

Minimum Controllable On-Time

PWM Minimum Controllable On-

Minimum PWM HIGH Pulse Required for

3-State Open Voltage

2.1

2.5

MIN_PWM_ON

Time

SW Node to Switch from GND to VIN

Forced Minimum GL HIGH Time

Minimum GL HIGH Time when LOW

BOOT-SW

detected and PWM

LOW=<100 ns

MIN_GL_HIGH

Forced Minimum GL HIGH

100

PWM Propagation Delays & Dead Times (V

=12 V, V

=PV

=5 V, f

=1 MHz, I

OUT

=20 A, T

=25

°C

)

PWM Going HIGH to GL Going LOW,

IH_PWM

to 90% GL

PWM Going LOW to GH

(6)

Going LOW,

IL_PWM

to 90% GH

PD_PHGLL

PD_PLGHL

PWM HIGH Propagation Delay

PWM LOW Propagation Delay

PWM Going HIGH to GH Going HIGH,

IH_PWM

to 10% GH (ZCD#=LOW, I

=0,

Assumes DCM)

PWM HIGH Propagation Delay

(ZCD# Held LOW)

PD_PHGHH

Continued

on the following page…

www.onsemi.com

FDMF5821 • Rev.

1.0

Electrical Characteristics

Typical value is under V

=12 V, V

=PV

=5 V and T

=+ 25°C unless otherwise noted. Minimum / Maximum

values are under V

=12 V, V

=PV

=5 V ± 10% and T

=-40 ~ 125°C unless otherwise noted.

Symbol

Parameter

Condition

Min. Typ. Max. Unit

GL Going LOW to GH Going HIGH, 10%

GL to 10% GH, PWM Transition LOW to

HIGH

–

See

Figure 27

D_DEADON

LS Off to HS On Dead Time

GH Going LOW to GL Going HIGH, 10%

GH to 10% GL, PWM Transition HIGH to

LOW

–

See

Figure 27

D_DEADOFF

HS Off to LS On Dead Time

R_GH_20A

F_GH_20A

R_GL_20A

F_GL_20A

GH Rise Time under 20 A I

OUT

GH Fall Time under 20 A I

OUT

GL Rise Time under 20 A I

OUT

GL Fall Time under 20 A I

OUT

10% GH to 90% GH, I

OUT

=20 A

90% GH to 10% GH, I

OUT

=20 A

10% GL to 90% GL, I

OUT

=20 A

90% GL to 10% GL, I

OUT

=20 A

Exiting 3-State Propagation

Delay

PWM (from 3-State) Going HIGH to GH

Going HIGH, V

IH_PWM

to 10% GH

PD_TSGHH

PD_TSGLH

Exiting 3-State Propagation

Delay

PWM (from 3-State) Going LOW to GL

Going HIGH, V

IL_PWM

to 10% GL

High-Side Driver (HDRV, V

= PV

= 5 V)

SOURCE_GH

Output Impedance, Sourcing

Source Current=100 mA

0.68

0.9

SINK_GH

R_GH

Output Impedance, Sinking

GH Rise Time

Sink Current=100 mA

10% GH to 90% GH, C

LOAD

=1.3 nF

90% GH to 10% GH, C

LOAD

=1.3 nF

F_GH

GH Fall Time

Weak Low-Side Driver (LDRV2 Only under CCM2 Mode Operation, V

= PV

= 5 V)

SOURCE_GL

Output Impedance, Sourcing

Source Current=100 mA

GL=2.5 V

0.82

SOURCE_GL

SINK_GL

Output Sourcing Peak Current

Output Impedance, Sinking

Output Sinking Peak Current

Sink Current=100 mA

GL=2.5 V

0.86

Low-Side Driver (Paralleled LDRV1 + LDRV2 under CCM1 Mode Operation, V

= PV

= 5 V)

SOURCE_GL

Output Impedance, Sourcing

Source Current=100 mA

GL=2.5 V

0.47

SOURCE_GL

SINK_GL

R_GL

Output Sourcing Peak Current

Output Impedance, Sinking

Output Sinking Peak Current

GL Rise Time

Sink Current=100 mA

GL=2.5 V

0.29

10% GL to 90% GL, C

LOAD

=7.0 nF

90% GL to 10% GL, C

LOAD

=7.0 nF

F_GL

GL Fall Time

Thermal Monitor Current

TMON_25

Thermal Monitor Current

=25°C

39.3

1.39

40.2

41.0

µA

TMON_150

=150°C

=25 ~ 150°C

TMON_SLOPE

Thermal Monitor Current Slope

Programmable Thermal Shutdown

ACT_PTHDN

Activation Voltage

0.144

µA/°C

=125 ~ 150°C, R

TMON

=25

kΩ

=25°C

PLD_EN-PTHDN

=5 mA

1.62

PLD_EN-PTHDN

Pull-Down Resistance

Catastrophic Fault (SW Monitor)

SW_MON

SW Monitor Reference Voltage

1.3

Propagation Delay to Pull EN /

FAULT# Signal = LOW

D_FAULT

Boot Diode

Forward-Voltage Drop

Breakdown Voltage

=10 mA

=1 mA

0.4

Note:

6. GH

= Gate High, internal gate pin of the high-side MOSFET.

www.onsemi.com

FDMF5821 • Rev.

1.0

Typical Performance Characteristics

Test Conditions: V

=12 V,

=PV

=5 V,

OUT

=1.8 V,

OUT

=250 nH,

=25°C and natural convection cooling,

unless otherwise noted.

12Vin, 300kHz

12Vin, 500kHz

12Vin, 800kHz

12Vin, 1000kHz

& V

= 5V, V

OUT

= 1.8V

= 300kHz

= 1000kHz

= 12V, PV

& V

= 5V, V

OUT

= 1.8V

10 15 20 25 30 35 40 45 50 55 60

100

125

150

Module Output Current, I

OUT

[A]

PCB Temperature, T

PCB

[

Figure 4.

Safe Operating Area

Figure 5.

Power Loss vs. Output Current

1.5

1.12

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

& V

VCC

= 5V, V

OUT

= 1.8V, F

= 500kHz, I

OUT

= 30A

= 12V, PV

& V

= 5V, V

OUT

= 1.8V, I

OUT

= 30A

1.4

1.3

1.2

1.1

1.0

0.9

0.8

200

300

400

500

600

700

800

900 1000

Module Switching Frequenc

[kHz]

Module Input

ltage, V

[V]

Figure 6.

1.12

Power Loss vs. Switching Frequency

Figure 7.

Power Loss vs. Input Voltage

1.5

1.4

1.3

1.2

1.1

1.0

0.9

= 12V, V

OUT

= 1.8V, F

= 500kHz, I

OUT

= 30A

= 12V, PV

& V

VCC

= 5V, F

= 500kHz, I

OUT

= 30A

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

4.0

4.5

5.0

5.5

6.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Driver Supply

ltage, PV

& V

[V]

Module Output

ltage, V

OUT

[V]

Figure 8.

Power Loss vs. Driver Supply Voltage

Figure 9.

Power Loss vs. Output Voltage

www.onsemi.com

FDMF5821 • Rev.

1.0

Typical Performance Characteristics

Test Conditions: V

=12 V,

=PV

=5 V,

OUT

=1.8 V,

OUT

=250 nH,

=25°C and natural convection cooling,

unless otherwise noted.

1.01

1.00

0.99

0.98

0.97

0.07

0.06

0.05

0.04

0.03

0.02

0.01

= 12V, PV

& V

= 5V, V

OUT

= 1.8V, I

OUT

= 0A

= 12V, PV

& V

VCC

= 5V, F

= 500kHz, V

OUT

= 1.8V, I

OUT

= 30A

200

250

300

350

400

450

500

200

300

400

500

600

700

800

900 1000

Output Inductor, L

OUT

[nH]

Module Switching Frequenc

[kHz]

Figure 10.

Power Loss vs. Output Inductor

Figure 11.

Driver Supply Current vs. Switching

Frequency

0.036

1.06

= 12V, PV

& V

VCC

= 5V, V

OUT

= 1.8V

1.04

= 12V, V

OUT

= 1.8V, F

= 500kHz, I

OUT

= 0A

0.034

0.032

0.03

1.02

= 1000kHz

1.00

0.98

0.028

0.026

0.024

0.022

0.02

0.96

= 300kHz

0.94

0.92

0.90

0.88

4.0

4.5

5.0

5.5

6.0

10 15 20 25 30 35 40 45 50 55 60

Driver Supply

ltage, PV

& V

VCC

[V]

Module Output Current, I

OUT

[A]

Figure 12.

Driver Supply Current vs. Driver Supply

Figure 13.

Driver Supply Current vs. Output Current

Voltage

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

= 25

IH_PWM

TRI_HI

UVLO

HIZ_PWM

TRI_LO

UVLO

IL_PWM

5.50

4.50

4.75

5.00

5.25

-55

100

125

Driver IC Junction Temperature,

[

Driver Supply

ltage, V

[V]

Figure 14.

UVLO Threshold vs. Temperature

Figure 15.

PWM Threshold vs. Driver Supply Voltage

www.onsemi.com

FDMF5821 • Rev.

1.0

Typical Performance Characteristics

Test Conditions: V

=12 V,

=PV

=5 V,

OUT

=1.8 V,

OUT

=250 nH,

=25°C and natural convection cooling,

unless otherwise noted.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

= 5V

= 25

IH_PWM

TRI_HI

IH_ZCD#

HIZ_PWM

TRI_LO

IL_ZCD#

IL_PWM

100 125

-55

4.50

4.75

5.00

5.25

5.50

Driver IC Junction Temperature, T

[

Driver Supply

ltage, V

[V]

Figure 16.

PWM Threshold vs. Temperature

Figure 17.

ZCD# Threshold vs. Driver Supply

Voltage

0.22

= 5V

1.9

= 5V

0.2

0.18

0.16

0.14

0.12

0.1

1.8

1.7

1.6

1.5

IH_ZCD#

1.4

1.3

1.2

IL_ZCD#

1.1

-55

100

125

-55

100

125

Driver IC Junction Temperature, T

[

Driver IC Junction Temperature, T

[

Figure 18.

ZCD# Threshold vs. Temperature

Figure 19.

ZCD# Pull-Up Current vs. Temperature

2.2

2.0

= 5V

1.9

= 25

2.0

1.8

1.6

1.4

1.2

1.0

IH_EN

1.8

1.7

1.6

1.5

IH_EN

1.4

1.3

1.2

IL_EN

1.1

1.0

4.50

4.75

5.00

5.25

5.50

-55

100

125

Driver IC Junction Temperature, T

[

Driver Supply

ltage, V

[V]

Figure 20.

EN Threshold vs. Driver Supply Voltage

Figure 21.

EN Threshold vs. Temperature

www.onsemi.com

FDMF5821 • Rev.

1.0

Typical Performance Characteristics

Test Conditions: V

=12 V,

=PV

=5 V,

OUT

=1.8 V,

OUT

=250 nH,

=25°C and natural convection cooling,

unless otherwise noted.

0.43

0.42

0.41

0.4

500

450

400

350

300

= 10mA

= 5V

0.39

0.38

0.37

-55

100

125

-55

100

125

Driver IC Junction Temperature, T

[

Driver IC Junction Temperature, T

[

Figure 22.

EN Pull-Down Current vs. Temperature

Figure 23.

Boot Diode Forward Voltage

vs. Temperature

2.5

1.25

1.2

& V

= 5V, PWM = 0V, ZCD# = 0V, EN = 0V

& V

= 5V, ZCD# = 5V, EN = 5V

PWM = 0V

1.5

1.15

1.1

PWM = Float

PWM = 5V

0.5

1.05

-0.5

-1

0.95

0.9

-55

100

125

-55

100

125

Driver IC Junction Temperature, T

[

Driver IC Junction Temperature, T

[

Figure 24.

Driver Shutdown Current

vs. Temperature

Figure 25.

Driver Quiescent Current vs. Temperature

FDMF5821 • Rev.

1.0

www.onsemi.com

Functional Description

The SPS FDMF5821 is a driver-plus-MOSFET module

optimized for the synchronous buck converter topology.

A PWM input signal is required to properly drive the

high-side and the low-side MOSFETs. The part is

capable of driving speed up to 1.5 MHz.

EN / FAULT# (Enable / Fault Flag)

The driver can be disabled by pulling the EN / FAULT#

pin LOW (EN < V

IL_EN

), which holds both GL and GH

LOW regardless of the PWM input state. The driver can

be enabled by raising the EN / FAULT# pin voltage

HIGH (EN > V

IH_EN

). The driver IC has less than 3 µA

shutdown current when it is disabled. Once the driver is

re-enabled, it takes a maximum of 20 µs startup time.

Power-On Reset (POR)

The PWM input stage should incorporate a POR feature

to ensure both LDRV and HDRV are forced inactive

(LDRV = HDRV = 0) until UVLO > ~ 3.8

V (rising

threshold). After all gate drive blocks are fully powered

on and have finished the startup sequence, the internal

driver IC EN_PWM signal is released HIGH, enabling

the driver outputs. Once the driver POR has finished

(<20 µs

maximum), the driver follows the state of the

PWM signal (it is assumed that at startup the controller

is either in a high-impedance state or forcing the PWM

signal to be within the driver 3-state window).

EN / FAULT# pin is an open-drain output for fault flag

with an internal 250 k

pull-down resistor. Logic HIGH

signal from PWM controller or a ~ 10 k

external pull-up

resistor from EN / FAULT# pin to VCC is required to

start driver operation.

Table 1.

UVLO and Enable Logic

UVLO

Driver State

Disabled (GH & GL = 0)

Enabled (

see

Table 2

)

Disabled (GH & GL = 0)

Three conditions below must be supported for normal

startup / power-up.

rises to 5 V, then EN goes HIGH;

EN pin is tied to the VCC pin;

Open

The EN / FAULT# pin has two functions: enabling /

disabling driver and fault flag. The fault flag signal is

active LOW. When the driver detects a fault condition

during operation, it turns on the open-drain on the EN /

FAULT# pin and the pin voltage is pulled LOW. The

fault conditions are:

EN is commanded HIGH prior to 5 V V

reaching

the UVLO rising threshold.

The POR method is to increase the V

over than UVLO

> rising threshold and EN = HIGH.

Under-Voltage Lockout (UVLO)

High-side MOSFET false turn-on or VIN ~ SW short

during low-side MOSFET turn on;

UVLO is performed on V

only, not on PV

or V

When the EN is set HIGH and V

is rising over the

UVLO threshold level (3.8

V), the part starts switching

operation after a maximum 20 µs POR delay. The delay

is implemented to ensure the internal circuitry is biased,

stable, and ready to operate. Two VCC pins are

provided: PVCC and VCC. The gate driver circuitry is

powered from the PVCC rail. The user connects PVCC

to VCC through a low-pass R-C filter. This provides a

filtered 5 V bias to the analog circuitry on the IC.

P-THDN by exceeding 1.5 V on TMON pin.

When the driver detects a fault condition and disables

itself, a POR event on VCC is required to restart the

driver operation.

3-State PWM Input

The FDMF5821 incorporates a 3-state 5 V PWM input

gate drive design. The 3-state gate drive has both logic

HIGH and LOW levels, along with a 3-state shutdown

window. When the PWM input signal enters and

remains within the 3-state window for a defined hold-off

time (t

D_HOLD-OFF

), both GL and GH are pulled LOW. This

feature enables the gate drive to shut down both the

high-side and the low-side MOSFETs to support

features such as phase shedding, a common feature on

multi-phase voltage regulators.

Driver

State

Enable

Disable

Table 2.

EN / PWM / 3-State / ZCD# Logic States

PWM ZCD#

3.4

3.8

[V]

* EN pin keeps HIGH

3-State

Figure 26.

UVLO on VCC

1 (IL > 0), 0 (IL < 0)

www.onsemi.com

FDMF5821 • Rev.

1.0

IH_PWM

PWM

IL_PWM

90%

10%

90%

10%

90%

10%

90%

10%

GH-PHASE

(internal)

BOOT-GND

– V

F_DBOOT

– 1V

90%

PD_PHGLL

D_DEADON

RISE_GH

FALL_GL

PD_PLGHL

D_DEADOFF

RISE_GL

FALL_GH

PD_PHGLL

= PWM HI to GL LO, V

IH_PWM

to 90% GL

FALL_GL

= 90% GL to 10% GL

PD_PLGLH

D_DEADON

= LS Off to HS On Dead Time, 10% GL to V

BOOT-GND

<= PV

– V

F_DBOOT

– 1V or BOOT-GND dip start point

RISE_GH

= 10% GH to 90% GH, V

BOOT-GND

<= PV

– V

F_DBOOT

– 1V or BOOT-GND dip start point to GL bounce start point

PD_PLGHL

= PWM LO to GH LO, V

IL_PWM

to 90% GH or BOOT-GND decrease start point, t

PD_PLGLH

– t

D_DEADOFF

– t

FALL_GH

= 90% GH to 10% GH, BOOT-GND decrease start point to 90% V

or GL dip start point

D_DEADOFF

= HS Off to LS On Dead Time, 90% V

or GL dip start point to 10% GL

RISE_GL

= 10% GL to 90% GL

PD_PLGLH

= PWM LO to GL HI, V

IL_PWM

to 10% GL

Figure 27.

PWM Timing Diagram

(7)

(11)

IH_PWM

(9)

TRI_HI

(10)

TRI_LO

(12)

IL_PWM

PWM

IL_PWM

3-State

Window

3-State

Window

(8)

GH-PHASE

Figure 28.

PWM Threshold Definition

Notes:

7. The

timing diagram in

Figure 28

assumes very slow ramp on PWM.

8. Slow

ramp of PWM implies the PWM signal remains within the 3-state window for a time >>> t

D_HOLD-OFF.

9. V

TRI_HI

= PWM trip level to enter 3-state on PWM falling edge.

10. V

TRI_LO

= P

M trip level to enter 3-state on PWM rising edge.

11. V

IH_PWM

= P

M trip level to exit 3-state on PWM rising edge and enter the PWM HIGH logic state.

12. V

IL_PWM

= PWM trip level to exit 3-state on PWM falling edge and enter the PWM LOW logic state.

www.onsemi.com

FDMF5821 • Rev.

1.0

The primary reason for scaling back on the drive

strength is to limit the peak V

stress when the low-

side MOSFET hard-switches inductor current. This

peak V

stress has been an issue with applications

with large amounts of load transient and fast and

wide output voltage regulation.

Power Sequence

SPS FDMF5821 requires four (4) input signals to

conduct normal switching operation: V

, V

/ PV

PWM, and EN. PWM should not be applied before V

and the amplitude of PWM should not be higher than

. All

other combinations of their power sequences

are allowed. The below example of a power sequence

is for a reference application design:

The MOSFET gate driver in SPS FDMF5821 operates

in one of three modes, described below.

Continuous Current Mode 1 (CCM1) with Positive

Inductor Current

From no input signals

-> V

On: Typical 12 V

In this mode, inductor current is always flowing towards

the output capacitor, typical of a heavily loaded power

stage. The high-side MOSFET turns on with the low-

side body diode conducting inductor current and SW is

approximately a V

below ground, meaning hard-

switched turn-on and turn-off of the high-side MOSFET.

-> V

/ PV

On: Typical 5 V

-> EN HIGH: Typical 5 V

-> PWM Signaling: 5 V HIGH / 0 V LOW

The VIN pins are tied to the system main DC power rail.

PVCC and VCC pins are tied together to supply gate

driving and logic circuit powers from the system V

rail. Or the PVCC pin can be directly tied to the system

rail, and the VCC pin is powered by PVCC pin

through a filter resistor located between PVCC pin and

VCC pin. The filter resistor reduces switching noise

Discontinuous Current Mode (DCM)

Typical of lightly loaded power stage; the high-side

MOSFET turns on with zero inductor current, ramps the

inductor current, then returns to zero every switching

cycle. When the high-side MOSFET turns on under

DCM operation, the SW node may be at any voltage

from a V

below ground to a V

above V

. This is

because after the low-side MOSFET turns off, the SW

node capacitance resonates with the inductor current.

impact from PV

to V

The EN pin can be tied to the V

rail with an external

pull-up resistor and it will maintain HIGH once the V

rail turns on. Or the EN pin can be directly tied to the

PWM controller for other purposes.

The level shifter in driver IC should be able to turn on

the high-side MOSFET regardless of the SW node

voltage. In this case, the high-side MOSFET turns off a

positive current.

High-Side Driver

The high-side driver (HDRV) is designed to drive a

floating N-channel MOSFET (Q1). The bias voltage for

the high-side driver is developed by a bootstrap supply

circuit, consisting of the internal Schottky diode and

external bootstrap capacitor (C

BOOT

). During startup, the

SW node is held at PGND, allowing C

BOOT

to charge to

PVCC through the internal bootstrap diode. When the

PWM input goes HIGH, HDRV begins to charge the

gate of the high-side MOSFET (internal GH pin). During

this transition, the charge is removed from the C

BOOT

and delivered to the gate of Q1. As Q1 turns on, SW

rises to V

, forcing the BOOT pin to V

+ V

BOOT

, which

provides sufficient V

enhancement for Q1. To

complete the switching cycle, Q1 is turned off by pulling

HDRV to SW. C

BOOT

is then recharged to PVCC when

the SW falls to PGND. HDRV output is in phase with

the PWM input. The high-side gate is held LOW when

the driver is disabled or the PWM signal is held within

the 3-state window for longer than the 3-state hold-off

During this mode, both LDRV1 and LDRV2 operate in

parallel and the low-side gate driver pull-up and pull-

down resistors are operating at full strength.

Continuous Current Mode 2 (CCM2) with Negative

Inductor Current

This mode is typical in a synchronous buck converter

pulling energy from the output capacitors and delivering

the energy to the input capacitors (Boost Mode). In this

mode, the inductor current is negative (meaning

towards the MOSFETs) when the low-side MOSFET is

turned off (may be negative when the high-side

MOSFET turns on as well). This situation causes the

low-side MOSFET to hard switch while the high-side

MOSFET acts as a synchronous rectifier (temporarily

operated in synchronous Boost Mode).

During this mode, only the

“

weak

”

LDRV2 is used for

low-side MOSFET turn-on and turn-off. The intention is

to slow down the low-side MOSFET switching speed

when it is hard switching to reduce peak V

stress.

time, t

D_HOLD-OFF

Low-Side Driver

The low-side driver (LDRV) is designed to drive the

gate-source of

a ground-referenced low R

DS(ON)

Dead-Times in CCM1 / DCM / CCM2

N-channel MOSFET (Q2). The bias for LDRV is

internally connected between the PVCC and AGND.

When the driver is enabled, the driver output is 180° out

of phase with the PWM input. When the driver is

disabled (EN = 0 V), LDRV is held LOW.

The driver IC design ensures minimum MOSFET dead

times, while eliminating potential shoot-through (cross-

conduction) currents. To ensure optimal module

efficiency, body diode conduction times must be

reduced to the low nano-second range during CCM1

and DCM operation. CCM2 alters the gate drive

impedance while operating the power MOSFETs in a

different mode versus CCM1 / DCM. Altered dead-time

operation must be considered.

Continuous Current Mode 2 (CCM2) Operation

A main feature of the low-side driver design in SPS

FMDF5821DC is the ability to control the part of the

low-side gate driver upon detection of negative

inductor current, called CCM2 operation. This is

accomplished by using the ZCD comparator signal.

www.onsemi.com

FDMF5821 • Rev.

1.0

switching (negative inductor current). To avoid cross-

conduction, the slowing of the low-side gate also

requires an adjustment (increase) of the dead time

between low-side MOSFET off to high-side MOSFET

Low-Side MOSFET Off to High-Side MOSFET On

Dead Time in CCM1 / DCM

To prevent overlap during the low-side MOSFET off to

high-side MOSFET on switching transition, adaptive

circuitry monitors the voltage at the GL pin. When the

PWM signal goes HIGH, GL goes LOW after a

propagation delay (t

PD_PHGLL

). Once the GL pin is

discharged below ~ 1

–

2 V, GH is pulled HIGH after an

on.

fairly long fixed dead time (t

FD_ON2

)

implemented to ensure there is no cross conduction

during this CCM2 operation.

High-Side MOSFET Off to Low-Side MOSFET On

Dead Time in CCM1 / DCM

adaptive delay, t

D_DEADON

To get very short dead time during high-side MOSFET

off to low-side MOSFET on transition, a fixed-dead-time

method is implemented in the SPS gate driver. The

fixed-dead-time circuitry monitors the internal HS signal

and adds a fixed delay long enough to gate on GL after

a desired t

D_DEADOFF

(~ 5

ns, t

D_DEADOFF

= t

FD_OFF1

regardless of SW node state.

Some situations where the ZCD# rising-edge signal

leads the PWM rising edge by tens of nanoseconds,

can cause GH and GL overlap. This event can occur

when the PWM controller sends PWM and ZCD#

signals that lead, lag, or are synchronized. To avoid this

phenomenon, a secondary fixed propagation delay

FD_ON1

) is added to ensure there is always a minimum

delay between low-side MOSFET off to high-side

MOSFET on.

Exiting 3-State Condition

When exiting a valid 3-state condition, the gate driver of

the FDMF5821 follows the PWM input command. If the

PWM input goes from 3-state to LOW, the low-side

MOSFET is turned on. If the PWM input goes from 3-

state to HIGH, the high-side MOSFET is turned on. This

is illustrated in

Figure 29

below.

Low-Side MOSFET Off to High-Side MOSFET On

Dead Time in CCM2

As noted in the CCM2 Operation section, the low-side

driver strength is scale-able upon detection of CCM2.

CCM2 feature slows the charge and discharge of the

low-side MOSFET gate to minimize peak switching

voltage overshoots during low-side MOSFET hard-

IH_PWM

TRI_HI

IH_PWM

IL_PWM

TRI_HI

TRI_LO

3-State

Window

TRI_HI

TRI_LO

PWM

GH to SW

IL_PWM

90%

10%

90%

10%

PD_TLGLH

PD_THGHH

D_HOLD-OFF

PD_PHGLL

D_DEADON

PD_PLGHL

D_DEADOFF

PD_PHGLL

D_DEADON2

D_HOLD-OFF

Less than

D_HOLD-OFF

Less than

D_HOLD-OFF

Inductor

Current

3-State

HOLD_OFF

Window

3-State

HOLD_OFF

Window

GL / GH

off

GL / GH

off

NOTES:

PD_XXX

= propagation delay from external signal (PWM, ZCD#, etc.) to IC generated signal. Example : t

PD_PHGLL

–

PWM going HIGH to low-side MOSFET V

(GL) going LOW

D_XXX

= delay from IC generated signal to IC generated signal. Example : t

D_DEADON

–

low-side MOSFET V

LOW to high-side MOSFET V

HIGH

PWM

Exiting 3-State

PD_PHGLL

= PWM rise to LS V

fall, V

IH_PWM

to 90% LS V

PD_PLGHL

= PWM fall to HS V

fall, V

IL_PWM

to 90% HS V

PD_PHGHH

= PWM rise to HS V

rise, V

IH_PWM

to 10% HS V

(ZCD# held LOW)

PD_TSGHH

= PWM 3-State to HIGH to HS V

rise, V

IH_PWM

to 10% HS V

PD_TSGLH

= PWM 3-State to LOW to LS V

rise, V

IL_PWM

to 10% LS V

ZCD#

Dead Times

PD_ZLGLL

= ZCD# fall to LS V

fall, V

IL_ZCD#

to 90% LS V

PD_ZHGLH

= ZCD# rise to LS V

rise, V

IH_ZCD#

to 10% LS V

D_DEADON

= LS V

fall to HS V

rise, LS-Comp trip value to 10% HS V

D_DEADOFF

= SW fall to LS V

rise, SW-Comp trip value to 10% LS V

Figure 29.

PWM HIGH / LOW / 3-State Timing Diagram

FDMF5821 • Rev.

1.0

www.onsemi.com

IH_PWM

Exiting 3-State with Low BOOT-SW Voltage

The SPS module is used in multi-phase VR topologies

requiring the module to wait in 3-state condition for an

indefinite time. These long idle times can bleed the boot

capacitor down until eventual clamping occurs based

PWM

GH to

PHASE

on PV

and V

OUT

. Low BOOT-SW can cause

increased propagation delays in the level-shift circuit as

well as all HDRV floating circuitry, which is biased from

the BOOT-SW rail. Another issue with a depleted

BOOT-SW capacitor voltage is the voltage applied to

the HS MOSFET gate during turn-on. A low BOOT-SW

voltage results in a very weak HS gate drive, hence,

much larger HS R

DS(ON)

and increased risk for

unreliable operation since the HS MOSFET may not

turn-on if BOOT-SW falls too low.

GL / GH

off

100 ns

GL pulse

LOW

BOOT-SW

detect

Low BOOT-SW voltage detected

Figure 30.

Low BOOT-SW Voltage Detected and

PWM from 3-State to HIGH

PWM LOW

> 100 ns

To address this issue, the SPS monitors for a low

BOOT-SW voltage when the module is in 3-state

condition. When the module exits 3-state condition with

a low BOOT-SW voltage, a 100

ns minimum GL on

time is output regardless of the PWM input. This

ensures the boot capacitor is adequately charged to a

safe operating level and has minimal impact on

transient response of the system. Scenarios of exiting

3-state condition are listed below.

IL_PWM

PWM

GH to

PHASE

GL / GH

off

> 100 ns

GL pulse

LOW

BOOT-SW

detect

If the part exits 3-state with a low BOOT-SW voltage

condition and the controller commands PWM=HIGH,

the SPS outputs a 100 ns GL pulse and follows the

PWM=HIGH command (

ee Figure 30)

Low BOOT-SW voltage detected

Figure 31.

Low BOOT-SW Voltage Detected and

PWM from 3-State to LOW for more than 100 ns

If the part exits 3-state with a low BOOT-SW

voltage condition and the controller commands

PWM=LOW for 100

ns or more, the SPS follows

the PWM input. If PWM=LOW for less than 100 ns,

GL remains on for 100

ns then follows the PWM

input (

see

Figure 31

and

Figure 32)

PWM LOW

< 100 ns

IL_PWM

PWM

GH to

PHASE

If no low BOOT-SW condition is detected, the SPS

follows the PWM command when exiting 3-state

(

ee Figure 33

)

GL / GH

off

The SPS momentarily stays in an adaptive dead time

mode when exiting 3-state condition or at initial power-

up. This adaptive dead time mode lasts for no more

than two (2) consecutive switching cycles, giving the

boot capacitor ample time to recharge to a safe level.

The module switches back to fixed dead time control for

maximum efficiency.

100 ns

GL pulse

LOW

BOOT-SW

detect

Low BOOT-SW voltage detected

Figure 32.

Low BOOT-SW voltage Detected and

PWM from 3-State to LOW for Less than 100 ns

IH_PWM

IL_PWM

PWM

GH to

PHASE

GL / GH

off

GL / GH

off

LOW

BOOT-SW

detect

Low BOOT-SW voltage NOT detected

Figure 33.

Low BOOT-SW Voltage NOT Detected

and PWM from 3-State to HIGH or LOW

www.onsemi.com

FDMF5821 • Rev.

1.0

within a 0.5 mV worst-case range. The negative offset

is to ensure the inductor current never reverses; some

small body-diode conduction is preferable to having

negative current.

Zero Cross Detect (ZCD) Operation

The ZCD control block houses the circuitry that

determines when the inductor current reverses direction

and controls when to turn off the low-side MOSFET. A

low offset comparator monitors the SW-to-PGND

voltage of the low-side MOSFET during the LS

MOSFET on-time. When the sensed voltage switches

polarity from negative to positive, the comparator

changes state and reverse current has been detected.

This comparator offset must sense the negative V

The comparator is switched on after the rising edge of

the low-side gate drive and turned off by the signal at

the input to the low-side gate driver. In this way, the

zero-current comparator is connected with a break-

before-make connection, allowing the comparator to be

designed with low-voltage transistors.

IH_ZCD#

IL_ZCD#

ZCD#

IH_PWM

IL_PWM

PWM

90%

GH to

10%

90%

10%

90%

10%

PD_PLGHL

10%

PD_PHGLL

D_DEADON

PD_PHGLL

D_DEADON2

PD_ZCD

PD_PHGHH

PD_ZHGLH

PD_ZLGLL

Delay from PWM going

HIGH to HS V

HIGH

(HS turn-on in DCM)

Delay from ZCD# going

HIGH to LS V

HIGH

LOW to LS V

LOW

D_DEADOFF

CCM

DCM

(Negative inductor current)

OUT

Inductor

Current

(simplified

slopes)

(zoom)

ZCD_OFF

-0.5mV

DCM operation: Diode

Emulation using the GL (LS

MOSFET V

) to eliminate

negative inductor current

DCM operation: Diode

Emulation using the GL (LS

MOSFET V

) to eliminate

negative inductor current

ZCD# used to

control negative

inductor current

(fault condition)

CCM operation with

positive inductor current

CCM operation with

negative inductor current

Figure 34.

ZCD# & PWM Timing Diagram

driver temperature versus TMON pin voltage with 25 k

Temperature Monitor (TMON)

TMON

and 0.1 µF C

TMON

The FDMF5821 provides a temperature monitor (TMON)

to warn of over-temperature conditions. The gate driver

uses the TMON pin to source an analog current

proportional to absolute temperature (PTAT). It is

expected that the analog current will be used with a

properly chosen external resistor to AGND to develop a

TMON

[V]

1.45

1.0

voltage across TMON (V

TMON

) proportional to the

temperature. A filter capacitance may be needed to

minimize noise spikes in the analog current, I

TMON

. Noise

spikes are generated from power MOSFET switching

dv / dt and di / dt coupling back into the driver VCC pin.

150

[°C]

* R

TMON

= 25 k

, C

TMON

= 0.1 µF

The TMON pin needs a pull-down resistor (R

TMON

) and

filter capacitor (C

TMON

) to AGND. With 25 k

TMON

and

0.1 µF C

TMON

, the TMON voltage is around 1 V at 25°C

of gate driver T

, and 1.5 V when the driver temperature

reaches 150°C. The V

TMON

signal can be connected to

PWM controller or MCU in system to indicate the

thermal status of the gate drive

r. Figure 35

shows gate

Figure 35.

Gate Driver T

vs. V

TMON

The TMON voltage is defined by following equation:

ꢅ

ꢇ

ꢅ

ꢇ

_{ꢀꢁꢂꢃ
ꢄ

ꢆ

ꢈ

ꢉ
ꢀꢁꢂ
ꢃ
ꢄ

ꢊꢋ

ꢌ

ꢍ
ꢀꢁꢂ
ꢃ
ꢄꢅꢎꢏꢇ}

ꢑꢒꢄꢊꢋ

(1)

ꢈ

ꢐ

ꢌ

ꢖꢗꢘꢙꢚꢗꢄꢛ

ꢕ

ꢝ

ꢞꢟꢠꢡꢄꢊꢋꢢ

ꢜ

ꢑꢓꢔꢄꢕ

ꢌ

ꢍ

ꢀꢁꢂꢃ

ꢄꢅꢎꢏꢇ

www.onsemi.com

FDMF5821 • Rev.

1.0

P-THDN

Temp. [°C]

Programmable Thermal Shutdown (P-THDN)

When the TMON pin voltage exceeds 1.5 V, the internal

comparator shuts down the driver (EN pin goes LOW).

The programmable thermal shutdown temperature

range can be adjusted by R

TMON

so that the shutdown

temperature can be customized. The equation below

shows the relationship between R

TMON

value in design

and desirable thermal shutdown temperature.

200

150

100

ꢍ

ꢀꢁꢂꢃ

ꢄꢅꢎꢏꢇ

ꢑꢓꢔꢄꢕ

25.9

29.5

TMON

]

ꢈ

ꢐ

ꢢ

(2)

* V

TMON

= 1.5 V, C

TMON

= 0.1 µF

ꢣ

ꢤ

ꢛꢥꢖꢦꢄꢛꢚꢆꢧꢚꢗꢨꢩꢪꢗꢚꢄꢕ

ꢝ

ꢓꢔꢞꢄꢕ

ꢌ

ꢒꢞꢠꢞꢄꢎꢏ

Figure 36.

TMON

vs. P-THDN Temperature

Figure 36

shows the relationship between R

TMON

and P-

THDN temperature. Increasing the R

TMON

value results

in a lower P-THDN temperature. The system designer

can define the shutdown temperature of FDMF5821

based on the system thermal design.

Catastrophic Fault

SPS FDMF5821 includes a catastrophic fault feature. If

a HS MOSFET short is detected, the driver internally

pulls the EN / FAULT# pin LOW and shuts down the

SPS driver. The intention is to implement a basic circuit

to test the HS MOSFET short by monitoring LDRV and

the state of SW node.

The P-THDN is a latch-off shutdown, so the (POR) on

VCC is needs to re-enable the gate driver. If not using

TMON / P-THDN features, tie the TMON pin to AGND.

If a HS short fault is detected, the SPS module clocks

the fault latch shutting down the module. The module

requires a VCC POR event to restart.

PWM

LDRV

(internal)

HS FET short during

LS FET turning on

Potential noise from

adjacent phases switching

SW-Fault

(internal)

false trigger

FAULT

(internal)

EN/FAULT#

Normal switching operation

EN/FAULT#

pulled LOW and

driver IC disabled

Figure 37.

Catastrophic Fault Waveform

www.onsemi.com

FDMF5821 • Rev.

1.0

Application Information

PWM (Input)

Decoupling Capacitor for PVCC & VCC

The PWM pin recognizes three different logic levels

from PWM controller: HIGH, LOW, and 3-state. When

the PWM pin receives a HIGH command, the gate

driver turns on the high-side MOSFET. When the PWM

pin receives a LOW command, the gate driver turns on

the low-side MOSFET. When the PWM pin receives a

For the supply inputs (PVCC and VCC pins), local

decoupling capacitors are required to supply the peak

driving current and to reduce noise during switching

operation. Use at least 0.68 ~ 1 µF / 0402 ~ 0603 / X5R

~ X7R multi-layer ceramic capacitors for both power

rails. Keep these capacitors close to the PVCC and

VCC pins and PGND and AGND copper planes. If they

need to be located on the bottom side of board, put

through-hole vias on each pads of the decoupling

capacitors to connect the capacitor pads on bottom with

PVCC and VCC pins on top.

voltage signal inside of the 3-state window (V

TRI_Window

)

and exceeds the 3-state hold-off time, the gate driver

turns off both high-side and low-side MOSFETs. To

recognize the high-impedance 3-state signal from the

controller, the PWM pin has an internal resistor divider

from VCC to PWM to AGND. The resistor divider sets

a voltage level on the PWM pin inside the 3-state

window when the PWM signal from the controller is

high-impedance.

The supply voltage range on PVCC and VCC is 4.5 V ~

5.5 V, typically 5 V for normal applications.

R-C Filter on VCC

ZCD# (Input)

The PVCC pin provides power to the gate drive of the

high-side and low-side power MOSFETs. In most cases,

PVCC can be connected directly to VCC, which is the

pin that provides power to the analog and logic blocks of

the driver. To avoid switching noise injection from PVCC

into VCC, a filter resistor can be inserted between

PVCC and VCC decoupling capacitors.

When the ZCD# pin sets HIGH, the ZCD function is

disabled and high-side and low-side MOSFETs switch in

CCM (or FCCM, Forced CCM) by PWM signal. When

the ZCD# pin is LOW, the low-side MOSFET turns off

when the SPS driver detects negative inductor current

during the low-side MOSFET turn-on period. This ZCD

feature allows higher converter efficiency under light-

load condition and PFM / DCM operation.

Recommended filter resistor value range is 0 ~ 10

typically 0

for most applications.

The ZCD# pin has an internal current source from VCC,

so it may not need an external pull-up resistor. Once

is supplied and the driver is enabled, the ZCD# pin

holds logic HIGH without external components and the

driver operates switching in CCM or FCCM. The ZCD#

pin can be grounded for automatic diode emulation in

DCM by the SPS itself, or it can be connected to the

controller or system to follow the command from them.

Bootstrap Circuit

The bootstrap circuit uses a charge storage capacitor

BOOT

). A bootstrap capacitor of 0.1 ~ 0.22 µF / 0402 ~

0603 / X5R ~ X7R is usually appropriate for most

switching applications. A series bootstrap resistor may

be needed for specific applications to lower high-side

MOSFET switching speed. The boot resistor is required

when the SPS is switching above 15 V V

; when it is

effective at controlling V

overshoot. R

BOOT

value from

zero to 6

is typically recommended to reduce

excessive voltage spike and ringing on the SW node. A

higher R

BOOT

value can cause lower efficiency due to

high switching loss of high-side MOSFET.

The typical pull-up resistor value on ZCD# ~ VCC is

10 k

for stable ZCD# HIGH level. If not using the ZCD

feature, tie the ZCD# pin to VCC with a pull-up resistor.

Do not add any noise filter capacitor on the ZCD# pin.

TMON (Output) / P-THDN

During normal operation (no fault detected), the TMON

pin sources an analog current proportional to the

absolute temperature of the gate driver. With 25

TMON

and 0.1

µF C

TMON

on TMON pin to AGND, it

outputs 1 V at 25°C driver T

and 1.5 V at 150°C driver

. The C

TMON

is a filter capacitor to minimize switching

noise injection onto the TMON pin. The TMON pin can

be connected to a PWM controller or system controller

and used to monitor the SPS module temperature.

Do not add a capacitor or resistor between the BOOT

pin and GND.

EN / FAULT# (Input / Output)

The driver in SPS is enabled by pulling the EN pin

HIGH. The EN pin has internal 250

pull-down

resistor, so it needs to be pulled-up to V

with an

external resistor or connected to the controller or system

to follow up the command from them. If the EN pin is

floated, it cannot turn on the driver.

If the TMON pin voltage exceeds 1.5

V with 25

TMON

, the driver temperature is over 150°C and the

driver is shut down by the P-THDN feature. The 150°C

thermal shutdown temperature can be adjusted by the

TMON

value to define the THDN temperature for the

application.

Refer to the P-THDN section to define

thermal shutdown temperature and R

TMON

value.

The fault flag LOW signal is asserted on the EN /

FAULT# pin when the driver temperature reaches P-

THDN temperature or a high-side MOSFET fault occurs.

Then the driver shuts down.

The typical pull-up resistor value on EN ~ VCC is 10 k

Do not add a noise filter capacitor on the EN pin.

If not using the TMON / P-THDN features, tie the TMON

pin to GND.

www.onsemi.com

FDMF5821 • Rev.

1.0

Power Loss and Efficiency

Figure 38

shows an example diagram for power loss

and efficiency measurement.

Power loss calculation and equation examples:

= (V



) + (V



)

[W]

[%]

= V



OUT

= V

OUT



OUT

LOSS_MODULE

= P

–

LOSS_TOTAL

= P

–

OUT

EFFI

MODULE

= (P

/ P

)



100

EFFI

TOTAL

= (P

OUT

/ P

)



100

Pulse

Generator

PWM

/ I

Power

VIN

Supply 1

/ I

Power

Supply 2

Electronic

Load

PVCC

VCC

VOUT

/ I

OUT

/ I

OUT

Fairchild SPS

Evaluation Board

Figure 38.

Power Loss and Efficiency Measurement Diagram

www.onsemi.com

FDMF5821 • Rev.

1.0

PCB Layout Guideline

Figure 39

through

Figure 42

provide examples of single-

phase and multi-phase layouts for the FDMF5821 and

critical components. All of the high-current paths; such

as VIN, SW, VOUT, and GND coppers; should be short

and wide for low parasitic inductance and resistance.

This helps achieve a more stable and evenly distributed

current flow, along with enhanced heat radiation and

system performance.

A boot resistor may be required when the SPS is

operating above 15 V V

and it is effective to control the

high-side MOSFET turn-on slew rate and SW voltage

overshoot. R

BOOT

can improve noise operating margin in

synchronous buck designs that may have noise issues

due to ground bounce or high positive and negative V

ringing. Inserting a boot resistance lowers the SPS

module efficiency. Efficiency versus switching noise

must be considered. R

BOOT

values from 0.5

to 6.0

are typically effective in reducing V

overshoot.

Input ceramic bypass capacitors must be close to the

VIN and PGND pins. This reduces the high-current

power loop inductance and the input current ripple

induced by the power MOSFET switching operation.

The VIN and PGND pins handle large current transients

with frequency components greater than 100

MHz. If

possible, these pins should be connected directly to the

VIN and board GND planes. The use of thermal relief

traces in series with these pins is not recommended

since this adds extra parasitic inductance to the power

path. This added inductance in series with either the

VIN or PGND pin degrades system noise immunity by

increasing positive and negative V

ringing.

The SW copper trace serves two purposes. In addition

to being the high-frequency current path from the SPS

package to the output inductor, it serves as a heat sink

for the low-side MOSFET. The trace should be short

and wide enough to present a low-impedance path for

the high-frequency, high-current flow between the SPS

and the inductor. The short and wide trace minimizes

electrical losses and SPS temperature rise. The SW

node is a high-voltage and high-frequency switching

node with high noise potential. Care should be taken to

minimize coupling to adjacent traces. Since this copper

trace acts as a heat sink for the low-side MOSFET,

balance using the largest area possible to improve SPS

cooling while maintaining acceptable noise emission.

PGND pad and pins should be connected to the GND

copper plane with multiple vias for stable grounding.

Poor grounding can create a noisy and transient offset

voltage level between PGND and AGND. This could

lead to faulty operation of gate driver and MOSFETs.

Ringing at the BOOT pin is most effectively controlled

by close placement of the boot capacitor. Do not add

any additional capacitors between BOOT to PGND. This

may lead to excess current flow through the BOOT

diode, causing high power dissipation.

An output inductor should be located close to the

FDMF5821 to minimize the power loss due to the SW

copper trace. Care should also be taken so the inductor

dissipation does not heat the SPS.

PowerTrench

MOSFETs are used in the output stage

and are effective at minimizing ringing due to fast

switching. In most cases, no RC snubber on SW node is

required. If a snubber is used, it should be placed close

to the SW and PGND pins. The resistor and capacitor of

the snubber must be sized properly to not generate

excessive heating due to high power dissipation.

The ZCD# and EN pins have weak internal pull-up and

pull-down current sources, respectively. These pins

should not have any noise filter capacitors. Do not float

these pins unless absolutely necessary.

Put multiple vias on the VIN and VOUT copper areas to

interconnect top, inner, and bottom layers to evenly

distribute current flow and heat conduction. Do not put

too many vias on the SW copper to avoid extra parasitic

inductance and noise on the switching waveform. As

long as efficiency and thermal performance are

acceptable, place only one SW node copper on the top

layer and put no vias on the SW copper to minimize

switch node parasitic noise. Vias should be relatively

large and of reasonably low inductance. Critical high-

frequency components; such as R

BOOT

, C

BOOT

, RC

snubber, and bypass capacitors; should be located as

close to the respective SPS module pins as possible on

the top layer of the PCB. If this is not feasible, they can

be placed on the board bottom side and their pins

connected from bottom to top through a network of low-

inductance vias.

Decoupling capacitors on PVCC, VCC, and BOOT

capacitors should be placed as close as possible to the

PVCC ~ PGND, VCC ~ AGND, and BOOT ~ PHASE pin

pairs to ensure clean and stable power supply. Their

routing traces should be wide and short to minimize

parasitic PCB resistance and inductance.

The board layout should include a placeholder for small-

value series boot resistor on BOOT ~ PHASE. The boot-

loop size, including series R

BOOT

and C

BOOT

, should be

as small as possible.

www.onsemi.com

FDMF5821 • Rev.

1.0

PCB Layout Guideline

(Continued)

Figure 39.

Single-Phase Board Layout Example

–

Top View

Figure 40.

Single-Phase Board Layout Example

–

Bottom View (Mirrored)

FDMF5821 • Rev.

1.0

www.onsemi.com

PCB Layout Guideline

(Continued)

Figure 41.

6-Phase Board Layout Example with 6 mm x 6 mm Inductor

–

Top View

Figure 42.

6-Phase Board Layout Example with 6 mm x 6 mm Inductor

–

Bottom View (Mirrored)

FDMF5821 • Rev.

1.0

www.onsemi.com

0.10

0.05

C A B

3.80±0.10

(0.85)

C.L.

0.40

0.50

0.30

0.35

0.15

(2X)

0.85

16 17

18 19 20 21

22 23

0.40

0.55

1.03

C.L.

0.30

1.92±0.10

0.30

0.55

(0.22)

0.45

1.03±0.10

0.40

0.50

0.30

PIN #1 INDICATOR

(31X)

0.30

0.20

0.50

(0.38)

1.98±0.10

1.32±0.10

0.50

SEE

DETAIL ‘A’

PIN#1

INDICATOR

0.10 C

5.00±0.10

C.L.

NOTES: UNLESS OTHERWISE SPECIFIED

C.L.

5.00±0.10

A) DOES

NOT FULLY CONFORM TO JEDEC

REGISTRATION MO-220, DATED

MAY/2005.

0.10 C

B) ALL

DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS

DO NOT INCLUDE BURRS

OR MOLD FLASH. MOLD FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING

AND TOLERANCING PER

ASME Y14.5M-1994.

0.10 C

E) DRAWING

FILE NAME: MKT-PQFN31BREV3

0.80

0.70

0.08 C

0.30

0.20

0.05

0.00

SEATING

PLANE

SCALE: 2:1

C.L.

2.70

2.10

1.90

1.75

1.90

0.60

0.40

0.05

0.00

0.10

0.27

0.62

5.40

C.L.

0.50 TYP

1.75

1.90

2.10

1.90

0.60(13X)

0.20

0.50 TYP

0.30 (13X)

LAND PATTERN

RECOMMENDATION

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at

www.onsemi.com/site/pdf/Patent

−

Marking.pdf

. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMEN

N. American Technical Support

: 800

−

282

−

9855

ll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81

−

5817

−

1050

ON Semiconductor Website

www.onsemi.com

Order Literature

: http://www.onsemi.com/orderlit

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone

: 303

−

675

−

2175 or 800

−

344

−

3860

ll Free USA/Canada

Fax

: 303

−

675

−

2176 or 800

−

344

−

3867

ll Free USA/Canada

: orderlit@onsemi.com

For additional information, please contact your local

Sales Representative

Semiconductor Components Industries, LLC

onsemi-FDMF5821

Related Posts

CUI-CPE-171

DB-Unlimited-TP243408-1

DB-Unlimited-TE054003-2