onsemi-FDMS0310AS

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August 2014  
FDMS0310AS  
N-Channel PowerTrench

®

SyncFET

TM  

30 V, 22 A, 4.3 m
Ω  
Features  
General Description  
The FDMS0310AS has been designed to minimize losses in  
power conversion application. Advancements in both silicon and  
package technologies have been combined to offer the lowest  
r

DS(on)

while maintaining excellent switching performance.This  
device has the added benefit of an efficient monolithic Schottky  
body diode.  
„
Max r

DS(on)

= 4.3 m
Ω
at V

GS

= 10 V, I

D

= 19 A  
„
Max r

DS(on)

= 5.2 m
Ω
at V

GS

= 4.5 V, I

D

= 17 A  
„
Advanced package and Silicon combination for low r

DS(on)  

and high efficiency  
„
SyncFET

TM

Schottky Body Diode  
„
MSL1 robust package design  
„
100% UIL tested  
Applications  
„
Synchronous Rectifier for DC/DC Converters  
„
Notebook Vcore/GPU low side switch  
„
Networking Point of Load low side switch  
„
T
e
lecom secondary side rectification  
„
RoHS Compliant  
Bottom  
Top  
Pin 1  
D
D
D
G
5
6
7
8
4
3
2
1
S
S
S
G
S
S
S
D
D
D
D
D
Power 56  
MOSFET Maximum Ratings
T

A

= 25°C unless otherwise noted  
Symbol  
V

DS  

V

GS  

Parameter  
Ratings  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
30  
V
V
(Note 4)  
±20  
Drain Current
 
-Continuous (Package limited)  
-Continuous (Silicon limited)  
-Continuous  
T

C

= 25°C  

C

= 25°C  
22  
T
80  
I

D  

A
T

A

= 25°C  
(Note 1a)  
(Note 3)  
(Note 1a)  
19  
100  
-Pulsed  
E

AS  

Single Pulse Avalanche Energy  
Power Dissipation  
33  
mJ  
W
T

C

= 25°C  
T

A

= 25°C  
41  
P

D  

Power Dissipation  
2.5  
T

J

, T

STG  

Operating and Storage Junction
T
e
mperature Range  
-55 to +150  
°C  
Thermal Characteristics  
R

θ
JC  

R

θ
JA  

Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
3.0  
50  
°C/W  
(Note 1a)  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
Reel Size  
13 ’’  
Tape Width  
12 mm  
Quantity  
FDMS0310AS  
FDMS0310AS  
Power 56  
3000 units  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
1

Electrical Characteristics
T

J

= 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BV

DSS  

Drain to Source Breakdown Voltage  
I

D

= 1 mA, V

GS

= 0 V  
30  
33  
V
V
Drain to Source Breakdown Voltage  
Transient  
BV

DSST  

V

GS

= 0 V, Transient = 100 ns  
Δ
BV

DSS  

Δ
T

J  

Breakdown Voltage
T
e
mperature  
Coefficient  
I

D

= 10 mA, referenced to 25°C  
23  
mV/°C  
I

DSS  

I

GSS  

Zero Gate Voltage Drain Current  
V

DS

= 24 V, V

GS

= 0 V  
500  
100  
μ
A  
Gate to Source Leakage Current, Forward
 
V

GS

= 20 V, V

DS

= 0 V  
nA  
On Characteristics  
V

GS(th)  

Gate to Source Threshold Voltage  
V

GS

= V

DS

, I

D

= 1 mA  

D

= 10 mA, referenced to 25°C  

GS

= 10
V
,
I

D

= 19 A  
1.2  
1.5  
-4  
3.0  
V
Δ
V

GS(th)  

Δ
T

J  

Gate to Source Threshold Voltage  
T
e
mperature Coefficient  
I
mV/°C  
V
3.6  
4.5  
4.8  
103  
4.3  
5.2  
6.0  
r

DS(on)  

g

FS  

Static Drain to Source On Resistance  
Forward Transconductance  
V

GS

= 4.5 V, I

D

= 17 A  
m
Ω  
V

GS

= 10
V
,
I

D

= 19 A, T

J

= 125°C  
V

DS

= 5
V
,
I

D

= 19 A  
S
Dynamic Characteristics  
C

iss  

C

oss  

C

rss  

R

g  

Input Capacitance  
1715  
655  
75  
2280  
870  
110  
2.5  
pF  
pF  
pF  
Ω
V

DS

= 15 V, V

GS

= 0 V,  
f = 1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
0.7  
Switching Characteristics  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn-On Delay Time  
Rise Time  
9.0  
3.9  
25  
18  
10  
40  
10  
37  
19  
ns  
ns  
V

DD

= 15 V, I

D

= 19 A,  
V

GS

= 10 V, R

GEN

= 6
Ω  
Turn-Off Delay Time  
Fall Time  
ns  
3.2  
27  
ns  
Q

g  

T
o
tal Gate Charge  
T
o
tal Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
V

GS

= 0 V to 10 V  
V

GS

= 0 V to 4.5 V  
nC  
nC  
nC  
nC  
Q

g  

13  
V

DD

= 15
V
,  

D

= 19 A  
I
Q

gs  

Q

gd  

4.2  
3.7  
Drain-Source Diode Characteristics  
V

GS

= 0 V, I

S

= 2 A  
(Note 2)  
(Note 2)  
0.6  
0.8  
24  
0.8  
1.2  
38  
V

SD  

Source-Drain Diode
 
Forward Voltage  
V
V

GS

= 0 V, I

S

= 19 A  
t

rr  

Reverse Recovery Time  
ns  
I

F

= 19 A, di/dt = 300 A/
μ
s  
Q

rr  

Reverse Recovery Charge  
24  
38  
nC  
Notes
:  
2
1. R  
is determined with the device mounted on a 1 in
 
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R  
is guaranteed by design while R
 
is determined by  
θ
CA  
θ
JA  
θ
JC  
the user’s board design.  
a. 50 °C/W when mounted
 
on a  
b. 125 °C/W when mounted on
 
a  
minimum pad of 2 oz copper.  
2
1 in
 
pad of
 
2 oz
 
copper.  
2. Pulse Test: Pulse Width < 300
μ
s, Duty cycle < 2.0%.  
3. E
 
of 33 mJ is based on starting T
 
= 25
°
C, L = 0.3 mH, I
 
= 15 A, V
 
= 27
V
, V
 
=
1
0 V.  
AS  
J
AS  
DD  
GS  
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
2

Typical Characteristics
T

J

= 25°C unless otherwise noted  
100  
5
4
3
2
1
0
V

GS

= 10 V  
V

GS

= 6 V  
PULSE DURATION = 80
μ
s  
DUTY CYCLE = 0.5% MAX  
V

GS

= 3 V  
80  
60  
40  
20  
0
V

GS

= 4.5 V  
V

GS

= 4 V  
V

GS

= 3.5 V  
V

GS

= 3 V  
V

GS

= 3.5 V  
V

GS

= 4 V  
PULSE DURATION = 80
μ
s  
DUTY CYCLE = 0.5% MAX  
V

GS

= 6 V  
60  
V

GS

= 4.5 V  
40  
V

GS

= 10 V  
80 100  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
0
20  
V

DS

,
DRAIN TO SOURCE VOLTAGE (V)  
I

D

,
DRAIN CURRENT (A)  
Figure 1.
 
On Region Characteristics  
Figur
e
2
. N
 
o r m a l i z e d O n – R e s i s ta n c e  
vs Drain Current and Gate Voltage  
1.6  
16  
I

D

= 19 A  

GS

= 10 V  
PULSE DURATION = 80
μ
s  
DUTY CYCLE = 0.5% MAX  
V
14  
12  
10  
8
1.4  
1.2  
1.0  
0.8  
0.6  
I

D

= 19 A  
T

J

= 125

o  

C
6
4
T

J

= 25

o  

C
2
-75 -50 -25  
0
25 50 75
 
100 125 150  
2
4
6
8
10  
T

J

,
JUNCTION TEMPERATURE
(

o

C
)  
V

GS

,
GATE TO SOURCE VOLTAGE (V)  
Figur
e
4
. On-Resistance
 
vs Gate to  
Source Voltage  
Figure 3. Normalized On Resistance  
vs Junction Temperature  
100  
100  
PULSE DURATION = 80
μ
s  
DUTY CYCLE = 0.5% MAX  
V

GS

= 0 V  
T

J

= 125

o  

80  
60  
40  
20  
0
10  
1
C
V

DS

= 5 V  
T

J

= 125

o  

C
T

J

= 25

o

C  
T

J

= 25

o  

C
0.1  
T

J

= -55

o  

C
T

J

= -55

o  

C
0.01  
0.001  
1
2
3
4
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V

GS

, GATE TO SOURCE VOLTAGE (V)  
V

SD

, BODY DIODE FORWARD VOLTAGE (V)  
Figure 5.
 
Transfer Characteristics  
Figur
e
6
. Source
 
to Drain Diode  
Forward Voltage vs Source Current  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
3

Typical Characteristics
T

J

= 25°C unless otherwise noted  
3000  
1000  
10  
I

D

= 19 A  
C

iss  

C

oss  

C

rss  

8
6
4
2
0
V

DD

= 15 V  
V

DD

= 10 V  
V

DD

= 20 V  
100  
40  
f = 1 MHz  
= 0 V  
V
GS  
0
5
10  
15  
20  
25  
30  
0.1  
1
10  
30  
V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
Q ,
 
GATE CHARGE (nC)  
g
Figure 7.
 
Gate Charge Characteristics  
Figur
e
8
. C
 
a p a c i t a n c e v s D r a i n  
to Source Voltage  
100  
80  
60  
40  
20  
0
40  
T

J

= 25

o

C  
V

GS

= 10 V  
10  
T

J

= 100

o

C  
V

GS

= 4.5 V  
T

J

= 125

o  

C
R

θ
JC

= 3.0

o

C/W  
Limited by Package  
25 50  
1
0.001  
0.01  
0.1  
1
10  
40  
75  
100  
125  
150  
T

C

,
CASE TEMPERATURE
(

o

C
)  
t

AV

, TIME IN AVALANCHE (ms)  
Figur
e
9
. U
 
n c l a m p e d I n d u c t i v e  
Switching Capability  
Figur
e
1
0. Maximum Continuous Drain  
Current vs
 
Case Temperature  
200  
100  
2000  
1000  
100  
10  
100
μ
s  
10  
1
1 ms  
10 ms  
THIS AREA IS  
100 ms  
LIMITED BY r  
DS(on)  
1 s  
SINGLE PULSE  
T

J

= MAX RATED  
SINGLE PULSE  

θ
JA

= 125

o

C/W  
0.1  
10 s  
DC  
R
R

θ
JA

= 125

o

C/W  

A

= 25

o

C  
T

A

= 25

o

C  
1
T
0.01  
0.5  
10

-4  

10

-3  

10

-2  

t, PULSE WIDTH (sec)  
10

-1  

1
10  
0.01  
0.1  
1
10  
100200  
100 1000  
V

DS

, DRAIN to SOURCE VOLTAGE (V)  
Figure 11.
 
Forward Bias Safe  
Operating Area  
Figur
e
1
2. Single Pulse
 
Maximum  
Power Dissipation  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
4

Typical Characteristics
T

J

= 25°C unless otherwise noted  
2
1
DUTY CYCLE-DESCENDING ORDER  
D = 0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.01  
t
1
t
2
SINGLE PULSE  
NOTES:  
DUTY FACTOR: D = t
 
/t  
0.001  
R

θ
JA

= 125

o

C/W  
1
2
PEAK T
 
= P  
J
x Z  
x R  
+ T  
DM  
θ
JA  
θ
JA
A  
(
Note 1b
)  
0.0001  
10

-4  

10

-3  

10

-2  

10

-1  

t, RECTANGULAR PULSE DURATION (sec)  
1
10  
100  
1000  
Figure 13.
 
Junction-to-Ambient Transient Thermal Response Curve  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
5

Typical Characteristics
(continued)  
TM  
SyncFET Schottky
 
body diode  
Characteristics  
Fairchild’s SyncFET

TM

process embeds a Schottky diode in  
parallel with PowerTrench MOSFET. This diode exhibits similar  
characteristics to a discrete external Schottky diode in parallel  
Schottky barrier diodes exhibit significant leakage at high tem-  
perature and high reverse voltage. This will increase the power  
in the device.  
with  
a MOSFET. Figure 14 shows the reverse recovery  
characteristic of the FDMS0310AS.  
0.01  
25  
20  
15  
T

J

= 125

o  

C
0.001  
0.0001  
T

J

= 100

o  

C
di/dt = 300 A/
μ
s  
10  
5
1E-5  
T

J

= 25

o  

C
0
-5  
0.000001  
0
50  
100  
150  
200  
0
5
10  
15  
20  
25  
TIME (ns)  
V

DS

, REVERSE VOLTAGE (V)  
Figure 15. SyncFET

TM

body diode reverse  
leakage versus
 
drain-source voltage  
Figure 14. FDMS0310AS SyncFET

TM

body  
diode reverse recovery characteristic  
©2010 Fairchild Semiconductor Corporation  
FDMS0310AS Rev.C2  
6

PQFN8 5X6, 1.27P  
CASE 483AE  
ISSUE A  
5.10  
3.91  
5.10  
PKG  
A
SEE  
DETAIL B  
1.27  
6.61  
C
L
B
8
7
6
5
8
5
0.77  
4.52  
3.75  
5.85  
5.65  
C
PKG  
6.15  
L
KEEP OUT  
AREA  
1.27  
1
4
1
2
3
4
TOP VIEW  
0.61  
1.27  
3.81  
LAND PATTERN  
RECOMMENDATION  
OPTIONAL DRAFT  
ANGLE MAY APPEAR  
ON FOUR SIDES  
SEE  
DETAIL C  
5.00  
4.80  
OF THE PACKAGE  
0.35  
0.15  
ꢀƒꢁꢂꢃƒ  
0.10 C  
0.30  
0.05  
0.05  
0.00  
SIDE VIEW  
ꢀƒꢁꢂꢃƒ  
8X  
0.08 C  
C
0.35  
0.15  
5.20  
4.80  
1.10  
0.90  
SEATING  
PLANE  
DETAIL C  
DETAIL B  
SCALE: 2:1  
3.81  
SCALE: 2:1  
1.27  
0.51  
(8X)  
0.31  
NOTES: UNLESS OTHERWISE SPECIFIED  
(0.34)  
A. PACKAGE
 
STANDARD REFERENCE:
 
JEDEC MO-240,  
ISSUE A, VAR. AA,.  
0.10  
C A B  
1
2
3
4
B. DIMENSIONS
 
DO NOT INCLUDE BURRS OR MOLD FLASH.  
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.  
C. ALL
 
DIMENSIONS ARE IN MILLIMETERS.  
0.76  
0.51  
(0.52)  
D. DIMENSIONING
 
AND TOLERANCING PER
 
ASME Y14.5M-2009.  
E. IT
 
IS RECOMMENDED TO HAVE NO TRACES OR  
VIAS WITHIN THE KEEP
 
OUT AREA.  
6.25  
5.90  
+0.30  
3.48  
-0.10  
(0.50)  
(0.30)  
(2X)  
8
7
6
5
ꢀꢄꢅꢅ“ꢀꢄꢂꢀ  
+0.10  
-0.15  
0.20  
(8X)  
3.96  
3.61  
BOTTOM VIEW  

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