onsemi-FDMS0348
| Part # | onsemi-FDMS0348 |
Download  | onsemi-FDMS0348 |
October 2014
FDMS0348
N-Channel PowerTrench
®
MOSFET
ꢀ
30V, 35A, 7.0m
:
Features
tm
General Description
Max r
DS(on)
= 7.0m
:ꢀ
at V
GS
= 10V, I
D
= 14A
Max r
DS(on)
= 11.0m
:
at V
GS
= 4.5V, I
D
= 11.5A
The FDMS0348 has been designed to minimize losses in power
conversion application.
Advancements in both silicon and
package technologies have been combined to offer the lowest
r
DS(on)
while maintaining excellent switching performance.
Advanced Package and Silicon combination for
low r
DS(on)
and high efficiency
Applications
MSL1 robust package design
RoHS Compliant
Low Side for Synchronous Buck to Power Core Processor
Secondary Side Synchronous Rectifier
Low Side Switch in POL DC/DC Converter
Oring FET/ Load Switch
Top
Bottom
Pin 1
S
D
D
D
D
5
6
7
8
4
3
2
1
G
S
S
S
S
S
G
D
D
D
D
Power 56
MOSFET Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
30
V
V
20
Drain Current
-Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
T
C
= 25°C
T
C
= 25°C
T
A
= 25°C
35
63
I
D
A
(Note 1a)
(Note 3)
14
-Pulsed
100
E
AS
Single Pulse Avalanche Energy
Power Dissipation
216
mJ
W
T
C
= 25°C
T
A
= 25°C
50
P
D
Power Dissipation
(Note 1a)
2.5
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
T
JC
R
T
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
2.5
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
12mm
Quantity
FDMS0348
FDMS0348
Power 56
13″
3000units
1
©2010 Fairchild Semiconductor Corporation
FDMS0348 Rev.C1
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain to Source Breakdown Voltage
I
D
= 250
P
A, V
GS
= 0V
30
V
‘
BV
DSS
ꢀꢀꢀ’
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
P
A, referenced to 25°C
V
DS
= 24V,
V
GS
= 0V
24
mV/°C
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
1
P
A
nA
V
GS
=
20V, V
DS
= 0V
100
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
P
A
1.0
1.8
3.0
V
ꢀ’
V
GS(th)
ꢀꢀꢀ’
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
P
A, referenced to 25°C
-5.7
mV/°C
V
GS
= 10V,
I
D
= 14A
5.5
8.5
8.2
72
7.0
11.0
10.5
r
DS(on)
Static Drain to Source On Resistance
Forward Transconductance
V
GS
= 4.5V,
I
D
= 11.5A
V
GS
= 10V,
I
D
= 14A, T
J
= 125°C
V
DD
= 10V,
I
D
= 14A
m
:
g
FS
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
1195
555
95
1590
740
145
4.0
pF
pF
pF
:
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
f = 1MHz
0.8
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
9
3
18
10
34
10
26
14
ns
ns
V
DD
= 15
V
,
I
D
= 14A,
V
GS
= 10V, R
GEN
= 6
:
Turn-Off Delay Time
Fall Time
21
2
ns
ns
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 0V to 10V
18
10
3.2
2.7
nC
nC
nC
nC
V
DD
= 15V,
I
D
= 14A
Q
g
V
GS
= 0V to 5V
Q
gs
Q
gd
Drain-Source Diode Characteristics
V
SD
t
rr
Source to Drain Diode
Forward Voltage
Reverse Recovery Time
V
GS
= 0V, I
S
= 14A
(Note 2)
0.8
27
15
1.2
44
27
V
ns
nC
I
F
= 14A, di/dt = 100A/
P
s
Q
rr
Reverse Recovery Charge
NOTES:
2
1. R
is determined with the device mounted on a 1in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
the user’s board design.
is guaranteed by design while R
is determined by
T
CA
T
JA
T
JC
a. 50°C/W
when mounted on a
2
b. 125°C/W when mounted on
a
minimum pad of 2 oz copper.
1in pad
of 2 oz copper.
2. Pulse Test: Pulse Width < 30
0
P
s, Duty cycle < 2.0%.
3. Starting T
= 25°C,
L = 3mH, I
= 12A, V
= 30V, V
= 10V.
GS
J
AS
DD
©2010 Fairchild Semiconductor Corporation
FDMS0348 Rev.C1
2
Typical Characteristics
T
J
= 25°C unless otherwise noted
100
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
PULSE DURATION = 80
P
s
DUTY CYCLE = 0.5%MAX
V
GS
= 3V
V
GS
= 4V
80
60
40
20
0
V
GS
= 10V
V
GS
= 4.5V
V
GS
= 3.5V
V
GS
= 4V
V
GS
= 3.5V
V
GS
= 3V
V
GS
= 4.5V
PULSE DURATION = 80
P
s
DUTY CYCLE = 0.5%MAX
V
GS
= 10V
0
1
2
3
4
0
20
40
60
80
100
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT(A)
Figure 1.
On-Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s ta n c e
vs Drain Current and Gate Voltage
1.8
24
I
D
= 14A
GS
= 10V
PULSE DURATION = 80
P
s
DUTY CYCLE = 0.5%MAX
I
D
= 14A
V
1.6
1.4
1.2
1.0
0.8
0.6
20
16
12
8
T
J
= 125
o
C
T
J
= 25
o
C
4
-75 -50 -25
0
25 50 75
100 125 150
2
4
6
8
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE
(
V
)
F i gu re 3 .
N orma li zed
On – Res is ta nc e
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
100
100
PULSE DURATION = 80
P
s
DUTY CYCLE = 0.5%MAX
V
GS
= 0V
80
60
40
20
0
10
1
V
DD
= 5V
T
J
= 25
o
C
T
J
= 150
o
C
0.1
T
J
= 150
o
C
0.01
0.001
T
J
= -55
o
C
T
J
= 25
o
C
T
J
= -55
o
C
1
2
3
4
5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2010 Fairchild Semiconductor Corporation
FDMS0348 Rev.C1
3
Typical Characteristics
T
J
= 25°C unless otherwise noted
10
2000
1000
C
iss
I
D
= 14A
8
V
DD
= 10V
V
DD
= 15V
C
oss
6
V
DD
= 20V
4
2
0
100
50
C
rss
f = 1MHz
= 0V
V
GS
0
4
8
12
16
20
0.1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
Q ,
GATE CHARGE(nC)
g
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s D r a i n
to Source Voltage
70
60
50
40
30
20
10
0
20
10
V
GS
= 10V
T
J
= 25
o
C
T
J
= 125
o
C
Limited by Package
R
T
JC
= 2.5
o
C/W
V
GS
= 4.5V
1
0.01
0.1
1
10
100
300
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE(ms)
Figure9. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs
Case Temperature
200
100
2000
1000
100
10
V
GS
= 10V
SINGLE PULSE
R
T
JA
= 125
o
C/W
T
A
= 25
o
C
100us
1ms
10
1
10ms
THIS AREA IS
100ms
LIMITED BY r
DS(on)
SINGLE PULSE
T
J
= MAX RATED
R
T
JA
= 125
o
C/W
1s
0.1
0.01
10s
DC
1
T
A
= 25
o
C
0.5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
10
2
10
3
0.01
0.1
1
10
100
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse
Maximum
Power Dissipation
©2010 Fairchild Semiconductor Corporation
FDMS0348 Rev.C1
4
Typical Characteristics
T
J
= 25°C unless otherwise noted
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
0.01
t
1
SINGLE PULSE
0.001
t
2
R
T
JA
= 125
o
C/W
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
J
x Z
x R
+ T
DM
T
JA
T
JA
A
0.0001
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t, RECTANGULAR PULSE DURATION (s)
Figure 13.
Transient Thermal Response Curve
©2010 Fairchild Semiconductor Corporation
FDMS0348 Rev.C1
5
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Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
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Formative / In Design
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Rev. I73
© Fairchild Semiconductor Corporation
