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September 2016
FDMS10C4D2N
N-Channel
Shielded Gate
PowerTrench
®
MOSFET
100 V, 124 A, 4.2 m
Ω
Features
General Description
Shielded Gate MOSFET
T
e
chnology
This N-Channel MV MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench
®
process that
incorporates Shielded Gate technology. This process has been
optimized to minimise on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
Max r
DS(on)
= 4.2 m
Ω
at V
GS
= 10 V, I
D
= 44 A
Max r
DS(on)
= 14 m
Ω
at V
GS
= 6 V, I
D
= 22 A
ADD
50% lower Qrr than other MOSFET suppliers
Lowers switching noise/EMI
MSL1 robust package design
100% UIL tested
Applications
Industrial Motor Drive
Industrial Power Supply
Industrial Automation
Battery Operated
T
o
ols
Battery Protection
Solar Inverters
RoHS Compliant
UPS and Energy Inverters
Energy Storage
Load Switch
Bottom
Top
Pin 1
S
S
D
D
D
D
S
S
G
S
S
G
Pin 1
D
D
D
D
Power 56
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Ratings
100
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
V
V
±20
T
C
= 25 °C
T
C
= 100 °C
T
A
= 25 °C
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
124
78
I
D
A
-Continuous
17
-Pulsed
510
E
AS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
337
mJ
W
T
C
= 25 °C
T
A
= 25 °C
125
P
D
(Note 1a)
2.5
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
θ
JC
R
θ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
1.0
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS10C4D2N
FDMS10C4D2N
Power 56
3000 units
©2016 Fairchild Semiconductor Corporation
FDMS10C4D2N Rev. 1.0
1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain to Source Breakdown Voltage
I
D
= 250
μ
A, V
GS
= 0 V
100
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
60
mV
/
°C
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 80 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
1
μ
A
100
nA
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
μ
A
2.0
3.1
-9
4.0
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
mV/°C
V
GS
= 10
V
,
I
D
= 44 A
3.3
5.3
5.7
116
4.2
14
r
DS(on)
g
FS
Static Drain to Source On Resistance
Forward Transconductance
V
GS
= 6 V, I
D
= 22 A
m
Ω
V
GS
= 10
V
,
I
D
= 44 A, T
J
= 125 °C
V
DS
= 10
V
,
I
D
= 44 A
9.0
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
2945
1730
20
4500
2600
50
pF
pF
pF
Ω
V
DS
= 50 V, V
GS
= 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
1.3
2.6
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
17
9
31
18
40
12
65
43
ns
ns
V
DD
= 50
V
, I
D
= 44 A,
V
GS
= 10 V, R
GEN
= 6
Ω
Turn-Off Delay Time
Fall Time
25
6
ns
ns
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 0 V to 10 V
V
GS
= 0 V to 6 V
42
27
13
9.3
nC
nC
nC
nC
Q
g
V
DD
= 50 V,
D
= 44 A
I
Q
gs
Q
gd
Drain-Source Diode Characteristics
V
GS
= 0 V, I
S
= 2.1 A
(Note 2)
(Note 2)
0.7
0.8
32
1.2
1.3
52
V
SD
Source to Drain Diode
Forward Voltage
V
V
GS
= 0 V, I
S
= 44 A
t
rr
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
ns
nC
ns
I
F
= 20 A, di/dt = 300 A/
μ
s
I
F
= 20 A, di/dt = 1000 A/
μ
s
Q
rr
t
rr
57
92
25
40
Q
rr
158
253
nC
Notes
:
2
1. R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is determined by
the user’s board design.
θ
JA
θ
CA
a)
50 °C/W when mounted
on a
1 in
pad of
2 oz
copper
b) 125
°C/W when mounted on a
minimum pad of 2 oz copper.
2
2. Pulse Test: Pulse Width < 30
0
μ
s, Duty cycle < 2.0%.
3.
E of
337 mJ is based on starting T
= 25
°
C; N-ch: L = 3 mH, I
= 15 A, V
= 100 V, V
=10 V. 100% test at L = 0.1 mH, I
= 49 A.
AS
J
AS
DD
GS
AS
4.
Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2016 Fairchild Semiconductor Corporation
FDMS10C4D2N Rev. 1.0
2
Typical Characteristics
T
J
= 25 °C unless otherwise noted
300
6
4
2
0
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 5 V
250
200
150
100
50
V
GS
= 8 V
V
GS
= 6.5 V
V
GS
= 6 V
V
GS
= 6.5 V
V
GS
= 6 V
V
GS
= 8 V
V
GS
= 5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
100
0
0
1
2
3
4
0
50
150
200
250
300
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On-Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s ta n c e
vs Drain Current and Gate Voltage
2.0
30
PULSE DURATION = 80
μ
s
I
D
= 44 A
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
25
20
15
10
5
I
D
= 44 A
T
J
= 125
o
C
T
J
= 25
o
C
0
-75 -50 -25
0
25 50 75
100 125 150
4
5
6
7
8
9
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
F i gu re 3 .
N orma li zed
On – Res is ta nc e
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
300
300
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
100
250
200
150
100
50
V
DS
= 5 V
10
1
T
J
= 150
o
C
T
J
= 25
o
C
0.1
T
J
= 150
o
C
T
J
= 25
o
C
0.01
0.001
T
J
= -55
o
C
T
J
= -55
o
C
0
2
4
6
8
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2016 Fairchild Semiconductor Corporation
FDMS10C4D2N Rev. 1.0
3
Typical Characteristics
T
J
= 25 °C unless otherwise noted
10
10000
1000
100
10
I
D
= 44 A
C
iss
V
DD
= 50 V
8
C
oss
V
DD
= 25 V
6
V
DD
= 75 V
4
C
rss
f = 1 MHz
GS
= 0 V
2
0
V
1
0.1
0
10
20
30
40
50
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s D r a i n
to Source Voltage
1
0
0
10
1
140
120
100
80
R
θ
JC
= 1.0
o
C/W
V
GS
= 10 V
T
J
= 25
o
C
T
J
= 100
o
C
60
V
GS
= 6 V
40
T
J
= 1
2
5
o
C
20
0
25
0.
0
1
0
.
1
t
1
10
1
0
0
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
AV
, TIME
I
N
A
VALANCHE (ms)
Figur
e
9. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs Case Temperature
1000
100
10
20000
SINGLE PULSE
R
θ
JC
= 1.0
o
C/W
C
= 25
o
C
10000
1000
100
T
10
μ
s
THIS AREA IS
LIMITED BY r
DS(on)
100
μ
s
SINGLE PULSE
T
J
= MAX RATED
1 ms
1
R
θ
JC
= 1.0
o
C/W
10 ms
DC
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
0.1
0.1
10
10
-5
10
-4
10
-3
t, PULSE WIDTH (sec)
10
-2
10
-1
1
10
100
500
1
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
©2016 Fairchild Semiconductor Corporation
FDMS10C4D2N Rev. 1.0
4
Typical Characteristics
T
J
= 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
P
DM
0.05
0.02
0.01
0.1
t
1
t
2
0.01
0.001
NOTES:
(t) = r(t) x R
Z
θ
JC
θ
JC
SINGLE PULSE
o
R
= 1.0
C/W
θ
JC
Peak T
= P
x Z
(t) + T
J
DM
θ
JC C
Duty Cycle, D = t
/ t
1
2
10
-5
10
-4
10
-3
t, RECTANGULAR PULSE DURATION (sec)
10
-2
10
-1
1
Figure 13.
Junction-to-Case Transient Thermal Response Curve
©2016 Fairchild Semiconductor Corporation
FDMS10C4D2N Rev. 1.0
5
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE
STANDARD REFERENCE:
JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS
DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL
DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-2009.
E. IT
IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP
OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
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. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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