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August 2011
FDMS3600S
PowerTrench
®
Power Stage
25 V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFE
T
s
i
n a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Max r
DS(on)
= 5.6 m
Ω
at V
GS
= 10 V, I
D
= 15 A
Max r
DS(on)
= 8.1 m
Ω
at V
GS
= 4.5 V, I
D
= 14 A
Q2: N-Channel
Max r
DS(on)
= 1.6 m
Ω
at V
GS
= 10 V, I
D
= 30 A
Max r
DS(on)
= 2.4 m
Ω
at V
GS
= 4.5 V, I
D
= 25 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
Computing
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Communications
General Purpose Point of Load
Notebook VCORE
Server
RoHS Compliant
G1
Pin 1
D1
D1
D1
Q2
D1
S2
D1
5
6
7
8
4
3
2
1
PHASE
(S1/D2)
PHASE
D1
D1
S2
S2
G2
G2
S2
S2
G1
Q1
S2
Bottom
Top
Power 56
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Q1
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
25
±20
30
25
±20
V
V
(Note 3)
T
C
= 25 °C
T
C
= 25 °C
T
A
= 25 °C
Drain Current
-Continuous (Package
limited)
-Continuous (Silicon
limited)
-Continuous
40
65
15
1a
155
30
1b
100
200
5
2.5
1b
1.0
1d
I
D
A
-Pulsed
40
E
AS
Single Pulse Avalanche Energy
50
4
2.2
1a
1.0
1c
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction
T
e
mperature Range
T
A
= 25 °C
T
A
= 25 °C
P
D
T
J
, T
STG
-55 to +150
°C
Thermal Characteristics
R
θ
JA
R
θ
JA
R
θ
JC
Thermal Resistance, Junction to Ambient
57
1a
125
1c
3.5
50
1b
120
1d
2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
22OA
N9OC
FDMS3600S
Power 56
12 mm
3000 units
1
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
I
I
D
= 250
μ
A, V
GS
= 0 V
D
= 1 mA, V
GS
= 0 V
Q1
Q2
25
25
BV
DSS
Drain to Source Breakdown Voltage
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= 10 mA, referenced to 25 °C
Q1
Q2
20
18
mV/°C
I
Q1
Q2
1
500
μ
A
μ
A
I
DSS
I
GSS
Zero Gate Voltage Drain Current
V
DS
= 20 V, V
GS
= 0 V
Gate to Source Leakage Current,
Forward
Q1
Q2
100
100
nA
nA
V
GS
= 20 V, V
DS
= 0 V
On Characteristics
V
V
GS
= V
DS
, I
D
= 250
μ
A
GS
= V
DS
, I
D
= 1 mA
Q1
Q2
1.1
1
1.8
1.5
2.7
3
V
GS(th)
Gate to Source Threshold Voltage
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= 10 mA, referenced to 25 °C
V
GS
= 10 V,
I
D
= 15 A
Q1
Q2
-6
-5
mV/°C
I
4.3
6.2
5.9
5.6
8.1
8.7
V
V
GS
= 4.5 V,
I
D
= 14 A
GS
= 10 V,
I
D
= 15 A , T
J
= 125 °C
Q1
Q2
r
DS(on)
Drain to Source On Resistance
m
Ω
V
V
V
GS
= 10 V,
I
D
= 30 A
GS
= 4.5 V,
I
D
= 25 A
GS
= 10 V,
I
D
= 30 A , T
J
= 125 °C
1.3
1.7
1.8
1.6
2.4
2.7
V
V
DS
= 5 V,
I
D
= 15 A
DS
= 5 V,
I
D
= 30 A
Q1
Q2
67
171
g
FS
Forward Transconductance
S
Dynamic Characteristics
Q1
Q2
1264
4042
1680
5375
Q1:
C
iss
C
oss
C
rss
R
g
Input Capacitance
pF
pF
pF
Ω
V
DS
= 13 V, V
GS
= 0
V
, f = 1
M
HZ
Q1
Q2
340
1207
450
1605
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
V
DS
= 13 V, V
GS
= 0
V
, f = 1
M
HZ
Q1
Q2
58
148
90
220
Q1
Q2
0.2
0.2
0.6
0.9
2
3
Switching Characteristics
Q1
Q2
7.9
13
16
23
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2
5.3
10
11
V
DD
= 13 V, I
D
= 15 A, R
GEN
= 6
Ω
Q1
Q2
19
38
34
60
Q2:
Turn-Off Delay Time
Fall Time
ns
V
DD
= 13 V, I
D
= 30 A, R
GEN
= 6
Ω
Q1
Q2
1.8
3.9
10
10
ns
Q1
Q2
19
59
27
82
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
GS
= 0
V to 10 V
Q1
nC
nC
nC
nC
V
DD
= 13
V
,
Q1
Q2
9
27
13
38
Q
g
V
GS
= 0
V to 4.5 V
I
D
= 15 A
Q1
Q2
3.9
11
Q2
V
DD
= 13
V
,
Q
gs
Q
gd
Q1
Q2
2.4
5.8
I
D
= 30 A
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
2
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS
= 0 V, I
S
= 15 A
GS
= 0 V, I
S
= 30 A
(Note 2)
Q1
(Note 2)
Q2
0.8
0.8
1.2
1.2
V
SD
t
rr
Source to Drain Diode
Forward Voltage
Reverse Recovery Time
V
Q1
Q2
21
32
34
51
Q1
ns
nC
I
F
= 15 A, di/dt = 100 A/
μ
s
Q2
I
F
= 30 A, di/dt = 300 A/
μ
s
Q1
Q2
6.6
36
13
58
Q
rr
Reverse Recovery Charge
Notes:
2
1:
R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined
θ
CA
θ
JA
θ
JC
by the user’s board design.
b. 50 °C/W when mounted on
a 1 in
pad of
2 oz
copper
a. 57 °C/W when mounted on
a 1 in
pad of
2 oz
copper
2
2
c. 125 °C/W when mounted on
a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on
a
minimum pad of 2 oz copper
2:
Pulse
T
e
st: Pulse Width < 300
μ
s, Duty cycle < 2.0%.
3:
As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
o
4:
E of
50 mJ is based on starting T
= 25
C; N-ch: L = 1 mH, I
= 10 A, V
= 23 V, V
= 10 V. 100% test at L=0.3
mH, I
= 15 A.
AS
J
AS
DD
GS
AS
o
5:
E of
200 mJ is based on starting T
= 25
C; N-ch: L = 1 mH, I
= 20 A, V
= 23 V, V
= 10 V. 100% test at L=0.3
mH, I
= 30 A.
AS
J
AS
DD
GS
AS
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
3
Typical Characteristics (Q1 N-Channel)
T
J
= 25 °C unless otherwise noted
40
30
20
10
0
6
5
4
3
2
1
0
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
V
GS
= 4.5
V
V
GS
= 3 V
V
GS
= 4
V
V
GS
= 3.5 V
V
GS
= 3.5 V
V
GS
= 4.5 V
V
GS
= 4 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
= 3 V
GS
V
GS
= 10 V
0
10
20
30
40
0.0
0.2
0.4
0.6
0.8
1.0
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
F i g u r e 2 .
No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
1.6
25
I
D
= 15 A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
20
V
GS
= 10 V
1.4
1.2
1.0
0.8
0.6
I
D
= 15 A
15
T
J
= 125
o
C
10
5
T
J
= 25
o
C
0
-75 -50 -25
0
25 50 75
100 125 150
2
4
6
8
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
40
40
V
GS
= 0 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
10
30
20
10
0
T
J
= 150
o
C
T
J
= 25
o
C
V
DS
= 5 V
1
T
J
= 150
o
C
T
J
= -55
o
C
0.1
T
J
= 25
o
C
0.01
0.001
T
J
= -55
o
C
1
2
3
4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
4
Typical Characteristics (Q1 N-Channel)
T
J
= 25 °C unless otherwise noted
10
8
2000
1000
V
DD
= 10 V
I
D
= 15 A
C
iss
V
DD
= 13 V
C
oss
6
V
DD
=
16 V
100
4
C
rss
2
f = 1 MHz
GS
= 0 V
V
0
10
0
5
10
Q
g
, GATE CHARGE (nC)
15
20
0.1
1
10
25
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s D r a i n
to Source Voltage
20
80
60
40
20
0
R
θ
JC
= 3.5
o
C/W
10
V
GS
= 10 V
T
J
= 25
o
C
T
J
= 100
o
C
V
GS
= 4.5 V
T
J
=
125
o
C
Limited by Package
1
0.01
0.1
1
10
100
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figur
e
9. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figure 10.
Maximum Continuous Drain
Current vs
Case Temperature
100
10
1000
SINGLE PULSE
R
θ
JA
= 125
o
C/W
100
μ
s
T
A
= 25
o
C
100
10
1 ms
10 ms
1
THIS AREA IS
100 ms
LIMITED BY r
DS
(
on
)
1s
10s
SINGLE PULSE
T
J
= MAX RATED
0.1
R
θ
JA
= 125
o
C/W
A
= 25
o
C
DC
1
T
0.01
0.01
0.5
10
-4
10
-3
10
-2
t, PULSE WIDTH (sec)
10
-1
1
10
100 1000
0.1
1
10
100
200
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
5
Typical Characteristics (Q1 N-Channel)
T
J
= 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.01
0.1
P
DM
0.05
0.02
0.01
t
1
t
2
SINGLE PULSE
θ
JA
= 125
o
C/W
NOTES:
DUTY FACTOR: D = t /t
R
1
2
PEAK T
= P
J
x Z
x R
+ T
(
Note 1c
)
DM
θ
JA
θ
JA
A
0.001
10
-4
10
-3
10
-2
10
-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13.
Junction-to-Ambient Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
6
Typical Characteristics (Q2 N-Channel)
T
J
= 25
o
C unlenss otherwise noted
100
80
60
40
20
0
4
3
2
1
0
V
GS
= 10 V
V
GS
= 4.5
V
V
GS
= 4
V
V
GS
= 3 V
V
GS
= 4.5 V
V
GS
= 4 V
V
GS
= 3.5 V
V
= 3.5 V
GS
V
GS
= 3 V
V
GS
= 10 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
0
20
40
60
80
100
0.0
0.2
0.4
0.6
0.8
1.0
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 14. On-Region Characteristics
Figure 15. Normalized on-Resistance vs Drain
Current and Gate
Voltage
1.6
8
I
D
= 30 A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
1.4
1.2
1.0
0.8
6
I
D
= 30 A
4
T
J
= 125
o
C
2
T
J
= 25
o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75
100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
100
200
100
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
80
60
40
20
0
V
DS
= 5 V
T
J
= 125
o
C
T
J
= 125
o
C
10
1
T
J
= 25
o
C
T
J
= 25
o
C
T
J
= -55
o
C
T
J
= -55
o
C
0.1
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
7
Typical Characteristics (Q2 N-Channel)
T
J
= 25
o
C unless otherwise noted
10
10000
1000
100
I
D
= 30 A
C
iss
8
V
DD
= 10 V
C
oss
6
V
DD
= 13 V
4
C
rss
V
DD
=
16 V
2
f = 1 MHz
V
GS
= 0 V
0
10
25
0.1
1
10
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
g
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
40
200
150
100
50
R
θ
JC
= 2
o
C/W
T
J
= 25
o
C
V
GS
= 10 V
10
T
J
= 100
o
C
V
GS
= 4.5 V
T
J
= 125
o
C
Limited by Package
1
0.01
0
0.1
1
10
100 300
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figure 22. Unclamped
Inductive
Switching Capability
Figure 23.Maximun Continuous Drain
Current vs Case Temperature
200
10000
100
SINGLE PULSE
R
θ
JA
= 120
o
C/W
T
A
= 25
o
C
1000
100
10
1 ms
10
10 ms
THIS AREA IS
LIMITED BY r
100 ms
1
DS
(
on
)
1s
SINGLE PULSE
T
J
= MAX RATED
R
θ
JA
= 120
o
C/W
T
A
= 25
o
C
10s
DC
0.1
0.01
1
10
-4
10
-3
10
-2
t, PULSE WIDTH (sec)
10
-1
1
10
100 1000
0.01
0.1
1
10
100200
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
Figure 25. Single
Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
8
Typical Characteristics (Q2 N-Channel)
T
J
= 25
o
C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1
P
DM
0.05
0.02
0.01
0.01
0.001
t
1
t
2
SINGLE PULSE
R
θ
JA
= 120
o
C/W
(Note 1d)
NOTES:
DUTY FACTOR: D = t
/t
1
2
PEAK T
= P
J
x Z
x R
+ T
DM
θ
JA
θ
JA
A
0.0001
10
-4
10
-3
10
-2
10
-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure26. Junction-to-Ambient
Transient Thermal Response Curve
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
9
Typical Characteristics
(continued)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with
a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3600S.
10
-2
35
30
25
20
15
10
5
T
J
= 125
o
C
10
-3
10
-4
10
-5
10
-6
T
J
= 100
o
C
didt = 300 A/
μ
s
T
J
= 25
o
C
0
-5
0
5
10
15
20
25
0
50
100
150
200
250
300
V
DS
, REVERSE VOLTAGE (V)
TIME (ns)
Figure 27. FDMS3600S SyncFET body
diode reverse recovery characteristic
Figure 28. SyncFET body diode reverse
leakage versus
drain-source voltage
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
10
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29.
Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
11
Figure 30.
Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31.
Recommended PCB Layout
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
12
Following is a guideline, not a requirement which the PCB designer should consider:
1. Input
ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2.
Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench
®
Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2011 Fairchild Semiconductor Corporation
FDMS3600S Rev.C3
13
4.00
C
L
5.10
4.90
0.10 C
A
1.27 TYP
0.65 TYP
(2X)
PKG
B
C
L
8
5
8
6
7
5
0.63
2.15
2.52
1.60
KEEP OUT AREA
6.25
5.90
C
PKG
C
L
0.00
L
4.16
1.21
2.13
2.31
3.15
1
4
0.10 C
(2X)
2
4
1
3
PIN # 1
INDICATOR
0.63
0.59
TOP VIEW
3.18
5.10
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.10
0.05
C A B
C
0.10 C
3.16
2.80
0.65
0.38
0.70
0.36
8X
0.45
0.25
(6X)
0.08 C
1.34
1.12
C
0.05
0.00
1
2
3
0.35
0.15
4
1.10
0.90
SEATING
PLANE
0.66±.05
(SCALE: 2X)
2.25
2.05
4.08
3.70
1.02
0.82
0.65
0.38
8
7
6
5
0.44
0.24
0.61
0.31
(8X)
1.27
3.81
BOTTOM VIEW
5.10
4.90
0.10 C
(2X)
SEE
0.35
0.15
PKG
DETAIL B
C
L
5
8
0.28
0.08
10°
6.25
5.90
5.90
5.70
PKG
C
L
(SCALE: 2X)
0.10 C
1
4
(2X)
0.41
0.21
(8X)
TOP VIEW
5.00
4.80
SEE
0.10 C
0.08 C
DETAIL C
0.35
0.15
8X
C
SIDE VIEW
SEATING
PLANE
1.10
0.90
(SCALE: 2X)
0.10
0.05
C A B
3.16
2.80
0.70
0.36
0.65
0.38
C
0.45
0.25
(6X)
1
2
3
1.34
1.12
4
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
0.66±.05
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL
DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS
DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
2.25
2.05
4.08
3.70
D) DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT
IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING
FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
1.02
0.82
0.65
0.38
6
8
7
5
0.61
0.44
0.24
(8X)
0.31
1.27
3.81
BOTTOM VIEW
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