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July 2012
FDMS3620S
PowerTrench
®
PowerStage
25V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFE
T
s
i
n a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Max r
DS(on)
= 4.7 m
Ω
at V
GS
= 10 V, I
D
= 17.5 A
Max r
DS(on)
= 5.5 m
Ω
at V
GS
= 4.5 V, I
D
= 16 A
Q2: N-Channel
Max r
DS(on)
= 1.0 m
Ω
at V
GS
= 10 V, I
D
= 38 A
Max r
DS(on)
= 1.2 m
Ω
at V
GS
= 4.5 V, I
D
= 35 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Computing
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Communications
General Purpose Point of Load
Notebook VCORE
RoHS Compliant
G1
Pin 1
D1
D1
D1
Q2
D1
S2
D1
5
6
7
8
4
3
2
1
Pin 1
PHASE
(S1/D2)
PHASE
D1
D1
S2
S2
G2
G2
S2
S2
S2
G1
Q1
Bottom
Top
Power 56
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Q1
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
25
±12
30
25
±12
49
V
V
(Note 4)
T
C
= 25 °C
T
C
= 25 °C
T
A
= 25 °C
Drain Current
-Continuous (Package
limited)
-Continuous (Silicon
limited)
-Continuous
76
17.5
1a
211
I
D
A
38
1b
150
135
2.5
1b
1.0
1d
-Pulsed
70
E
AS
Single Pulse Avalanche Energy
(Note 3)
T
A
= 25 °C
T
A
= 25 °C
29
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction
T
e
mperature Range
2.2
1a
1.0
1c
P
D
T
J
, T
STG
-55 to +150
°C
Thermal Characteristics
R
θ
JA
R
θ
JA
R
θ
JC
Thermal Resistance, Junction to Ambient
57
1a
125
1c
3.0
50
1b
120
1d
1.7
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
08OD
06OD
FDMS3620S
Power 56
12 mm
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
I
I
D
= 250
μ
A, V
GS
= 0 V
D
= 1 mA, V
GS
= 0 V
Q1
Q2
25
25
BV
DSS
Drain to Source Breakdown Voltage
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= 10 mA, referenced to 25 °C
Q1
Q2
12
16
mV/°C
I
Q1
Q2
1
500
μ
A
μ
A
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 20 V, V
GS
= 0 V
V
GS
= 12/-8 V, V
DS
= 0 V
Q1
Q2
±100
±100
nA
nA
On Characteristics
V
V
GS
= V
DS
, I
D
= 250
μ
A
GS
= V
DS
, I
D
= 1 mA
Q1
Q2
0.8
1.1
1.2
1.3
2.0
2.2
V
GS(th)
Gate to Source Threshold Voltage
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
D
= 10 mA, referenced to 25 °C
V
GS
= 10 V,
I
D
= 17.5 A
Q1
Q2
-4
-4
mV/°C
I
3.8
4.4
5.4
4.7
5.5
7.0
V
V
GS
= 4.5 V,
I
D
= 16 A
GS
= 10
V
,
I
D
= 17.5 A,T
J
=125 °C
Q1
Q2
r
DS(on)
Drain to Source On Resistance
m
Ω
V
V
V
GS
= 10 V,
I
D
= 38 A
GS
= 4.5 V,
I
D
= 35 A
GS
= 10 V, I
D
=38 A ,T
J
=125 °C
0.8
0.9
1.1
1.0
1.2
1.5
V
V
DS
= 5 V,
I
D
= 17.5 A
DS
= 5 V,
I
D
= 38 A
Q1
Q2
100
271
g
FS
Forward Transconductance
S
Dynamic Characteristics
Q1
Q2
1570
6861
Q1:
C
iss
C
oss
C
rss
R
g
Input Capacitance
pF
pF
pF
Ω
V
DS
= 13 V, V
GS
= 0
V
, f = 1
M
HZ
Q1
Q2
448
1828
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
V
DS
= 13 V, V
GS
= 0
V
, f = 1
M
HZ
Q1
Q2
61
232
Q1
Q2
0.1
0.1
0.4
0.6
3.3
3.5
Switching Characteristics
Q1
Q2
7
14
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2
7
V
DD
= 13
V
,
I
D
= 17.5 A, R
GEN
= 6
Ω
Q1
Q2
23
41
Q2:
Turn-Off Delay Time
Fall Time
ns
V
DD
= 13 V, I
D
= 38 A, R
GEN
= 6
Ω
Q1
Q2
2
5
ns
Q1
Q2
26
106
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
GS
= 0
V to 10 V
Q1
nC
nC
nC
nC
V
DD
= 13
V
,
Q1
Q2
12
50
Q
g
V
GS
= 0
V to 4.5 V
I
D
= 17.5 A
Q1
Q2
3.3
12.9
Q2
V
DD
= 13
V
,
Q
gs
Q
gd
Q1
Q2
2.7
12
I
D
= 38 A
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
2
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS
= 0 V, I
S
= 17.5 A
GS
= 0 V, I
S
= 38
A
(Note 2)
Q1
(Note 2)
Q2
0.8
0.8
1.2
1.2
V
SD
t
rr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
Q1
Q2
23
38
Q1
ns
nC
I
F
= 17.5 A, di/dt = 100 A/
μ
s
Q2
I
F
= 38 A, di/dt = 300 A/
μ
s
Q1
Q2
9
54
Q
rr
Reverse Recovery Charge
Notes:
2
1.R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined by
θ
JA
θ
JC
θ
CA
the user’s board design.
c. 50 °C/W when mounted on
a 1 in
pad of
2 oz
copper
a. 57 °C/W when mounted on
a 1 in
pad of
2 oz
copper
2
2
b. 125 °C/W when mounted on
a
minimum pad of 2 oz copper
d. 120 °C/W when mounted on
a
minimum pad of 2 oz copper
2 Pulse Test: Pulse Width < 300
μ
s, Duty cycle < 2.0%.
o
3. Q1 :E
of 29
mJ is based on starting T
= 25
C; N-ch: L = 0.3
mH, I
= 14
A, V
= 23 V, V
= 10 V. 100% test at L= 0.1 mH, I
= 20 A.
AS
J
AS
DD
GS
AS
o
Q2: E
of 135 mJ is based on starting T
= 25
C; N-ch: L = 0.3 mH, I
= 30 A, V
= 23 V, V
= 10 V. 100% test at L=
0.1 mH, I
= 44 A.
AS
J
AS
DD
GS
AS
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only.
No continuous rating is implied.
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
3
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
70
60
50
40
30
20
10
0
3.0
2.5
2.0
1.5
1.0
0.5
V
GS
= 10 V
V
GS
= 4.5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 2.5 V
V
GS
= 3.5 V
V
GS
= 3 V
V
GS
= 3 V
V
GS
= 2.5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 4.5 V
V
GS
= 10 V
V
GS
= 3.5 V
0.0
0.3
0.6
0.9
1.2
1.5
0
10
20
30
40
50
60
70
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s t a n c e
vs Drain Current and Gate Voltage
1.8
1.6
1.4
1.2
1.0
0.8
0.6
20
16
12
8
I
D
= 17.5 A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 17.5 A
V
GS
= 10 V
T
J
= 125
o
C
4
T
J
= 25
o
C
0
-75 -50 -25
0
25 50 75
100 125 150
2
3
4
5
6
7
8
9
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
70
70
PULSE DURATION = 80
μ
s
V
GS
= 0 V
DUTY CYCLE = 0.5% MAX
60
50
40
30
20
10
0
10
1
V
DS
= 5 V
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= 150
o
C
0.1
T
J
= 25
o
C
T
J
= -55
o
C
T
J
= -55
o
C
0.01
0.001
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
4
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
10
8
2000
1000
I
D
= 17.5 A
C
iss
V
DD
= 10 V
V
DD
=
15 V
V
DD
= 13 V
C
oss
6
100
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
0
10
0.1
1
10
30
0
4
8
12
16
20
24
28
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q ,
GATE CHARGE (nC)
g
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s D r a i n
to Source Voltage
30
80
70
60
50
40
30
20
10
0
V
GS
= 10 V
10
T
J
= 25
o
C
T
J
= 100
o
C
V
GS
= 4.5 V
T
J
= 125
o
C
Limited by Package
R
θ
JC
= 3.0
o
C/W
1
0.001
0.01
0.1
1
10
50
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figur
e
9
. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs
Case Temperature
100
10
1000
SINGLE PULSE
θ
JA
= 125
o
C/W
R
100
μ
s
100
10
1 ms
10 ms
1
THIS AREA IS
LIMITED BY r
DS
(
on
)
100 ms
SINGLE PULSE
T
J
= MAX RATED
1s
0.1
10s
DC
R
θ
JA
= 125
o
C/W
A
= 25
o
C
1
T
0.01
0.5
10
-4
10
-3
10
-2
t, PULSE WIDTH (sec)
10
-1
1
10
0.01
0.1
1
10
100
100 1000
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse
Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
5
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.1
0.01
0.02
0.01
P
DM
t
1
SINGLE PULSE
θ
JA
= 125
o
C/W
t
2
NOTES:
DUTY FACTOR: D = t /t
R
1
2
(Note 1b)
PEAK T
= P
J
x Z
x R
+ T
θ
JA
A
DM
θ
JA
0.001
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 13.
Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
6
Typical Characteristics (Q2 N-Channel)
T
J
= 25 °C unless otherwise noted
150
120
90
60
30
0
6
5
4
3
2
1
0
V
GS
= 10 V
V
GS
= 4.5 V
V
GS
= 3.5 V
V
GS
= 3 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 2.5 V
V
GS
= 2.5 V
V
GS
= 3 V
V
GS
= 3.5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
120 150
V
GS
= 4.5 V
60
0
30
90
0
0.3
0.6
0.9
I
D
,
DRAIN CURRENT (A)
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
Figure 14.
On-Region Characteristics
Figure 15. Normalized on-Resistance vs Drain
Current and Gate
Voltage
1.6
5
I
D
= 38 A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
1.4
1.2
1.0
0.8
0.6
4
I
D
= 38 A
3
2
T
J
= 125
o
C
1
0
T
J
= 25
o
C
2
4
6
8
10
-75 -50 -25
0
25 50 75
100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
150
200
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
100
10
1
120
90
60
30
0
V
DS
= 5 V
T
J
= 150
o
C
T
J
= 150
o
C
T
J
= 25
o
C
T
J
= 25
o
C
T
J
= -55
o
C
T
J
= -55
o
C
1.0
1.5
2.0
2.5
3.0
0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
7
Typical Characteristics (Q2 N-Channel)
T
J
= 25°C unless otherwise noted
10
8
10000
1000
100
I
D
= 38 A
C
iss
C
oss
6
V
DD
= 13 V
V
DD
= 15 V
V
DD
= 10 V
4
C
rss
2
f = 1 MHz
= 0 V
V
GS
10
0.1
0
0
20
40
60
80
100
120
1
10
30
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
210
180
150
120
90
100
V
GS
= 10 V
T
J
= 25
o
C
V
GS
= 4.5 V
T
J
= 100
o
C
10
60
30
T
J
= 125
o
C
R
θ
JC
= 1.7
o
C/W
0
25
1
0.001
0.01
0.1
1
10
100
1000
50
75
100
125
150
T
C
, CASE
TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figure 22. Unclamped Inductive
Switching Capability
Figure 23. Maximum Continuous Drain
Current vs
Case Temperature
1000
100
10
10000
SINGLE PULSE
1000
100 us
R
θ
JA
= 120
o
C/W
T
A
= 25
o
C
100
10
1
1 ms
THIS AREA IS
LIMITED BY r
DS(on)
10 ms
100 ms
1 s
1
SINGLE PULSE
T
J
= MAX RATED
0.1
0.01
10 s
DC
R
θ
JA
= 120
o
C/W
A
= 25
o
C
T
0.1
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
1
10
0.01
0.1
1
10
100
100 1000
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
Figure 25. Single Pulse Maximum Power
Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
8
Typical Characteristics (Q2 N-Channel)
T
J
= 25 °C unless otherwise noted
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
P
DM
0.01
t
1
t
2
SINGLE PULSE
R
θ
JA
= 120
o
C/W
NOTES:
DUTY FACTOR: D = t /t
0.001
0.0001
1
2
PEAK T
= P
J
x Z
x R
+ T
θ
JA
A
DM
θ
JA
Note 1d
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (s)
1
10
100
1000
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
9
Typical Characteristics (Q2 N-Channel)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with
a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3620S.
10
-2
45
40
35
30
25
20
15
10
5
T
J
= 125
o
C
10
-3
10
-4
10
-5
10
-6
T
J
= 100
o
C
di/dt = 300 A/
μ
s
T
J
= 25
o
C
0
-5
0
5
10
15
20
25
0
50
100
150
200
250
300
350
TIME (ns)
V
DS
, REVERSE VOLTAGE (V)
Figure 28. SyncFET body diode reverse
leakage versus
drain-source voltage
Figure 27. FDMS3620S SyncFET body
diode reverse recovery characteristic
©2012 Fairchild Semiconductor Corporation
FDMS3620S Rev.C1
10
4.00
C
L
5.10
4.90
0.10 C
A
1.27 TYP
0.65 TYP
(2X)
PKG
B
C
L
8
5
8
6
7
5
0.63
2.15
2.52
1.60
KEEP OUT AREA
6.25
5.90
C
PKG
C
L
0.00
L
4.16
1.21
2.13
2.31
3.15
1
4
0.10 C
(2X)
2
4
1
3
PIN # 1
INDICATOR
0.63
0.59
TOP VIEW
3.18
5.10
SEE
DETAIL A
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.10
0.05
C A B
C
0.10 C
3.16
2.80
0.65
0.38
0.70
0.36
8X
0.45
0.25
(6X)
0.08 C
1.34
1.12
C
0.05
0.00
1
2
3
0.35
0.15
4
1.10
0.90
SEATING
PLANE
0.66±.05
(SCALE: 2X)
2.25
2.05
4.08
3.70
1.02
0.82
0.65
0.38
8
7
6
5
0.44
0.24
0.61
0.31
(8X)
1.27
3.81
BOTTOM VIEW
5.10
4.90
0.10 C
(2X)
SEE
0.35
0.15
PKG
DETAIL B
C
L
5
8
0.28
0.08
10°
6.25
5.90
5.90
5.70
PKG
C
L
(SCALE: 2X)
0.10 C
1
4
(2X)
0.41
0.21
(8X)
TOP VIEW
5.00
4.80
SEE
0.10 C
0.08 C
DETAIL C
0.35
0.15
8X
C
SIDE VIEW
SEATING
PLANE
1.10
0.90
(SCALE: 2X)
0.10
0.05
C A B
3.16
2.80
0.70
0.36
0.65
0.38
C
0.45
0.25
(6X)
1
2
3
1.34
1.12
4
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
0.66±.05
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL
DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS
DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
2.25
2.05
4.08
3.70
D) DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT
IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING
FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
1.02
0.82
0.65
0.38
6
8
7
5
0.61
0.44
0.24
(8X)
0.31
1.27
3.81
BOTTOM VIEW
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