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May 2014
FDMS7700S
Dual N-Channel PowerTrench
®
MOSFET
N-Channel: 30 V, 30 A, 7.5 m
Ω
N-Channel: 30 V, 40 A, 2.4 m
Ω
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFE
T
s
i
n a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET
TM
(Q2) have been designed to provide optimal power
efficiency.
Max r
DS(on)
= 7.5 m
Ω
at V
GS
= 10 V, I
D
= 12 A
Max r
DS(on)
= 12 m
Ω
at V
GS
= 4.5 V, I
D
= 10 A
Q2: N-Channel
Max r
DS(on)
= 2.4 m
Ω
at V
GS
= 10 V, I
D
= 20 A
Max r
DS(on)
= 2.9 m
Ω
at V
GS
= 4.5 V, I
D
= 18 A
Applications
RoHS Compliant
Computing
Communications
General Purpose Point of Load
Notebook VCORE
S2
S2
Q2
S2
D1
S2
5
6
7
8
4
3
2
1
G2
S1/D2
D1
D1
S2
S2
G2
D1
G1
D1
D1
D1
G1
Q1
Top
Bottom
Power 56
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Q1
30
Q2
30
Units
Drain to Source Voltage
Gate to Source Voltage
V
V
(Note 3)
T
C
= 25 °C
T
A
= 25 °C
±20
±20
Drain Current
-Continuous
30
40
I
D
-Continuous
-Pulsed
12
1a
40
22
1b
60
A
Power Dissipation
for Single Operation
T
A
= 25 °C
T
A
= 25 °C
2.2
1a
1.0
1c
2.5
1b
1.0
1d
P
D
W
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
θ
JA
R
θ
JA
R
θ
JC
Thermal Resistance, Junction to Ambient
57
1a
125
1c
3.5
50
1b
120
1d
2
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
FDMS7700S
FDMS7700S
Power 56
12 mm
3000 units
1
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
I
D
= 250
μ
A, V
GS
= 0 V
I
D
= 1 mA, V
GS
= 0 V
Q1
Q2
30
30
BV
DSS
Drain to Source Breakdown Voltage
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
Q1
Q2
15
14
mV/°C
I
D
= 1 mA, referenced to 25 °C
Q1
Q2
1
500
μ
A
μ
A
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 24 V,
V
GS
= 0 V
V
GS
= 20 V, V
DS
= 0 V
Q1
Q2
100
100
nA
nA
On Characteristics
V
GS
= V
DS
, I
D
= 250
μ
A
Q1
Q2
1
1
1.8
1.5
3
3
V
GS(th)
Gate to Source Threshold Voltage
V
V
GS
= V
DS
, I
D
= 1 mA
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
I
D
= 1 mA, referenced to 25 °C
Q1
Q2
-6
-4
mV/°C
V
V
GS
= 10 V,
I
D
= 12 A
GS
= 4.5 V,
I
D
= 10 A
6.0
8.5
8.3
7.5
12
12
Q1
Q2
V
GS
= 10
V
,
I
D
= 12 A , T
J
= 125 °C
r
DS(on)
Drain to Source On Resistance
m
Ω
V
GS
= 10 V,
I
D
= 20 A
V
GS
= 4.5 V,
I
D
= 18 A
V
GS
= 10
V
,
I
D
= 20 A , T
J
= 125 °C
1.9
2.2
2.1
2.4
2.9
3.4
V
DS
= 5 V,
I
D
= 12 A
Q1
Q2
63
160
g
FS
Forward Transconductance
S
V
DS
= 5 V,
I
D
= 20 A
Dynamic Characteristics
Q1
Q2
1315
7240
1750
9630
Q1:
C
iss
C
oss
C
rss
R
g
Input Capacitance
pF
pF
pF
Ω
V
DS
= 15
V
,
V
GS
= 0 V, f = 1 MHZ
Q1
Q2
445
2690
600
3580
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
V
DS
= 15
V
,
V
GS
= 0 V, f = 1 MHZ
Q1
Q2
45
185
70
280
Q1
Q2
0.9
0.8
Switching Characteristics
Q1
Q2
8.6
21
18
34
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2.5
9.2
10
18
V
DD
= 15 V, I
D
= 12 A,
R
GEN
= 6
Ω
Q1
Q2
20
58
32
93
Q2:
Turn-Off Delay Time
Fall Time
ns
V
DD
= 15 V, I
D
= 20 A,
R
GEN
= 6
Ω
Q1
Q2
2.3
6.8
10
14
ns
Q1
Q2
20
105
28
147
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
GS
= 0
V to 10 V
Q1
nC
nC
nC
nC
V
DD
= 15 V,
I
D
= 12 A
Q1
Q2
9.3
48
13
67
Q
g
V
GS
= 0
V to 4.5 V
Q1
Q2
4.3
19
Q2
V
DD
= 15 V,
Q
gs
Q
gd
Q1
Q2
2.2
11
I
D
= 20 A
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS
= 0 V, I
S
= 12 A
GS
= 0 V, I
S
= 20 A
(Note 2)
Q1
(Note 2)
Q2
0.8
0.7
1.2
1.2
V
SD
t
rr
Source to Drain Diode
Forward Voltage
Reverse Recovery Time
V
Q1
Q2
27
53
43
85
Q1
ns
nC
I
F
= 12 A, di/dt = 100 A/
μ
s
Q2
I
F
= 20 A, di/dt = 300 A/
μ
s
Q1
Q2
10
100
18
160
Q
rr
Reverse Recovery Charge
Notes:
2
1:
R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined
θ
CA
θ
JA
θ
JC
by the user’s board design.
b. 50 °C/W when mounted on
a 1 in
pad of
2 oz
copper
a. 57 °C/W when mounted on
a 1 in
pad of
2 oz
copper
2
2
c. 125 °C/W when mounted on
minimum pad of 2 oz copper
a
d. 120 °C/W when mounted on
minimum pad of 2 oz copper
a
2:
Pulse
T
e
st: Pulse Width < 300
μ
s, Duty cycle < 2.0%.
3:
As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
40
30
20
10
0
4
3
2
1
0
V
GS
= 10 V
= 6 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
V
GS
= 4.5
V
V
GS
= 4
V
V
GS
= 3.5 V
V
GS
= 4 V
V
GS
= 4.5 V
V
GS
= 3.5 V
0.5
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 6 V
V
GS
= 10 V
0.0
1.0
1.5
2.0
0
10
20
30
40
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
Figur
e
2
. No
rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
40
1.6
1.4
1.2
1.0
0.8
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 12 A
V
GS
= 10 V
30
I
D
= 12 A
20
T
J
= 125
o
C
10
T
J
= 25
o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75
100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
40
40
V
GS
= 0 V
PULSE DURATION = 80
μ
s
10
DUTY CYCLE = 0.5% MAX
30
20
10
0
V
DS
= 5 V
1
T
J
= 150
o
C
T
J
= 150
o
C
T
J
= 25
o
C
0.1
T
J
= 25
o
C
0.01
0.001
T
J
= -55
o
C
T
J
= -55
o
C
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
10
2000
1000
I
D
= 12 A
C
iss
8
V
DD
= 10 V
C
oss
6
V
DD
= 15 V
100
4
V
DD
=
20 V
2
C
rss
f = 1 MHz
= 0 V
V
GS
0
10
0.1
1
10
30
0
5
10
Q ,
GATE CHARGE (nC)
15
20
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
g
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s
D r a i n
to Source Voltage
60
100
10
R
θ
JC
= 3.5
o
C/W
V
GS
= 10 V
100us
1 ms
40
20
0
V
GS
= 4.5 V
10 ms
1
THIS AREA IS
LIMITED BY r
100 ms
DS
(
on
)
Limited by Package
SINGLE PULSE
T
J
= MAX RATED
1s
0.1
10s
DC
R
θ
JA
= 125
o
C/W
T
A
= 25
o
C
0.01
0.01
25
50
75
100
125
150
0.1
1
10
100
200
T
C
,
CASE TEMPERATURE
(
o
C
)
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figur
e
9
. Maximum Continuous Drain
Current vs Case Temperature
Figur
e
1
0. Forward
Bias Safe
Operating Area
1000
100
10
SINGLE PULSE
R
θ
JA
= 125
o
C/W
T
A
= 25
o
C
1
0.5
10
-4
10
-3
10
-2
10
-1
t, PULSE WIDTH (s)
1
10
100
1000
Figure 11.
Single Pulse Maximum Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics (Q1 N-Channel)
T
J
= 25°C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
t
SINGLE PULSE
2
R
θ
JA
= 125
o
C/W
NOTES:
DUTY FACTOR: D = t
/t
1
2
x R
(
Note 1c
)
PEAK T
= P
J
x Z
+ T
DM
θ
JA
θ
JA
A
0.001
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 12.
Junction-to-Ambient Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics (Q2 SyncFET)
60
6
5
4
3
2
1
0
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
μ
s
50
DUTY CYCLE = 0.5% MAX
V
GS
= 2.5 V
V
GS
= 10 V
40
30
20
10
0
V
GS
= 4.5 V
V
GS
= 3.5 V
V
GS
= 3 V
V
GS
= 3 V
V
GS
= 2.5 V
V
GS
= 3.5 V
10
V
GS
= 4.5 V
V
GS
= 10 V
50
0
0.2
0.4
0.6
0.8
1.0
0
20
30
40
60
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 13. On-Region Characteristics
Figure 14.
Normalized on-Resistance vs Drain
Current and Gate
Voltage
1.6
10
I
D
= 20 A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
8
V
GS
= 10 V
1.4
1.2
1.0
0.8
0.6
I
D
= 20 A
6
4
T
J
= 125
o
C
2
0
T
J
= 25
o
C
-75 -50 -25
0
25 50 75
100 125 150
2
4
6
8
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 16. On-Resistance vs Gate to
Source Voltage
Figure 15. Normalized On-Resistance
vs Junction Temperature
60
60
V
GS
= 0 V
T
J
= 125
o
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
10
1
50
40
30
20
10
0
C
V
DS
= 5 V
T
J
= 25
o
C
T
J
= 125
o
C
0.1
T
J
= 25
o
C
T
J
= -55
o
C
0.01
0.001
T
J
= -55
o
C
1.0
1.5
2.0
2.5
3.0
0
0.2
0.4
0.6
0.8
1.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 17. Transfer Characteristics
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics
(Q2 SyncFET)
30000
10000
10
I
D
= 20 A
C
iss
8
V
DD
= 10 V
6
C
oss
V
DD
= 15 V
1000
100
4
V
DD
= 20 V
C
rss
2
0
f = 1 MHz
= 0 V
V
GS
30
0.1
1
10
0
40
80
120
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 20. Capacitance vs Drain
to Source Voltage
Figure 19. Gate Charge Characteristics
150
100
10
R
θ
JC
= 2
o
C/W
V
GS
= 10 V
1 ms
100
50
0
10 ms
V
GS
= 4.5 V
THIS AREA IS
1
100 ms
LIMITED BY r
DS(on)
1 s
SINGLE PULSE
T
J
= MAX RATED
θ
JA
= 120
o
C/W
A
= 25
o
C
0.1
10 s
DC
R
Limited by Package
T
0.01
25
50
75
100
125
150
0.01
0.1
1
10
100
T
C
,
CASE TEMPERATURE
(
o
C
)
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 21.
Maximum Continuous Drain
Current vs Case
Temperature
Figure 22. Forward Bias Safe Operating Area
1000
100
10
SINGLE PULSE
R
θ
JA
= 120
o
C/W
T
A
= 25
o
C
1
0.5
10
-3
10
-2
10
-1
1
10
100
1000
t, PULSE WIDTH (s)
Figure 23. Single
Pulse Maximum Power Dissipation
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics
(Q2 SyncFET)
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
/t
θ
JA
= 120
o
C/W
1
2
R
PEAK T
= P
x Z
x R
+ T
J
DM
θ
JA
θ
JA
A
(Note 1d)
10
-3
10
-2
10
-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 24. Junction-to-Ambient Transient Thermal Response Curve
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
Typical Characteristics
(continued)
TM
SyncFET Schottky
Body Diode
Characteristics
Fairchild’s SyncFET
TM
process embeds a Schottky diode in
parallel with PowerTrench
MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
®
with
a MOSFET. Figure 25 shows the reverse recovery
characteristic of the FDMS7700S.
10
-1
12
9
T
J
= 125
o
C
C
10
-2
10
-3
10
-4
10
-5
6
didt = 300 A/
μ
s
T
J
= 100
o
3
0
-3
-6
T
J
= 25
o
C
0
5
10
15
20
25
30
100
150
200
250
300
TIME (ns)
V
DS
, REVERSE VOLTAGE (V)
Figure 26. SyncFET
TM
Body Diode Reverse
Leakage vs.
Drain-Source Voltage
Figure 25. FDMS7700S SyncFET
TM
Body
Diode Reverse Recovery Characteristic
©2009 Fairchild Semiconductor Corporation
FDMS7700S Rev.C1
0.05 C
B
5.00
A
2X
4.46
1.27
0.65
8
6
7
5
0.63(5X)
0.25
0.40
6.00
2.67
6.30
0.54
0.66
0.05 C
PIN#1 IDENT
2X
0.92
ꢀꢁꢄꢃꢀꢁꢀꢃ
0.10 C
ꢀꢁꢂꢀꢀꢁꢀꢃ
0.08 C
2
4
1
3
0.65 (5X)
ꢀꢁꢀꢂꢃꢀꢁꢀꢂꢃ
4.00
C
SIDE VIEW
SEATING
PLANE
RECOMMENDED LAND PATTERN
(OPTION 1 – FUSED LEADS 5,6,7)
ꢃꢁꢀꢀꢀꢁꢀꢃ
ꢅꢁꢆꢀꢀꢁꢀꢃ
(0.34)4X
ꢀꢁꢉꢅꢀꢁꢀꢃꢊꢃ;ꢋ
4.46
1.27
2
1
3
4
PIN#1 IDENT
0.65(8X)
8
6
7
5
0.63(8X)
ꢀꢁꢌꢂꢀꢁꢀꢃ
0.40
(0.66)
ꢀꢁꢃꢃꢀꢁꢀꢃ
ꢈꢁꢀꢀꢀꢁꢀꢃ
2.67
ꢂꢁꢈꢄꢀꢁꢀꢃ
6.30
0.54
0.66
0.45
0.92
5
8
6
7
ꢀꢁꢃꢇꢀꢁꢀꢃꢊꢃ;ꢋ
0.10 C A B
0.05 C
1.27
ꢅꢁꢆꢇꢀꢁꢀꢃ
2
4
1
3
4.00
BOTTOM VIEW
RECOMMENDED LAND PATTERN
(OPTION 2 – ISOLATED LEADS)
NOTES:
A. PACKAGE
DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS
ARE IN MILLIMETERS.
C. DIMENSIONS
AND TOLERANCES PER
ASME Y14.5M, 2009.
D. LAND
PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
E. DRAWING
FILENAME: MKT-MLP08Prev2.
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