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October 2014
FDMS86101A
N-Channel Shielded Gate PowerTrench
®
MOSFET
100 V, 60 A, 8 m
Ω
Features
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced PowerTrench
®
process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Shielded Gate MOSFET Technology
Max r
DS(on)
= 8 m
Ω
at V
GS
= 10 V, I
D
= 13 A
Max r
DS(on)
= 13.5 m
Ω
at V
GS
= 6 V, I
D
= 9.5 A
Advanced Package and Silicon combination for
low r
DS(on)
and high efficiency
MSL1 robust package design
100% UIL tested
Application
DC-DC Conversion
100% Rg tested
RoHS Compliant
Bottom
Top
Pin 1
S
D
D
D
D
S
S
S
G
S
S
G
Pin 1
D
D
D
D
Power 56
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted
Symbol
V
DS
V
GS
Parameter
Ratings
100
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
V
V
±20
T
C
= 25 °C
T
A
= 25 °C
60
I
D
(Note 1a)
(Note 3)
13
A
-Pulsed
180
E
AS
Single Pulse Avalanche Energy
Power Dissipation
486
mJ
W
T
C
= 25 °C
T
A
= 25 °C
104
P
D
Power Dissipation
(Note 1a)
2.5
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
θ
JC
R
θ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
1.2
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS86101A
FDMS86101A
Power 56
3000 units
1
©2012 Fairchild Semiconductor Corporation
FDMS86101A Rev.C2
Electrical Characteristics
T
J
= 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
Drain to Source Breakdown Voltage
I
D
= 250
μ
A, V
GS
= 0 V
100
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
71
mV/°C
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 80 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
800
nA
nA
±100
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
μ
A
2.0
3.1
-9
4.0
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
GS
= 10 V, I
D
= 13 A
mV/°C
V
6.3
8.0
8
r
DS(on)
g
FS
Static Drain to Source On Resistance
Forward Transconductance
V
GS
= 6 V, I
D
= 9.5 A
13.5
13.1
m
Ω
V
GS
= 10 V, I
D
= 13 A, T
J
= 125 °C
V
DS
= 10 V, I
D
= 13 A
10.3
53
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
3095
460
15
4120
615
25
pF
pF
pF
Ω
V
DS
= 50 V, V
GS
= 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
1.6
3.3
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
19
5.4
27
35
11
44
10
58
31
ns
ns
V
DD
= 50 V, I
D
= 13 A,
V
GS
= 10 V, R
GEN
= 6
Ω
Turn-Off Delay Time
Fall Time
ns
4
ns
Q
g
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 0 V to 10 V
V
GS
= 0 V to 5 V
42
nC
nC
nC
nC
Q
g
22
V
DD
= 50 V,
D
= 13 A
I
Q
gs
Q
gd
13.5
6.2
Drain-Source Diode Characteristics
V
GS
= 0 V, I
S
= 2.1 A
(Note 2)
(Note 2)
0.74
0.81
64
1.2
1.3
V
SD
Source to Drain Diode
Forward Voltage
V
V
GS
= 0 V, I
S
= 13 A
t
rr
Reverse Recovery Time
102
164
ns
I
F
= 13 A, di/dt = 100 A/
μ
s
Q
rr
Reverse Recovery Charge
102
nC
Notes
:
2
1. R
is determined with the device mounted on a 1 in
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined by
θ
CA
θ
JA
θ
JC
the user’s board design.
a. 50 °C/W when mounted
on a
b. 125 °C/W when mounted on
a
minimum pad of 2 oz copper.
2
1 in
pad of
2 oz
copper.
2. Pulse Test: Pulse Width < 300
μ
s, Duty cycle < 2.0%.
3. E
486 mJ is based on starting T
= 25
°
C, L = 3 mH, I
= 18 A, V
= 100 V, V
= 10 V. 100% test at L = 0.1 mH, I
= 51 A.
AS
J
AS
DD
GS
AS
©2012 Fairchild Semiconductor Corporation
FDMS86101A Rev.C2
2
Typical Characteristics
T
J
= 25 °C unless otherwise noted
4
3
2
1
0
180
V
GS
= 4.5 V
V
= 10 V
V
= 6 V
GS
GS
V
GS
= 5 V
150
120
90
60
30
0
V
= 5.5 V
GS
V
GS
= 5.5 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
= 5 V
GS
V
GS
= 6 V
V
GS
= 10 V
V
= 4.5 V
GS
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
0
30
60
90
120
150
180
0
1
2
3
4
5
I
D
,
DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 1.
On-Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s ta n c e
vs Drain Current and Gate Voltage
40
2.0
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 13 A
I
D
= 13 A
1.8
1.6
1.4
1.2
1.0
0.8
0.6
V
GS
= 10 V
30
20
10
0
T
J
= 125
o
C
T
J
= 25
o
C
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75
100 125 150
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
F i gu re 3 .
N orma li zed
On – Res is ta nc e
vs Junction Temperature
Figur
e
4
. On-Resistance
vs Gate to
Source Voltage
180
200
100
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
150
120
90
60
30
0
V
DS
= 5 V
10
T
J
= 150
o
C
1
T
J
= 25
o
C
T
J
= 150
o
C
0.1
T
J
= -55
o
C
T
J
= 25
o
C
0.01
0.001
T
J
= -55
o
C
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDMS86101A Rev.C2
3
Typical Characteristics
T
J
= 25 °C unless otherwise noted
10000
1000
100
10
V
DD
= 50 V
I
D
= 13 A
C
iss
8
6
4
2
0
V
DD
= 25 V
V
DD
= 75 V
C
oss
C
rss
f = 1 MHz
10
5
V
GS
= 0 V
0.1
1
10
100
0
5
10 15 20 25 30 35 40 45
Q ,
GATE CHARGE (nC)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
g
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s D r a i n
to Source Voltage
100
90
75
60
45
30
15
0
R
θ
JC
= 1.2
o
C/W
V
GS
= 10 V
T
J
= 25
o
C
T
J
= 100
o
10
C
Limited by Package
V
GS
= 6 V
T
J
= 125
o
C
1
0.01
25
50
75
100
125
150
0.1
1
10
100 300
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figur
e
9. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs Case Temperature
200
100
500
SINGLE PULSE
θ
JA
= 125
o
C/W
A
= 25
o
C
R
100
10
T
10
1
1 ms
THIS AREA IS
LIMITED BY r
10 ms
DS(on)
100 ms
SINGLE PULSE
T
J
= MAX RATED
0.1
1 s
R
θ
JA
= 125
o
C/W
10 s
DC
T
A
= 25
o
C
1
0.01
0.01
0.5
10
-3
10
-2
10
-1
t, PULSE WIDTH (sec)
1
10
100
1000
0.1
1
10
100
500
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS86101A Rev.C2
4
Typical Characteristics
T
J
= 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.01
0.1
P
DM
0.05
0.02
0.01
t
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
SINGLE PULSE
θ
JA
= 125
o
C/W
1
2
R
PEAK T
= P
x Z
x R
+ T
J
DM
θ
JA
θ
JA
A
0.001
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 13.
Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS86101A Rev.C2
5
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE
STANDARD REFERENCE:
JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS
DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL
DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING
AND TOLERANCING PER
ASME Y14.5M-2009.
E. IT
IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP
OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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