onsemi-FDMS9408-F085
| Part # | onsemi-FDMS9408-F085 |
Download  | onsemi-FDMS9408-F085 |
Ma
rch
201
6
FDMS9408_F085
®
N-Channel PowerTrench
MOSFET
40 V, 80 A, 1.8 m
Ω
Features
Typical R
= 1.5 m
Ω
at V
= 10V, I
= 80 A
GS D
DS(on)
Typical Q
= 68 nC at V
= 10V, I
= 80 A
g(tot)
GS
D
UIS Capability
RoHS Compliant
Qualified to AEC Q101
Applications
Automotive Engine Control
PowerTrain Management
Solenoid and Motor Drivers
Integrated Starter/Alternator
Primary Switch for 12V Systems
For current package drawing, please refer to the Fairchild web
‐
PQFN08M.pdf
MOSFET Maximum Ratings
T
J
= 25°C unless otherwise noted.
Symbol
V
DSS
Parameter
Ratings
Units
Drain-to-Source Voltage
Gate-to-Source Voltage
40
V
V
V
GS
±20
Drain Current – Continuous (V
GS
=10) (Note 1)
Pulsed Drain Current
T
C
= 25°C
T
C
= 25°C
80
See Figure 4
143
I
D
A
E
AS
P
D
Single Pulse Avalanche Energy
(Note 2)
(Note 3)
mJ
W
W/
o
C
o
C
o
C/W
o
C/W
Power Dissipation
Derate Above 25
o
C
214
1.43
T
J
, T
STG
Operating and Storage
T
e
mperature
-55 to + 175
0.7
R
θ
JC
R
θ
JA
Thermal Resistance, Junction to Case
Maximum Thermal Resistance, Junction to Ambient
50
Notes:
1: Current
is limited by bondwire configuration.
2: Starting
T =
25°C, L = 70uH, I
= 64A, V
= 40V during inductor charging and V
= 0V during time in avalanche.
J
AS
DD
DD
3: R
is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder
θ
JA
mounting surface of the drain pins.
presented here is based on mounting on a 1 in
pad of 2oz copper.
R
is guaranteed by design, while R
is determined by the board design.
The maximum rating
θ
JC
θ
JA
2
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FDMS9408
FDMS9408_F085
Power56
13”
12mm
3000units
©2015 Fairchild Semiconductor Corporation
1
FDMS9408_F085 Rev. 1.
3
Electrical Characteristics
T
J
= 25°C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
B
VDSS
I
DSS
Drain-to-Source Breakdown Voltage
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
I
D
= 250
μ
A, V
GS
= 0V
40
–
–
–
–
–
–
1
V
V
DS
= 4 0 V ,
T
J
= 25
o
C
μ
A
mA
nA
V
GS
= 0V
T
J
= 175
o
C (Note 4)
–
1
I
GSS
V
GS
= ±20V
–
±100
On Characteristics
V
GS(th)
R
DS(on)
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
GS
= V
DS
, I
D
= 250
μ
A
2.0
3.0
1.5
2.5
4.0
1.8
3.0
V
T
J
= 25
o
C
–
–
m
Ω
m
Ω
I
D
= 80A,
T
J
= 175
o
C (Note 4)
V
GS
= 10V
Dynamic Characteristics
C
iss
Input Capacitance
–
–
–
–
–
–
–
–
5150
1770
89
–
–
pF
pF
pF
Ω
V
DS
= 20V, V
GS
= 0V,
C
oss
C
rss
R
g
Output Capacitance
f = 1MHz
Reverse Transfer Capacitance
Gate Resistance
–
f = 1MHz
2.8
68
–
Q
g(
T
o
T)
Q
g(th)
Q
gs
T
o
tal Gate Charge
V
GS
= 0 to 10V
V
GS
= 0 to 2V
92
14
–
nC
nC
nC
nC
V
DD
= 32V
I
D
= 80A
Threshold Gate Charge
Gate-to-Source Gate Charge
Gate-to-Drain “Miller“ Charge
9.3
22
Q
gd
12
–
Switching Characteristics
t
on
t
d(on)
t
r
Turn-On Time
Turn-On Delay
Rise Time
–
–
–
–
–
–
–
51
–
ns
ns
ns
ns
ns
ns
19
20
41
19
–
–
V
DD
= 20V, I
D
= 80A,
V
GS
= 10V, R
GEN
= 6
Ω
t
d(off)
t
f
Turn-Off Delay
Fall Time
–
–
t
off
Turn-Off Time
79
Drain-Source Diode Characteristics
I
SD
=80A, V
GS
= 0V
–
–
–
–
–
1.25
1.2
V
V
SD
Source-to-Drain Diode Voltage
I
SD
= 40A, V
GS
= 0V
–
V
t
rr
Reverse-Recovery Time
74
83
96
ns
nC
I
F
= 80A, dI
SD
/dt = 100A/
μ
s
V
DD
= 32V
Q
rr
Reverse-Recovery Charge
108
Note:
4: The
maximum value is specified by design at T
= 175°C.
Product is not tested to this condition in production.
J
©2015 Fairchild Semiconductor Corporation
2
FDMS9408_F085 Rev. 1.
3
Typical Characteristics
1.2
1.0
0.8
0.6
0.4
0.2
0.0
300
250
200
150
100
50
V
GS
= 10V
CURRENT LIMITED
BY PACKAGE
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
200
T
C
, CASE TEMPERATURE(
o
C)
T
C
, CASE TEMPERATURE(
o
C)
Figure 2.
Maximum Continuous Drain Current vs.
Case Temperature
Figure 1.
Normalized Power Dissipation vs. Case
Temperature
2
DUTY CYCLE – DESCENDING ORDER
1
D = 0.50
0.20
0.10
P
DM
0.05
0.02
0.01
t
0.1
1
t
2
NOTES:
DUTY FACTOR: D = t
/t
SINGLE PULSE
1
2
PEAK T
= P
x Z
x R
+ T
J
DM
θ
JC
θ
JC C
0.01
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t, RECTANGULAR
PULSE DURATION(s)
Figure 3.
Normalized Maximum Transient Thermal Impedance
10000
T
C
= 25
o
C
V
GS
= 10V
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
175 – T
C
I = I
2
1000
100
10
150
SINGLE PULSE
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t, RECTANGULAR PULSE DURATION(s)
Figure 4.
Peak Current Capability
©2015 Fairchild Semiconductor Corporation
3
FDMS9408_F085 Rev. 1.
3
Typical Characteristics
500
100
1000
100
10
If R = 0
= (L)(I
)/(1.3*RATED BV
t
AV
– V
)
AS
DSS
DD
If R
≠
0
t
AV
= (L/R)ln[(I
*R)/(1.3*RATED BV
– V
) +1]
DSS DD
AS
100us
STARTING T
J
= 25
o
C
OPERATION IN THIS
AREA MAY BE
10
LIMITED BY r
DS(on)
1ms
1
STARTING T
J
= 150
o
C
10ms
100ms
SINGLE PULSE
T
= MAX RATED
J
o
T
C
= 25
C
1
0.1
0.001 0.01
0.1
1
10
100 1000
10000
0.1
1
10
100 200
t
AV
, TIME IN AVALANCHE (ms)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6.
Unclamped Inductive Switching
Capability
Figure 5.
Forward Bias Safe Operating Area
300
300
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
GS
= 0 V
100
250
V
DD
= 5V
200
150
T
J
= 175
o
C
T
J
= 25
o
C
10
1
T
J
= 175
o
C
T
J
= -55
o
C
100
T
J
= 25
o
C
50
0
0.1
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7.
Transfer Characteristics
Figure 8.
Forward Diode Characteristics
300
250
200
150
100
50
300
V
GS
15V Top
10V
8V
7V
6V
250
200
150
100
50
V
GS
15V Top
10V
8V
7V
6V
5V
5.5V
5V Bottom
5.5V
5V Bottom
5V
80
μ
s PULSE WIDTH
Tj=175
o
C
80
μ
s PULSE WIDTH
Tj=25
o
C
0
0
0
1
2
3
4
5
0
1
2
3
4
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 9.
Saturation Characteristics
Figure 10.
Saturation Characteristics
©2015 Fairchild Semiconductor Corporation
4
FDMS9408_F085 Rev. 1.
3
Typical Characteristics
40
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
=
80A
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
30
20
10
0
T
J
= 175
o
C
T
J
= 25
o
C
I
D
= 80A
V
GS
= 10V
2
4
6
8
10
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE
(
o
C
)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 11.
R
DSON
vs. Gate Voltage
Figure 12.
Normalized R
DSON
vs. Junction
Temperature
1.4
1.10
V
GS
=
V
DS
I
D
= 5mA
I
D
= 250
μ
A
1.2
1.0
0.8
0.6
0.4
0.2
1.05
1.00
0.95
0.90
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE(
o
C)
Figure 13.
Normalized Gate Threshold Voltage vs.
Temperature
Figure 14.
Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
10000
10
I
D
= 80A
V
DD
=16V
C
iss
8
V
DD
= 20V
V
DD
= 24V
1000
C
oss
6
4
2
0
100
C
rss
f = 1MHz
V
GS
= 0V
10
0.1
1
10
100
0
20
40
60
80
Q
g
,
GATE CHARGE(nC)
V
DS
, DRAIN TO SOURCE VOLTAGE
(
V
)
Figure 15.
Capacitance vs. Drain to Source
Voltage
Figure 16.
Gate Charge
vs. Gate to Source
Voltage
©2015 Fairchild Semiconductor Corporation
5
FDMS9408_F085 Rev. 1.
3
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Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
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Rev. I77
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