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FDMT1D3N08B
N-Channel Dual Cool
TM
88 PowerTrench
®
MOSFET
80 V, 164 A, 1.35 m
Ω
Features
General Description
Max r
DS(on)
= 1.35 m
Ω
at V
GS
= 10 V, I
D
= 36 A
Max r
DS(on)
= 1.8 m
Ω
at V
GS
= 8 V, I
D
= 31 A
Advanced Package and Silicon Combination for Low r
DS(on)
and High Efficiency
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s
advanced
PowerTrench
®
process.
Advancements in both silicon and Dual Cool
TM
package
technologies have been combined to offer the lowest r
DS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance.
Next Generation Enhanced Body Diode
T
e
chnology,
Engineered for Soft Recovery
Applications
Low Profile 8×8 mm MLP Package
MSL1 Robust Package Design
100% UIL
T
e
sted
OringFET / Load Switching
Synchronous Rectification
DC-DC Conversion
RoHS Compliant
Pin 1
Pin 1
G
S
D
D
D
D
G
S
S
S
S
S
S
D
D
D
D
Top
Dual Cool
TM
88
Bottom
MOSFET Maximum Ratings
T
A
= 25 °C unless otherwise noted.
Symbol
V
DS
V
GS
Parameter
Ratings
80
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
V
V
±20
T
C
= 25 °C
C
= 100 °C
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
164
T
103
I
D
A
-Continuous
T
A
= 25 °C
36
-Pulsed
864
E
AS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
1734
178
mJ
W
T
C
= 25 °C
T
A
= 25 °C
P
D
(Note 1a)
3.3
T
J
, T
STG
Operating and Storage Junction
T
e
mperature Range
-55 to +150
°C
Thermal Characteristics
R
θ
JC
R
θ
JC
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
Thermal Resistance, Junction-to-Case
(
T
o
p Source)
(Bottom Drain)
(Note 1a)
1.9
0.7
38
81
15
21
9
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
(Note 1b)
°C/W
(Note 1i)
(Note 1j)
(Note 1k)
Package Marking and Ordering Information
Device Marking
Device
Package
Dual Cool
TM
88
Reel Size
Tape Width
13.3 mm
Quantity
1D3N08B
FDMT1D3N08B
13”
3000 units
Semiconductor Components Industries, LLC, 2016
November, 2016, Rev. 1.0
Publication Order Number:
FDMT1D3N08B/D
1
Electrical Characteristics
T
J
= 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BV
DSS
Drain to Source Breakdown Voltage
I
D
= 250
μ
A, V
GS
= 0 V
80
V
Δ
BV
DSS
Δ
T
J
Breakdown Voltage
T
e
mperature
Coefficient
I
D
= 250
μ
A, referenced to 25 °C
50
mV
/
°C
I
DSS
I
GSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
DS
= 64 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
1
μ
A
100
nA
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
μ
A
2.0
3.2
-11
4.0
V
Δ
V
GS(th)
Δ
T
J
Gate to Source Threshold Voltage
T
e
mperature Coefficient
I
D
= 250
μ
A, referenced to 25 °C
V
GS
= 10 V, I
D
= 36 A
GS
= 8 V, I
D
= 31 A
mV/°C
1.1
1.3
1.8
116
1.35
1.8
r
DS(on)
g
FS
Static Drain to Source On Resistance
Forward Transconductance
V
m
Ω
V
GS
= 10 V, I
D
= 36 A, T
J
= 125 °C
V
DS
= 5 V, I
D
= 36 A
2.2
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
14000
2050
50
19600
2870
150
pF
pF
pF
Ω
V
DS
= 40 V, V
GS
= 0 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
1.4
2.1
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Turn-On Delay Time
Rise Time
63
56
101
90
ns
ns
V
DD
= 40 V, I
D
= 36 A,
V
GS
= 10 V, R
GEN
= 6
Ω
Turn-Off Delay Time
Fall Time
68
109
32
ns
20
ns
Q
g(TOT)
Q
g(TOT)
Q
gs
T
o
tal Gate Charge
T
o
tal Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Output Charge
V
GS
= 0 V to 10 V
V
GS
= 0 V to 8 V
186
152
67
260
213
nC
nC
nC
nC
nC
V
DD
= 40 V,
D
= 36 A
I
Q
gd
37
Q
oss
V
DD
= 40 V, V
GS
= 0 V
185
Drain-Source Diode Characteristics
V
GS
= 0 V, I
S
= 2.6 A
(Note 2)
(Note 2)
0.7
0.8
83
1.1
1.2
V
SD
Source to Drain Diode
Forward Voltage
V
V
GS
= 0 V, I
S
= 36 A
t
rr
Reverse Recovery Time
132
143
ns
I
F
= 36 A, di/dt = 100 A/
μ
s
Q
rr
Reverse Recovery Charge
90
nC
2
Thermal Characteristics
R
θ
JC
R
θ
JC
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JA
Thermal Resistance, Junction-to-Case
(
T
o
p Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1d)
(Note 1e)
(Note 1f)
1.9
0.7
38
81
26
34
14
16
26
60
15
21
9
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
°C/W
(Note 1g)
(Note 1h)
(Note 1i)
(Note 1j)
(Note 1k)
(Note 1l)
11
NOTES:
1. R
is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. R
is determined
by the user’s board design.
θ
CA
θ
JA
b. 81 °C/W when mounted on
a minimum pad of 2 oz copper
a. 38 °C/W when mounted on
a 1 in
pad of
2 oz
copper
2
2
c. Still air, 20.9×10.4×12.7mm Aluminum Heat Sink, 1 in
pad of 2 oz copper
d. Still air, 20.9×10.4×12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
2
e. Still air, 45.2×41.4×11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in
pad of 2 oz copper
f. Still air, 45.2×41.4×11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2
g. 200FPM Airflow, No Heat Sink,1 in
pad of 2 oz copper
h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper
2
i. 200FPM Airflow, 20.9×10.4×12.7mm Aluminum Heat Sink, 1 in
pad of 2 oz copper
j. 200FPM Airflow, 20.9×10.4×12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
2
k. 200FPM Airflow, 45.2×41.4×11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in
pad of 2 oz copper
l. 200FPM Airflow, 45.2×41.4×11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 30
0
μ
s, Duty cycle < 2.0%.
3. E
of 1734
mJ is based on starting T
= 25
°
C; N-ch: L = 3 mH, I
= 34 A, V
= 80 V, V
=10 V. 100% test at L = 0.3 mH, I
= 77 A.
AS
J
AS
DD
GS
AS
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
3
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
320
4
3
2
1
0
V
GS
= 10 V
V
GS
= 8 V
V
GS
= 6 V
V
GS
= 7 V
240
V
GS
= 6.5 V
V
GS
= 6.5 V
160
V
GS
= 7 V
V
GS
= 6 V
80
V
GS
= 10 V
V
GS
= 8 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
0
0.0
0.5
1.0
1.5
2.0
0
64
128
192
256
320
V
DS
,
DRAIN TO SOURCE VOLTAGE (V)
I
D
,
DRAIN CURRENT (A)
Figure 1.
On Region Characteristics
Figur
e
2
. N
o r m a l i z e d O n – R e s i s ta n c e
vs. Drain Current and Gate Voltage
1.9
12
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
I
D
= 36 A
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
V
GS
= 10 V
I
D
= 36 A
9
6
3
0
T
J
= 125
o
C
T
J
= 25
o
C
-75 -50 -25
0
25 50 75
100 125 150
4
5
6
7
8
9
10
T
J
,
JUNCTION TEMPERATURE
(
o
C
)
V
GS
,
GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figur
e
4
. On-Resistance
vs. Gate to
Source Voltage
320
320
V
GS
= 0 V
PULSE DURATION = 80
μ
s
DUTY CYCLE = 0.5% MAX
V
DS
= 5 V
100
256
192
128
64
10
T
J
= 150
o
C
1
T
J
= 150
o
C
T
J
= 25
o
C
0.1
T
J
= 25
o
C
T
J
= -55
o
C
0.01
0.001
T
J
= -55
o
C
0
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5.
Transfer Characteristics
Figur
e
6
. Source
to Drain Diode
Forward Voltage vs. Source Current
4
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
10
100000
10000
1000
100
I
D
= 36 A
C
iss
V
DD
= 30 V
8
V
DD
= 40 V
C
oss
6
V
DD
= 50 V
C
rss
4
2
0
10
f = 1 MHz
GS
= 0 V
V
1
0
40
80
120
160
200
0.1
1
10
80
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7.
Gate Charge Characteristics
Figur
e
8
. C
a p a c i t a n c e v s . D r a i n
to Source Voltage
200
180
144
108
72
100
10
1
T
J
= 25
o
C
V
GS
= 10 V
T
J
= 100
o
C
V
GS
= 4.5 V
T
J
= 125
o
C
36
R
θ
JC
= 1.9
o
C/W
0
0.001 0.01
0.1
1
10
100 1000
10000
25
50
75
100
125
150
T
C
,
CASE TEMPERATURE
(
o
C
)
t
AV
, TIME IN AVALANCHE (ms)
Figur
e
9
. U
n c l a m p e d I n d u c t i v e
Switching Capability
Figur
e
1
0. Maximum Continuous Drain
Current vs.
Case Temperature
1000
100
10
100000
10000
1000
100
SINGLE PULSE
R
θ
JC
= 1.9
o
C/W
C
= 25
o
C
T
10
μ
s
THIS AREA IS
LIMITED BY r
DS(on)
100
μ
s
1 ms
SINGLE PULSE
T
J
= MAX RATED
R
θ
JC
= 1.9
o
C/W
1
10 ms
100 ms
CURVE BENT TO
MEASURED DATA
T
C
= 25
o
C
0.1
0.1
10
10
-5
10
-4
10
-3
t, PULSE WIDTH (sec)
10
-2
10
-1
1
1
10
100
300
V
DS
, DRAIN to SOURCE VOLTAGE (V)
Figure 11.
Forward Bias Safe
Operating Area
Figur
e
1
2. Single Pulse
Maximum
Power Dissipation
5
Typical Characteristics
T
J
= 25 °C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
P
DM
0.1
0.1
0.05
0.02
0.01
t
1
t
2
NOTES:
(t) = r(t) x R
0.01
SINGLE PULSE
Z
θ
JC
θ
JC
o
R
= 1.9
C/W
θ
JC
Peak T
= P
x Z
(t) + T
J
DM
θ
JC C
Duty Cycle, D = t
/ t
1
2
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13.
Junction-to-Case Transient Thermal Response Curve
6
Dimensional Outline and Pad Layout
ON Semiconductor and the ON Logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other
countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent-Marking.pdf.
ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON
Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a
critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices
intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall
indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is
subject to all applicable copyright laws and is not for resale in any manner.
7
(2X)
8
8.00
6.90
2.00
0.05 C
A
8.00±0.10
8
B
5
5
1.10
5.23
KEEP OUT
AREA
4.24
3.94
PKG
L
8.00±0.10
9.00
C
(1.83)
1.55
0.48
(2.41)
1.13
0.05 C
(2X)
1
4
PKG
1
4
C
L
(1.00)
5.10
7.10
1.10
4.03
3.68
(1.56)
SEE DETAIL A
(8X)
LAND PATTERN
RECOMMENDATION
0.30
0.20
0.95
0.75
0.10
.05
C A B
6.00
C
C
0.05
0.00
8X
1.10
SEATING
PLANE
2.00
0.90
(0.40)
(0.50)
0.70
0.50
SCALE: 2X
1
2
3
4
PIN #1
IDENT
1.68
1.48
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE IS NOT PRESENTLY REGISTERED
WITH ANY STANDARDS COMMITTEE.
B) DIMENSIONS ARE INCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DRAWING CONFORMS TO ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUR AREA.
1.20
2.78
5.33
5.13
(0.91)
0.45
(1.23)
F) DRAWING FILENAME: MKT-PQFN08RREV2
8
7
6
5
0.25
7.00
6.80
(4X)
(0.60)
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at
www.onsemi.com/site/pdf/Patent
−
Marking.pdf
. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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1050
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone
: 303
−
675
−
2175 or 800
−
344
−
3860
T
o
ll Free USA/Canada
Fax
: 303
−
675
−
2176 or 800
−
344
−
3867
T
o
ll Free USA/Canada
Email
: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
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Semiconductor Components Industries, LLC
