onsemi-FDP12N50NZ

Part #onsemi-FDP12N50NZ
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onsemi-FDP12N50NZ
November 2013  
FDP12N50NZ / FDPF12N50NZ  
TM  
N-Channel UniFET
 
II MOSFET
 
500 V, 11.5 A, 520 m
 
Features  
Description  
•
•
•
•
•
•
R

DS(on)

= 460 m
(Typ.) @ V

GS

= 10
V
,
I

D

= 5.75 A  
Low Gate Charge (Typ. 23 nC )  
Low C

rss

(Typ. 14 pF )  
UniFET

TM

II MOSFET is Fairchild Semiconductor’s high voltage  
MOSFET family based on advanced planar stripe and DMOS  
technology. This advanced MOSFET family has the smallest  
on-state resistance among the planar MOSFE
T
,
a
nd also pro-  
vides superior switching performance and higher avalanche  
energy strength. In addition, internal gate-source ESD diode  
allows UniFET II MOSFET to withstand over 2kV HBM surge  
stress. This device family is suitable for switching power con-  
verter applications such as power factor correction (PFC), flat  
panel display (FPD) TV power, ATX and electronic lamp bal-  
lasts.  
100% Avalanche Tested  
ESD Improved Capability  
RoHS Compliant  
Applications  
•
•
•
LCD/LED/PDP TV  
Lighting  
Uninterruptible Power Supply  
D
G
G
D
S
G
D
TO-220F  
TO-220  
S
S
MOSFET Maximum Ratings
T

C

= 25

o

C unless otherwise noted
.  
Symbol  
V

DSS  

V

GSS  

Parameter  
FDP12N50NZ FDPF12N50NZ  
Unit  
V
Drain to Source Voltage  
Gate to Source Voltage  
500  
±25  
V
– Continuous (T

C

= 25

o

C)  
– Continuous (T

C

= 100

o

C)  
– Pulsed  
11.5  
6.9  
46  
11.5*  
6.9*  
46*  
I

D  

Drain Current  
Drain Current  
A
I

DM  

(Note 1)  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
A
mJ  
A
E

AS  

I

AR  

Single Pulsed Avalanche Energy  
Avalanche Current  
560  
11.5  
17  
E

AR  

dv/dt  
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
mJ  
V/ns  
W
W/

o

C  

o

C  
4.5  
(T

C

= 25

o

C)  
– Derate above 25

o

C  
170  
42  
P

D  

Power Dissipation  
1.37  
0.33  
T

J

, T

STG  

T

L  

Operating and Storage
T
e
mperature Range  
-55 to +150  
300  
Maximum Lead
T
e
mperature for Soldering,  
1/8” from Case for 5 Seconds  

o

C  
*Drain current limited by maximum junction temperature  
Thermal Characteristics  
Symbol  
R

JC  

R

JA  

Parameter  
Unit  
FDP12N50NZ FDPF12N50NZ  
Thermal Resistance, Junction to Case, Max.  
Thermal Resistance, Junction to Ambient, Max.  
0.73  
62.5  
3.0  

o

C/W  
62.5  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
1

Package Marking and Ordering Information  
Device Marking  
FDP12N50NZ  
FDPF12N50NZ  
Device  
Package  
TO-220  
Reel Size  
Tube  
Tape Width  
N/A  
Quantity  
50 units  
50 units  
FDP12N50NZ  
FDPF12N50NZ  
TO-220F  
Tube  
N/A  
Electrical Characteristics

T

C

= 25

o

C unless otherwise noted.  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
Off Characteristics  
I

D

= 250
A, V

GS

= 0V, T

J

= 25

o

C  
–
–
–
V
500  
–
BV

DSS  

Drain to Source Breakdown Voltage  
BV

DSS  

/
T

J  

Breakdown Voltage
T
e
mperature  
Coefficient  
I

D

= 250
A, Referenced to 25

o

C  
0.5  
V/

o

C  
V

DS

= 500V, V

GS

= 0V  
–
–
–
–
–
–
1
I

DSS  

I

GSS  

Zero Gate Voltage Drain Current  
Gate to Body Leakage Current  
A  
A  
V

DS

= 400V, T

C

= 125

o

C  
10  
V

GS

= ±25V, V

DS

= 0V  
±10  
On Characteristics  
V

GS(th)  

R

DS(on)  

g

FS  

Gate Threshold Voltage  
V

GS

= V

DS

, I

D

= 250
A  
V

GS

= 10V, I

D

= 5.75A  
V

DS

= 20V, I

D

= 5.75A  
3.0  
–
5.0  
0.52  
–
V
S
Static Drain to Source On Resistance  
Forward Transconductance  
–
–
0.46  
12  
Dynamic Characteristics  
C

iss  

C

oss  

C

rss  

Q

g  

Input Capacitance  
–
–
–
–
–
945  
155  
14  
1235  
205  
20  
30  
–
pF  
pF  
pF  
nC  
nC  
nC  
V

DS

= 25V, V

GS

= 0V  
f = 1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
T
o
tal Gate Charge at 10V  
Gate to Source Gate Charge  
Gate to Drain “Miller” Charge  
23  
V
V

DS

= 400V, I

D

= 11.5A  

GS

= 10V  
Q

gs  

Q

gd  

5.5  
9.6  
(Note 4)  
–
–
Switching Characteristics  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn-On Delay Time  
Turn-On Rise Time  
Turn-Off Delay Time  
Turn-Off Fall Time  
–
–
–
–
20  
50  
60  
45  
50  
ns  
ns  
ns  
ns  
V
R

DD

= 250V, I

D

= 11.5A  

G

= 25
  
110  
130  
100  
(Note 4)  
Drain-Source Diode Characteristics  
I

S  

Maximum Continuous Drain to Source Diode Forward Current  
Maximum Pulsed Drain to Source Diode Forward Current  
–
–
–
–
–
–
–
11.5  
46  
1.4  
–
A
A
I

SM  

V

SD  

t

rr  

Drain to Source Diode Forward Voltage  
Reverse Recovery Time  
V

GS

= 0V, I

SD

= 11.5A  
–
V
315  
2.0  
ns  
C  
V

GS

= 0V, I

SD

= 11.5A  
dI

F

/dt = 100A/
s  
Q

rr  

Reverse Recovery Charge  
–
Notes:  
1. Repetitive Rating: Pulse width limited by maximum junction temperature  
2. L = 8.5mH, I
 
= 11.5A, V
 
= 50V, R
 
= 25
, Starting T
 
= 25
C  
AS  
DD  
G
J
3. I
 

11.5A, di/dt
200A/
s, V
 
BV  
, Starting T
 
= 25
C  
SD  
DD  
DSS  
J
4. Essentially Independent of Operating
T
e
mperature Typical Characteristics  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
2

Typical Characteristics  
Figure 1. On-Region Characteristics  
Figure 2. Transfer Characteristics  
30  
50  
V

GS

=
15.0 V  
10.0 V  
8.0 V  
7.0 V  
10  
10  
6.5V  
6.0 V  
5.5 V  
150

o

C  
25

o

C  
1
1
-55

o

C  
*Notes:  
1. 250
s Pulse Test  
2. T

C

= 25

o

C  
*Notes:  
1. V

DS

= 20V  
2. 250
s Pulse Test  
0.1  
0.1  
0.1  
1
10  
20  
3
4
5
6
7
8
9
10  
V

DS

, Drain-Source Voltage[V]  
V

GS

, Gate-Source Voltage[V]  
Figure 3. On-Resistance Variation vs.  
Figure 4. Body Diode Forward Voltage  
Variation vs. Source Current  
and Temperature  
Drain Current and Gate Voltage  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
100  
150

o

C  
10  
25

o

C  
V

GS

= 10V  
*Notes:  
1. V

GS

= 0V  
V

GS

= 20V  
*Note: T

C

= 25

o

C  
2. 250
s Pulse Test  
1
0.4  
0
6
12  
18  
24  
30  
0.6  
0.8  
1.0  
1.2  
1.4  
I

D

, Drain Current [A]  
V

SD

, Body Diode Forward Voltage [V]  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
10  
2500  
C
C
C
= C
 
+ C
 
(
C =
 
shorted
)  
gs gd
 
ds  
iss  
= C
 
+ C  
ds gd  
oss  
rss  
= C  
gd  
V

DS

= 100V  
8
2000  
1500  
1000  
500  
0
V

DS

= 250V  
*Note:  
1. V

GS

= 0V  
V

DS

= 400V  
2. f = 1MHz  
6
4
2
0
C

iss  

C

oss  

C

rss  

*Note: I

D

= 11.5A  
15 20  
0.1  
1
10  
30  
0
5
10  
25  
V

DS

, Drain-Source Voltage [V]  
Q

g

, Total Gate Charge [nC]  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
3

Typical Characteristics
(Continued)  
Figure 7. Breakdown Voltage Variation  
vs. Temperature  
Figure 8. On-Resistance Variation  
vs. Temperature  
2.8  
2.4  
2.0  
1.6  
1.2  
1.20  
1.15  
1.10  
1.05  
1.00  
0.95  
*Notes:  
1. V

GS

= 0V  
*Notes:  
1. V

GS

= 10V  
2. I

D

= 5.75A  
0.8  
0.90  
0.85  
2. I

D

= 250uA  
0.4  
-75 -50  
0
50  
100  
150  
-100  
-50  
0
50  
100  
150  
o
o
T

J

, Junction Temperature
[
C
]  
T

J

, Junction Temperature
[
C
]  
F i g u r e
 
9 .
 
M a x i m u m
 
S a f e
 
O p e r a t i n g
 
A r e a  
– FDPF12N50NZ  
F i g u r e
 
1 0 . M a x i m u m
 
S a f e
 
O p e r a t i n g
 
A r e a  
– FDP12N50NZ  
100  
100  
30
s  
100
s  
10
s  
100
s  
10  
10  
1ms  
1ms  
10ms  
10ms  
100 ms  
DC  
DC  
1
1
Operation in This Area  
Operation in This Area  
is Limited by R

DS(on)  

is Limited by R

DS(on)  

*Notes:  
1. T

C

= 25

o

C  
0.1  
* Notes :  
0.1  
1. T

C

= 25

o

C  
2. T

J

= 150

o

C  
2. T

J

= 150

o

C  
3. Single Pulse  
3. Single Pulse  
0.01  
0.01  
1
10  
100  
1000  
1
10  
100  
1000  
V

DS

, Drain-Source Voltage [V]  
V

DS

, Drain-Source Voltage [V]  
Figure 11. Maximum
 
Drain Current vs.
 
Case Temperature  
12  
10  
8
6
4
2
0
25  
50  
75  
100  
125  
150  
o
T

C

,
C
ase Temperature
[
C
]  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
4

Typical Characteristics
(Continued)  
Figure 12. Transient Thermal Response Curve
 
– FDP12N50NZ  
5
1
0.5  
0.2  
0.1
0.1  
P

DM  

0.05  
0.02  
0.01  
t

1  

t

2  

* Notes :  
1. Z

JC

(t) = 0.73

o

C/W Max.  
Single pulse  
0.01  
2. Duty Factor, D=t

1

/t

2  

3. T

JM

– T

C

= P

DM

* Z

JC

(t)  
0.001  
10

-5  

10

-4  

10

-3  

10

-2  

10

-1  

1
10  
t

1

, Square Wave Pulse Duration [sec]  
Figure 13. Transient Thermal Response Curve
 
– FDPF12N50NZ  
5
D=0.5  
1
0.2  
P

DM  

0.1  
t

1  

0.05  
10

-1  

10

-2  

t

2  

0.02  
0.01  
*Notes:  
1. Z

JC

(t) = 3.0

o

C/W Max.  
2. Duty Factor, D = t

1

/t

2  

3. T

JM

– T

C

= P

DM

* Z

JC

(t)  
single pulse  
10

-5  

10

-4  

10

-3  

10

-2  

10

-1  

1
10  
t

t

1

, Square Wave Pulse Duration [sec]  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
5

Figure 14. Gate Charge Test Circuit & Waveform  
I
= const.  
G
Figure 15. Resistive Switching Test Circuit & Waveforms  
R

L  

V

DS  

90%  
V

DS  

V

DD  

V

GS  

R

G  

10%  
V

GS  

DUT  
V
GS  
t

d(on)  

t

r  

t

d(off)  

t

f  

t

on  

t

off  

Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms  
V

GS  

©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
6

Figure 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
DUT  
V

DS  

_
I

SD  

L
Driver  
R

G  

Same Type  
as DUT  
V

DD  

V

GS  

• dv/dt controlled by
 
R

G  

• I

SD

controlled by pulse period  
Gate Pulse Width  
————————–  
V

GS  

D =  
Gate Pulse Period  
10V  
( Driver )  
I

FM

, Body Diode Forward Current  
I

SD  

di/dt  
( DUT )  
I

RM  

Body Diode Reverse Current  
Body Diode Recovery dv/dt  
V

SD  

V

DS  

( DUT )  
V

DD  

Body Diode  
Forward Voltage Drop  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
7

Mechanical Dimensions  
TO-220 3L  
Figure 18. TO-220, Molded, 3Lead, Jedec Variation AB  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-  
ically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
Dimension in Millimeters  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
8

Mechanical Dimensions  
TO-220F 3L  
Figure 19. TO220, Molded, 3LD, Full Pack, EIAJ SC91, Straight Lead  
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner  
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or  
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-  
ically the warranty therein, which covers Fairchild products.  
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:  
Dimension in Millimeters  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
9

TRADEMARKS  
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not  
intended to be an exhaustive list of all such trademarks.  
AccuPower™  
AX-CAP *  
BitSiC™  
Build it Now™  
CorePLUS™  
CorePOWER™  
CROSSVOLT
™  
CTL™  
F-PFS™  
FRFET  
Sync-Lock™  
®*  
®
®
®
tm  
®
Global Power Resource

SM  

GreenBridge™  
Green FPS™  
PowerTrench  
PowerXS™  
Programmable Active Droop™  
QFET  
QS™  
Quiet Series™  
RapidConfigure™  
™
®
TinyBoost  
TinyBuck  
®
®
Green FPS™ e-Series™  
G
max
™  
GTO™  
TinyCalc™  
®
TinyLogic  
TINYOPTO™  
TinyPower™  
TinyPWM™  
TinyWire™  
TranSiC™  
TriFault Detect™  
Current Transfer Logic™  
IntelliMAX™  
®
DEUXPEED  
ISOPLANAR™  
Marking Small Speakers Sound Louder  
and Better™  
MegaBuck™  
MICROCOUPLER™  
MicroFET™  
MicroPak™  
MicroPak2™  
MillerDrive™  
MotionMax™  
Dual Cool™  
®
EcoSPARK  
Saving our world, 1mW/W/kW at a time™  
SignalWise™  
SmartMax™  
EfficentMax™  
ESBC™  
®
TRUECURRENT *  
SerDes™  
SMART START™  
®
Solutions for Your Success™  
®
®
SPM  
Fairchild  
®
STEALTH™  
SuperFET  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
Fairchild Semiconductor  
FACT Quiet Series™  
®
®
UHC  
®
Ultra FRFET™  
UniFET™  
VCX™  
VisualMax™  
VoltagePlus™  
XS™  
®
mWSaver  
OptoHiT™  
OPTOLOGIC  
OPTOPLANAR  
FACT  
FAST  
®
®
FastvCore™  
FETBench™  
FPS™  
®
®
SupreMOS  
SyncFET™  
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE  
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY  
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY  
THEREIN, WHICH COVERS THESE PRODUCTS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE  
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used here in:  
1. Life
 
support devices or systems are devices or systems which, (a) are  
intended for surgical implant into the body or (b) support or sustain life,  
and (c) whose failure to perform when properly used in accordance with  
instructions for use provided in the labeling, can be reasonably  
expected to result in a significant injury of the user.  
2. A
 
critical component in any component of a life support, device, or  
system whose failure to perform can be reasonably expected to cause  
the failure of the life support device or system, or to affect its safety or  
effectiveness.  
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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,  
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their  
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PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Datasheet contains the design specifications for product development. Specifications  
may change in any manner without notice.  
Advance Information  
Formative / In Design  
Datasheet contains preliminary data; supplementary data will be published at a later  
date. Fairchild Semiconductor reserves the right to make changes at any time without  
notice to improve design.  
Preliminary  
First Production  
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to  
make changes at any time without notice to improve the design.  
No Identification Needed  
Obsolete  
Full Production  
Datasheet contains specifications on a product that is discontinued by Fairchild  
Semiconductor. The datasheet is for reference information only.  
Not In Production  
Rev. I66  
©2010 Fairchild Semiconductor Corporation  
FDP12N50NZ / FDPF12N50NZ Rev. C1  
10