onsemi-FDS2572
| Part # | onsemi-FDS2572 |
Download  | onsemi-FDS2572 |
July 2013
FDS2572
®
150V, 0.047 Ohms, 4.9A, N-Channel UltraFET
Trench MOSFET
General Description
Features
®
UltraFET devices
combine characteristics that enable
•
•
•
•
•
R
= 0.040
Ω
(Typ.), V
=
10V
DS(ON)
GS
benchmark efficiency in power conversion applications.
Optimized for Rds(on), low ESR, low total and Miller gate
charge, these devices are ideal for high frequency DC to
DC converters.
Q
= 29nC (Typ.), V
=
10V
g(TOT)
GS
Low Q
Body Diode
RR
Maximized efficiency at high frequencies
UIS Rated
Applications
•
•
•
•
DC/DC converters
Telecom and Data-Com Distributed Power Architectures
48-volt I/P Half-Bridge/Full-Bridge
24-volt Forward and Push-Pull topologies
D
5
6
7
8
4
3
2
1
D
D
D
G
SO-8
S
S
S
Pin 1
MOSFET Maximum Ratings
T =25°C
unless otherwise noted
A
Symbol
Parameter
Ratings
150
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
V
V
DSS
GS
±
20
Drain Current
o
o
4.9
3.1
A
A
Continuous (T
= 25
C, V
= 10V, R
= 50
C/W)
C
GS
θ
JA
I
D
o
o
Continuous (T
= 100
C, V
= 10V, R
= 50
C/W)
C
GS
θ
JA
Pulsed
Figure 4
A
Power dissipation
Derate above 25
C
2.5
20
W
mW/ C
P
o
o
D
o
T , T
Operating and Storage Temperature
-55 to 150
C
J
STG
Thermal Characteristics
o
R
R
R
Thermal Resistance Junction to Case
(NOTE1)
(NOTE2)
(NOTE2)
25
50
85
C/W
θ
JC
θ
JA
θ
JA
o
Thermal Resistance Junction to Case at 10 seconds
Thermal Resistance Junction to Case at steady state
C/W
o
C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape Width
12mm
Quantity
FDS2572
FDS2572
330mm
2500units
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
Electrical Characteristics
T =
25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250
µ
A, V
= 0V
150
–
–
–
–
–
V
VDSS
D
GS
V
V
V
= 120V
= 0V
–
–
–
1
DS
GS
GS
I
µ
A
nA
DSS
GSS
o
T
= 150
C
250
±
100
C
I
=
±
20V
On Characteristics
V
r
Gate to Source Threshold Voltage
V
I
= V
, I
= 250
µ
A
2
–
–
4
V
Ω
Ω
GS(TH)
GS
DS
D
Drain to Source On Resistance
Drain to Source On Resistance
= 4.9A, V
= 10V
0.040
0.044
0.047
0.053
DS(ON)
DS(ON)
D
GS
r
I
= 4.9A, V
= 6V
–
D
GS
Dynamic Characteristics
C
C
C
Input Capacitance
–
–
–
pF
pF
pF
2050
220
48
1.3
29
4
2870
310
80
3.0
38
6
ISS
V
= 25V, V
= 0V,
GS
DS
Output Capacitance
OSS
RSS
f = 1MHz
Reverse Transfer Capacitance
R
g
Ω
Gate Resistance
0.1
Q
Q
Q
Q
Q
Total Gate Charge at 10V
Threshold Gate Charge
V
V
= 0V to
10V
= 0V to 2V
–
–
–
–
–
nC
nC
nC
nC
nC
g(TOT)
g(TH)
gs
GS
GS
V
= 75V
DD
= 4.9A
I
D
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Gate Charge Threshold to Plateau
8
–
I =
1.0mA
g
6
–
gd
4
–
gs2
Switching Characteristics
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
–
–
–
–
–
–
–
27
ns
ns
ns
ns
ns
ns
ON
14
4
–
d(ON)
–
V
V
= 75V, I
= 4.9A
r
DD
GS
D
= 10V, R
= 10
Ω
Turn-Off Delay Time
Fall Time
44
22
–
–
–
G
d(OFF)
f
Turn-Off Time
100
OFF
Drain-Source Diode Characteristics
I
I
I
I
= 4.9A
= 3.1A
–
–
–
–
–
–
–
–
1.25
1.0
V
V
SD
SD
SD
SD
V
t
Source to Drain Diode Voltage
SD
Reverse Recovery Time
= 4.9A, dI
/dt =100A/
µ
s
= 4.9, dI
/dt =100A/
µ
s
72
ns
nC
rr
SD
Q
Reverse Recovered Charge
158
RR
Notes:
1. R
SD
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal referance is defined as the solder mounting surface of the
θ
JA
drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
θ
JC
θ
CA
2
2. R
is measured with 1.0in
copper on FR-4 board
θ
JA
FDS2572 Rev. C, July 2013
©2001 Fairchild Semiconductor Corporation
Typical Characteristic
1.2
1.0
0.8
0.6
0.4
0.2
0
6
4
2
0
V
= 10V
GS
0
25
50
75
100
125
150
25
50
75
T ,
CASE TEMPERATURE (
C)
C
100
125
150
o
o
T
, AMBIENT TEMPERATURE (
C)
A
Figure 1.
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
Maximum Continous Drain Current vs
Case Temperature
2
DUTY CYCLE – DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
NOTES:
DUTY FACTOR: D = t
/t
SINGLE PULSE
1
2
PEAK T
= P
J
x Z
x R
+ T
θ
JA A
DM
θ
JA
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3.
Normalized Maximum Transient Thermal Impedance
600
100
o
T
= 25
C
C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
o
ABOVE 25
C DERATE PEAK
CURRENT AS FOLLOWS:
V
= 10V
GS
150 – T
125
C
I = I
25
10
1
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
Figure 4.
Peak Current Capability
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
Typical Characteristic
(Continued)
10
30
20
10
0
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
o
STARTING T
= 25
C
J
V
= 15V
DD
o
o
STARTING T
= 150
C
T
= 25
C
J
J
1
o
T
= 150
C
J
If R = 0
= (L)(I
)/(1.3*RATED BV
o
T
= -55
C
t
– V
)
J
AV
AS
DSS
DD
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
– V
) +1]
DSS DD
t
AV
AS
0.1
3
4
5
6
160
160
0.001
0.1
1
10
100
t
, TIME IN AVALANCHE (ms)
V
, GATE TO SOURCE VOLTAGE (V)
AV
GS
Figure 5.
Unclamped Inductive Switching
Capability
Figure 6.
Transfer Characteristics
30
20
10
0
2.5
PULSE DURATION = 80
µ
s
V
= 10V
GS
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
0
V
= 5V
GS
V
= 6V
GS
V
= 4.5V
GS
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
V
= 10V, I
= 4.9A
D
GS
o
T
= 25
C
C
-80
-40
0
40
80
120
o
0
0.5
1.0
1.5
2.0
V
, DRAIN TO SOURCE VOLTAGE (V)
T ,
JUNCTION TEMPERATURE (
C)
J
DS
Figure 7.
Saturation Characteristics
Figure 8.
Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
1.2
1.0
0.8
0.6
0.4
1.2
V
= V
, I
= 250
µ
A
I =
250
µ
A
D
GS
DS
D
1.1
1.0
0.9
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
o
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
Figure 9.
Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10.
Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
Typical Characteristic
(Continued)
5000
10
8
C
=
C +
C
GS GD
ISS
V
= 75V
DD
1000
100
10
C
≅
C +
C
DS GD
OSS
6
C
=
C
GD
RSS
4
WAVEFORMS IN
DESCENDING ORDER:
2
I
I
= 4.9A
= 1A
D
D
V
=
0V, f
=
1MHz
GS
0
0.1
1
10
150
0
5
10
15
20
25
30
35
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Q ,
GATE CHARGE (nC)
g
Figure 11.
Capacitance vs Drain to Source
Voltage
Figure 12.
Gate Charge Waveforms for Constant
Gate Currents
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
V
L
DS
I
AS
V
VARY t
TO OBTAIN
P
DD
+
–
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01
Ω
t
AV
Figure 13.
Unclamped Energy Test Circuit
Figure 14.
Unclamped Energy Waveforms
D1
V
DS
V
Q
DD
g(TOT)
V
DS
L
V
= 10V
GS
V
GS
+
–
V
DD
V
GS
DUT
V
= 2V
GS
Q
gs2
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 15.
Gate Charge Test Circuit
Figure 16.
Gate Charge Waveforms
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
Test Circuits and Waveforms
(Continued)
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
–
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 17.
Switching Time Test Circuit
Figure 18.
Switching Time Waveforms
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
, and the
thermal resistance of the heat dissipating path
determines the maximum allowable device power
utilizing the normalized maximum transient thermal
impedance curve.
JM
Thermal resistances corresponding to other copper
areas can be obtained from Figure 19 or by calculation
using Equation 2. The area, in square inches is the top
copper area including the gate and source pads.
dissipation, P
, in an application.
Therefore the
DM
o
application’s ambient temperature, T
( C), and thermal
A
o
resistance R
( C/W) must be reviewed to ensure that
θ
JA
T
is never exceeded.
Equation 1 mathematically
JM
represents the relationship and serves as the basis for
establishing the rating of the part.
26
R
=
64 +
–
————————–
–
–
(EQ. 2)
θ
JA
0.23 +
Area
(
T
–
T
)
A
JM
R
(EQ. 1)
P
=
–
—————————-
DM
The transient thermal impedance (Z
) is also effected
θ
JA
θ
JA
by varied top copper board area. Figure 20 shows the
effect of copper pad area on single pulse transient
thermal impedance. Each trace represents a copper pad
area in square inches corresponding to the descending
list in the graph. Spice and SABER thermal models are
provided for each of the listed pad areas.
In using surface mount devices such as the SO8
package, the environment in which it is applied will have
a significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P
is complex and influenced by many factors:
DM
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms.
For pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and
RTHERM1 through RTHERM5 remain constant for each
of the thermal models. A listing of the model component
values is available in Table 1.
1. Mounting pad area onto which the device is attached
and whether there is copper on one side or both sides
of the board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 64 + 26/(0.23+Area)
θ
JA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the
part, the board and the environment they are in.
150
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 19
100
50
defines the R
for the device as a function of the top
θ
JA
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000
seconds of steady state power with no air flow. This
graph provides the necessary information for calculation
of the steady state junction temperature or power
dissipation. Pulse applications can be evaluated using
the Fairchild device Spice thermal model or manually
0.001
0.01
0.1
1
2
10
AREA, TOP COPPER AREA (in )
Figure 19.
Thermal Resistance vs Mounting
Pad Area
150
COPPER BOARD AREA – DESCENDING ORDER
2
0.04 in
2
0.28 in
120
2
0.52 in
0.76 in
1.00 in
2
2
90
60
30
0
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 20.
Thermal Impedance vs Mounting Pad Area
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
PSPICE Electrical Model
.SUBCKT FDS2572 2 1 3 ;
CA 12 8
8e-10
rev August 2001
Cb 15 14 8e-10
Cin 6 8 2e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
ESLC
Ebreak 11 7 17 18 157.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
11
51
–
+
50
–
17
18
–
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
+
16
21
–
19
8
MWEAK
LGATE
EVTEMP
It 8 17 1
RGATE
GATE
1
+
6
–
18
22
MMED
9
20
Lgate 1 9 5.61e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 1.98e-9
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
RLSOURCE
S1A
S2A
S2B
RBREAK
12
15
13
14
13
17
18
8
Mstro 16 6 8 8 MstroMOD
Mmed 16 6 8 8 MmedMOD
Mweak 16 21 8 8 MweakMOD
RVTEMP
19
S1B
13
CB
CA
IT
14
–
+
+
VBAT
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.1e-2
Rgate 9 20 1.47
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
6
8
5
8
EGS
EDS
+
–
–
8
22
RVTHRES
Rsource 8 7 RsourceMOD 1.5e-2
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50
VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*65),3))}
.MODEL DbodyMOD D (IS=4e-11 N=1.131 RS=4.4e-3 TRS1=2e-3 TRS2=1e-6
+ CJO=1.44e-9 M=0.67 TT=7.4e-8 XTI=4.2)
.MODEL DbreakMOD D (RS=0.38 TRS1=2e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=5e-10 IS=1e-30 N=10 M=0.7)
.MODEL MstroMOD NMOS (VTO=4.05 KP=85 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.35 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.47)
.MODEL MweakMOD NMOS (VTO=2.76 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14.7 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-3e-7)
.MODEL RdrainMOD RES (TC1=1e-2 TC2=3e-5)
.MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=4.5e-3 TC2=1e-6)
.MODEL RvtempMOD RES (TC1=-5e-3 TC2=2e-6)
.MODEL RvthresMOD RES (TC1=-3e-3 TC2=-1.4e-5)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-10 VOFF=-2)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-10)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.8)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
SABER Electrical Model
REV August 2001
template FDS2572 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod =
(isl=4e-11,nl=1.131,rs=4.4e-3,trs1=2e-3,trs2=1e-6,cjo=1.44e-9,m=0.67,tt=7.4e-8,xti=4.2)
dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6)
dp..model dplcapmod =
(cjo=5e-10,isl=10e-30,nl=10,m=0.7)
m..model mstrongmod = (type=_n,vto=4.05,kp=85,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.35,kp=5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod =
(ron=1e-5,roff=0.1,von=-10,voff=-2)
sw_vcsp..model s1bmod =
(ron=1e-5,roff=0.1,von=-2,voff=-10)
sw_vcsp..model s2amod =
(ron=1e-5,roff=0.1,von=-0.8,voff=0.3)
LDRAIN
sw_vcsp..model s2bmod =
(ron=1e-5,roff=0.1,von=0.3,voff=-0.8)
c.ca n12 n8 = 8e-10
c.cb n15 n14 = 8e-10
DPLCAP
5
DRAIN
2
10
RLDRAIN
RSLC1
51
c.cin n6 n8 = 2e-9
RSLC2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
ISCL
DBREAK
11
50
–
RDRAIN
6
8
ESG
spe.ebreak n11 n7 n17 n18 = 157.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
DBODY
EVTHRES
+
16
21
+
–
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
+
6
–
18
22
EBREAK
+
MMED
9
20
MSTRO
17
18
–
spe.evtemp n20 n6 n18 n22 = 1
RLGATE
LSOURCE
CIN
SOURCE
3
8
7
i.it n8 n17 = 1
RSOURCE
RLSOURCE
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1.98e-9
S1A
12
S2A
RBREAK
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
–
–
8
22
RVTHRES
res.rbreak n17 n18
= 1, tc1=1.1e-3,tc2=-3e-7
res.rdrain n50 n16
= 2.1e-2, tc1=1e-2,tc2=3e-5
res.rgate n9 n20 = 1.47
res.rslc1 n5 n51
= 1e-6, tc1=3e-3,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 1.5e-2, tc1=4.5e-3,tc2=1e-6
res.rvthres n22 n8
= 1, tc1=-3e-3,tc2=-1.4e-5
res.rvtemp n18 n19
= 1, tc1=-5e-3,tc2=2e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/65))** 3))
}
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
SPICE Thermal Model
JUNCTION
th
REV August 2001
FDS2572
Copper Area = 1 in
2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2.0e-1
CTHERM7 3 2 1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
CTHERM8 2 TL 3
RTHERM1 TH 8 1.0e-1
RTHERM2 8 7 5.0e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
6
5
SABER Thermal Model
Copper Area = 1 in
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 =2.0e-3
ctherm.ctherm2 c2 c3 =5.0e-3
ctherm.ctherm3 c3 c4 =1.0e-2
ctherm.ctherm4 c4 c5 =4.0e-2
ctherm.ctherm5 c5 c6 =9.0e-2
ctherm.ctherm6 c6 c7 =2.0e-1
ctherm.ctherm7 c7 c8 =1
ctherm.ctherm8 c8 tl =3
4
3
2
rtherm.rtherm1 th c2 =1.0e-1
rtherm.rtherm2 c2 c3 =5.0e-1
rtherm.rtherm3 c3 c4 =1
rtherm.rtherm4 c4 c5 =5
rtherm.rtherm5 c5 c6 =8
rtherm.rtherm6 c6 c7 =12
rtherm.rtherm7 c7 c8 =18
rtherm.rtherm8 c8 tl =25
}
tl
CASE
TABLE 1. THERMAL MODELS
2
2
2
2
2
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in
1.2e-1
0.5
0.28 in
0.52 in
0.76 in
1.0 in
1.5e-1
1.0
2.0e-1
1.0
2.0e-1
1.0
2.0e-1
1.0
3.0
12
1.3
2.8
3.0
3.0
26
20
15
13
39
24
21
19
18
55
38.7
31.3
29.7
25
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
INCHES
MIN MAX
MILLIMETERS
E
E
A
SYMBOL
NOTES
A
1
1
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
0.0532 0.0688
0.004 0.0098
–
–
e
A
1
D
b
0.013
0.020
–
b
c
D
E
0.0075 0.0098
0.189 0.1968
0.2284 0.244
0.1497 0.1574
0.050 BSC
–
2
–
o
h x 45
c
E
3
–
1
e
1.27 BSC
0.004 IN
0.10 mm
L
o
o
H
0.0099 0.0196
0.25
0.40
0.50
1.27
–
0 -8
0.060
1.52
L
0.016
0.050
4
NOTES:
1. All
dimensions are within allowable dimensions of
Rev. C of JEDEC MS-012AA outline dated 5-90.
0.050
1.27
2. Dimension
“D” does not include mold flash, protru-
sions or gate burrs. Mold flash, protrusions or gate
burrs shall not exceed 0.006 inches (0.15mm) per
side.
0.024
0.6
0.155
4.0
0.275
7.0
3. Dimension
“E ”
does not include inter-lead flash or
1
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
protrusions. Inter-lead flash and protrusions shall
not exceed 0.010 inches (0.25mm) per side.
4. “L”
is the length of terminal for soldering.
5. The
chamfer on the body is optional. If it is not
present, a visual index feature must be located with-
in the crosshatched area.
6. Controlling
dimension: Millimeter.
7. Revision
8 dated 5-99.
4.0mm
2.0mm
USER DIRECTION OF FEED
MS-012AA
12mm TAPE AND REEL
1.5mm
DIA. HOLE
1.75mm
C
L
12mm
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
50mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
12.4mm
©2001 Fairchild Semiconductor Corporation
FDS2572 Rev. C, July 2013
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Rev. I64
