onsemi-FDS6162N7
| Part # | onsemi-FDS6162N7 |
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May 2003
FDS6162N7
20V N-Channel PowerTrench
MOSFET
General Description
Features
This N-Channel MOSFET has been designed
specifically to improve the overall efficiency of DC/DC
converters using either synchronous or conventional
switching PWM controllers.
It has been optimized for
“low side” synchronous rectifier operation, providing an
extremely low R
DS(ON)
in a small package.
•
23 A, 20 V
R
DS(ON)
= 3.5 m
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 5.0 m
Ω
@ V
GS
= 2.5 V
•
High performance trench technology for extremely
low R
DS(ON)
Applications
•
High power and current handling capability
•
Fast switching
•
Synchronous rectifier
•
DC/DC converter
•
FLMP SO-8 package:
Enhanced thermal
performance in industry-standard package size
Bottom-side
Drain Contact
5
6
7
8
4
3
2
1
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
20
±
12
V
V
A
V
GSS
I
D
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
(Note 1a)
(Note 1a)
23
60
3.0
Power Dissipation
P
D
W
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°
C
Thermal Characteristics
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
40
0.5
R
θ
JA
R
θ
JC
°
C/W
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDS6162N7
FDS6162N7
13’’
12mm
2500 units
FDS6162N7 Rev
C2 (W)
2002 Fairchild Semiconductor Corporation
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max
Units
Off Characteristics
Drain–Source Breakdown
20
V
V
GS
= 0 V,
I
D
= 250
µ
A
BV
DSS
Voltage
∆
BV
DSS
Breakdown Voltage Temperature
13
I
D
= 250
µ
A, Referenced to 25
°
C
mV/
°
C
Coefficient
∆
T
J
I
DSS
I
GSSF
I
GSSR
Zero Gate Voltage Drain Current
V
DS
= 16 V,
V
GS
= 0 V
V
DS
= 0 V
V
DS
= 0 V
1
µ
A
nA
nA
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V
GS
= 12 V,
V
GS
= –12 V ,
100
–100
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
0.6
0.9
–4
1.5
V
V
DS
= V
GS
I
D
= 250
µ
A, Referenced to 25
°
C
,
I
D
= 250
µ
A
∆
V
GS(th)
Gate Threshold Voltage
mV/
°
C
Temperature Coefficient
Static Drain–Source
On–Resistance
∆
T
J
R
DS(on)
V
GS
= 4.5 V,
V
GS
= 2.5 V,
I
D
= 23 A
I
D
= 19 A
2.9
3.6
4.1
3.5
5.0
6.2
m
Ω
V
GS
= 4.5 V,
I
D
= 23 A,T
J
= 125
°
C
g
FS
Forward Transconductance
V
DS
= 5 V,
I
D
= 23 A
119
S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
5521
1473
706
pF
pF
pF
Ω
V
DS
= 10 V,
V
GS
= 0 V,
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
f = 1.0 MHz
V
GS
= 15 mV,
f = 1.0 MHz
1.3
Switching Characteristics
(Note 2)
V
DD
= 10 V,
I
D
= 1 A,
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
20
25
85
55
52
9
32
40
136
88
ns
ns
ns
V
GS
= 4.5
V,
R
GEN
= 6
Ω
ns
V
DS
= 10 V,
V
GS
= 4.5 V
I
D
= 23 A,
Q
g
Q
gs
Q
gd
73
nC
nC
nC
14.5
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
2.5
1.2
A
V
Drain–Source Diode Forward
V
GS
= 0 V,
I
S
= 2.5 A
(Note 2)
0.6
V
SD
t
rr
Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
I
F
= 23 A,
d
iF
/d
t
= 100 A/µs
42
52
nS
nC
Q
rr
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins.
R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user’s board design.
a)
40°C/W when
b)
85°C/W when mounted on
a minimum pad of 2 oz
copper
mounted on a 1in
2
pad
of 2 oz copper
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%
FDS6162N7 Rev C2 (W)
Typical Characteristics
60
2
1.8
1.6
1.4
1.2
1
V
GS
=4.5V
3.0V
2.5V
2.0V
50
40
30
20
10
0
V
GS
= 2.0V
2.5V
3.0V
30
3.5V
4.5V
1.5V
0.8
0.00
0.25
0.50
0.75
1.00
1.25
150
2
0
15
45
60
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.012
1.6
I
D
= 23 A
I
D
= 11.5 A
V
GS
= 4.5V
0.01
0.008
0.006
0.004
0.002
1.4
1.2
1
T
A
= 125
o
C
T
A
= 25
o
C
0.8
0.6
-50
-25
0
25
50
75
100
125
1
2
3
4
5
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
withTemperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
60
50
40
30
20
10
0
V
GS
= 0V
V
DS
= 5V
10
1
T
A
= 125
o
C
25
o
C
0.1
-55
o
C
0.01
0.001
0.0001
T
A
=125
o
C
25
o
C
-55
o
C
1
1.2
1.4
1.6
1.8
0
0.2
0.4
0.6
0.8
1
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDS6162N7 Rev C2 (W)
Typical Characteristics
8000
6000
4000
2000
0
5
V
DS
= 5V
f = 1MHz
GS
= 0 V
I
D
= 23 A
V
10V
4
3
2
1
0
15V
C
ISS
C
OSS
C
RSS
0
5
10
15
20
0
10
20
30
40
50
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
1000
100
10
50
SINGLE PULSE
R
θ
JA
= 85°C/W
T
A
= 25°C
R
DS(ON)
LIMIT
40
30
20
10
0
100µs
1ms
10ms
100ms
1s
10s
DC
1
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 85
o
C/W
T
A
= 25
o
C
0.1
0.01
0.01
0.1
1
10
100
0.01
0.1
1
10
100
1000
V
DS
, DRAIN-SOURCE VOLTAGE (V)
t
1
, TIME (sec)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
1.00
D = 0.5
R
R
θ
JA
(t) = r(t) * R
θ
JA
θ
JA
= 85 °C/W
0.2
0.1
0.10
0.05
P(pk)
0.02
t
1
0.01
t
2
0.01
T
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.00
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDS6162N7 Rev C2 (W)
Dimensional Outline and Pad Layout
FDS6162N7 Rev C2 (W)
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarksꢀ
ACEx
PACMAN
POP
Power247
PowerTrench
QFET
QS
SPM
Stealth
SuperSOT-3
SuperSOT-6
SuperSOT-8
ImpliedDisconnect
ISOPLANAR
LittleFET
MicroFET
MicroPak
MICROWIRE
MSX
FACT
ActiveArray
Bottomless
CoolFET
CROSSVOLT
DOME
EcoSPARK
E
2
CMOS
TM
EnSigna
TM
FACT Quiet Series
â
FAST
â
FASTr
FRFET
GlobalOptoisolator
GTO
HiSeC
I
2
C
SyncFET
â
QT Optoelectronics
TinyLogic
Quiet Series
RapidConfigure
RapidConnect
TruTranslation
UHC
UltraFET
MSXPro
OCX
â
OCXPro
OPTOLOGIC
Across the board
ꢀ
A
round the worldꢀ
The Power Franchise
Programmabl
e
A
ctive Droop
â
â
SILENT SWITCHER
VCX
SMAR
T
S
TART
OPTOPLANAR
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE T
O
A
NY PRODUCTS HEREIN TO IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGNꢀ FAIRCHILD
DOES NO
T
A
SSUM
E
A
NY LIABILIT
Y
A
RISING OUT OF TH
E
A
PPLICATION OR USE O
F
A
NY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERSꢀ
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATIONꢀ
As used herein:
1ꢀ Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
userꢀ
2ꢀ A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectivenessꢀ
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product developmentꢀ Specifications may change in
any manner without noticeꢀ
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later dateꢀ
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
designꢀ
No Identification Needed
Obsolete
Full Production
This datasheet contains final specificationsꢀ Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve designꢀ
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductorꢀ
The datasheet is printed for reference information onlyꢀ
Revꢀ I2
