onsemi-FDS6612A
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FDS6612A
Single N-Channel, Logic-Level, PowerTrench
MOSFET
General Description
Features
This
produced
N-Channel
using
Logic
ON
Level
MOSFET
Semiconductor’s
is
•
8.4 A, 30 V.
R
DS(ON)
= 22 m
Ω
@ V
GS
= 10 V
R
DS(ON)
= 30 m
Ω
@ V
GS
= 4.5 V
advanced PowerTrench process that has been
especially tailored to
minimize the on-state resistance
and yet maintain
superior switching performance.
•
Fast switching speed
•
Low gate charge
These devices are well suited for low voltage
and battery
powered applications where low in-line
power loss and fast switching are required.
•
High performance trench technology for extremely
low R
DS(ON)
•
High power and current handling capability
D
5
6
7
8
4
3
2
1
D
D
D
G
SO-8
S
S
S
Pin 1
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol
V
DSS
Parameter
Drain-Source Voltage
Ratings
Units
30
V
V
A
V
GSS
Gate-Source Voltage
±
20
8.4
I
D
Drain Current
– Continuous
– Pulsed
(Note 1a)
40
2.5
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
P
D
W
1.0
E
AS
mJ
Single Pulse Avalanche Energy
(Note 3)
24
T
J
, T
STG
Operating and Storage Junction Temperature Range
–55 to +150
°
C
Thermal Characteristics
Thermal Resistance, Junction-to-Ambient
(Note 1a)
(Note 1b)
(Note 1)
50
125
25
R
θ
JA
R
θ
JA
R
θ
JC
°
C/W
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
2500 units
FDS6612A
FDS6612A
13’’
12mm
Publication Order Number
:
©
2007 Semiconductor Components Industries, LLC.
FDS6612A/D
October-2017, Rev. 4
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BV
DSS
Drain–Source Breakdown Voltage
30
V
V
GS
= 0 V,
I
D
= 250
µ
A, Referenced to 25
°
C
V
DS
= 24 V,
V
GS
= 0 V
V
DS
= 24 V, V
GS
= 0 V, T
J
=55
°
C
GS
=
±
20 V,
V
DS
= 0 V
I
D
= 250
µ
A
∆
BV
DSS
∆
T
J
Breakdown Voltage Temperature
Coefficient
26
mV/
°
C
I
DSS
Zero Gate Voltage Drain Current
1
µ
A
µ
A
nA
10
I
GSS
Gate–Body Leakage
V
±
100
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
1
1.9
3
V
V
DS
= V
GS
,
I
D
= 250
µ
A
∆
V
GS(th)
Gate Threshold Voltage
Temperature Coefficient
I
D
= 250
µ
A, Referenced to 25
°
C
–4.4
mV/
°
C
m
Ω
∆
T
J
R
DS(on)
Static Drain–Source
On–Resistance
V
GS
= 10 V,
V
GS
= 4.5 V,
I
D
= 8.4 A
I
D
= 7.2 A
19
24
25
22
30
37
V
GS
= 10 V, I
D
= 8.4 A, T
J
=125
°
C
I
D(on)
g
FS
On–State Drain Current
V
GS
= 10 V,
V
DS
= 15 V,
V
DS
= 5 V
I
D
= 8.4 A
20
A
S
Forward Transconductance
30
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
560
140
55
pF
pF
pF
Ω
V
DS
= 15 V,
f = 1.0 MHz
V
GS
= 0 V,
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V
GS
= 15 mV,
f = 1.0 MHz
2.5
Switching Characteristics
(Note 2)
t
d(on)
t
r
t
d(off)
t
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
7
5
14
10
35
6
ns
ns
V
DD
= 15 V,
I
D
= 1 A,
R
GEN
= 6
Ω
V
GS
= 10 V,
22
3
ns
ns
Q
g
Q
gs
Q
gd
5.4
1.7
1.9
7.6
nC
nC
nC
V
DS
= 15 V,
V
GS
= 5 V
I
D
= 8.4 A,
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current
2.1
1.2
A
V
Drain–Source Diode Forward
Voltage
V
SD
V
GS
= 0 V,
I
S
= 2.1 A
(Note 2)
0.77
t
rr
Diode Reverse Recovery Time
19
9
nS
nC
I
F
= 8.4 A, d
iF
/d
t
= 100 A/µs
Q
rr
Diode Reverse Recovery Charge
Notes:
1.
R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins.
R
θ
JC
is guaranteed by design while R
θ
CA
is determined by the user’s board design.
a) 50°C/W
when mounted
on a 1in
2
pad of 2 oz
copper
b) 125°C/W
when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2
Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%
3
Starting TJ = 25°C, L = 1mH, I
AS
= 7A, V
DD
= 27V, V
GS
= 10V
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2
Typical Characteristics
40
2
1.8
1.6
1.4
1.2
1
V
GS
= 10V
4.5V
V
GS
= 3.5V
4.0V
30
20
10
0
6.0V
4.0V
3.5V
4.5V
5.0V
6.0V
10V
3.0V
2.5
0.8
0
0.5
1
1.5
2
3
0
10
20
I
D
, DRAIN CURRENT (A)
30
40
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
0.1
I
D
= 8.4A
V
GS
= 10V
I
D
= 4.2A
1.4
1.2
1
0.08
0.06
0.04
0.02
0
T
A
= 125
o
C
T
A
= 25
o
C
0.8
0.6
-50
-25
0
25
50
75
100
125
150
2
4
6
8
10
T
J
, JUNCTION TEMPERATURE (
o
C)
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
40
30
20
10
0
100
V
GS
= 0V
V
DS
= 5V
10
1
T
A
= 125
o
C
0.1
25
o
C
T
A
= 125
o
C
-55
o
C
0.01
0.001
0.0001
-55
o
C
25
o
C
0
0.2
0.4
0.6
0.8
1
1.2
1.5
2
2.5
3
3.5
4
4.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
SD
, BODY
DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
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.com
3
Typical Characteristics
10
800
600
400
200
0
f = 1 MHz
V
GS
= 0 V
I
D
= 8.4A
8
V
DS
= 10V
20V
C
iss
6
15V
4
2
0
C
oss
C
rss
0
2
4
6
8
10
12
0
5
10
15
20
25
30
Q
g
, GATE CHARGE (nC)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
100
100
10
1
100
µ
s
R
DS(ON)
LIMIT
1ms
10
10ms
100ms
1s
10s
1
DC
25
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 125
o
C/W
T
A
= 25
o
C
0.1
0.01
125
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
t
AV
, TIME IN AVALANCHE (mS)
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Unclamped Inductive Switching
Capability
50
40
30
20
10
0
SINGL
E
P
ULSE
R
θ
JA
= 125
o
C
/
W
T
A
= 25
o
C
0.001
0.01
0.1
1
10
100
t
1
, TIM
E
(
sec)
Figure 11. Single Pulse Maximum Power Dissipation.
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Typical Characteristics
1
D = 0.5
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 125
o
C/W
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
t
1
t
2
0.01
T
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
Figure 12. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
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5
PSPICE Electrical Model N-Channel
.SUBCKT FDS6612A
2 1 3
*NOM TEMP=25 DEG C
*REV A – JULY 2003
CA 12 8 1E-9
CB 15 14 4.0E-10
CIN 6 8 5.1E-10
L
D
R
A
I
N
D
P
L
C
A
P
5
DR
A
I
N
2
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
R
L
D
R
A
I
N
RS
L
C
1
51
DBRE
A
K
+
EBREAK 11 7 17 18 34.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RSLC2
5
51
ES
L
C
11
–
50
+
–
17
R
D
R
A
I
N
D
B
O
D
Y
6
8
EBRE
A
K 18
–
ESG
EVT
H
R
ES
+
16
21
+
–
19
8
IT 8 17 1
MWEAK
L
G
A
TE
EV
T
E
MP
R
G
A
T
E
G
A
T
E
1
+
6
18
22
–
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
MMED
9
20
MSTRO
8
RL
G
A
T
E
LSO
U
R
C
E
C
I
N
SOUR
C
E
3
7
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
R
S
O
U
R
C
E
RLS
O
U
R
CE
S1A
12
S2A
S2B
RB
R
E
AK
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
15
13
8
14
13
17
18
S
1
B
RVTEMP
19
–
13
CB
CA
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8E-3
RGATE 9 20 4.2
IT
14
+
+
VB
A
T
6
8
5
8
EGS
E
D
S
+
–
–
8
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
22
RVTH
R
E
S
RSOURCE 8 7 RSOURCEMOD 7.5E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50
VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))}
.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6
+ CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34)
.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7)
.MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
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emi.com
6
SPICE Thermal Model
.SUBCKT FDS6612A_THERM TH TL
*THERMAL MODEL SUBCIRCUIT
*REV A – JULY 2003
th
JUNCTION
*MIN PAD RJA
RTHERM1
RTHERM2
RTHERM3
CTHERM1
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
TH
8
7
6
5
4
3
2
8
7
6
5
4
3
2
TL
0.005
0.05
0.10
0.35
0.45
0.50
0.55
3.00
8
7
CTHERM2
CTHERM3
CTHERM4
CTHERM5
6
5
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
TH
8
7
6
5
4
3
2
8
7
6
5
4
3
2
TL
5.000
6.250
7.500
8.750
10.625
11.875
31.250
43.750
RTHERM4
RTHERM5
4
3
2
.ENDS
RTHERM6
RTHERM7
RTHERM8
CTHERM6
CTHERM7
CTHERM8
tl
AMBIENT
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7
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