onsemi-FDS8874
| Part # | onsemi-FDS8874 |
Download  | onsemi-FDS8874 |
April 2007
tm
FDS8874
N-Channel PowerTrench
®
MOSFET
30V, 16A, 5.5m
Ω
Features
General Description
r
DS(on)
= 5.5m
Ω
, V
GS
= 10
V
,
I
D
= 16A
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It
has been optimized for low gate charge, low
r
DS(on)
= 7.0m
Ω
, V
GS
= 4.5V, I
D
= 15A
High performance trench technology for extremely low
r
DS(on)
r
DS(on)
and fast switching speed.
Applications
Low gate charge
DC/DC converters
High power and current handling capability
100% Rg tested
RoHS Compliant
D
D
5
6
7
8
4
3
2
1
D
D
G
SO-8
S
S
Pin 1
S
MOSFET Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GS
Parameter
Ratings
30
±20
Units
V
V
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (T
A
= 25
o
C, V
GS
= 10V, R
θ
JA
= 50
o
C/W)
Continuous (T
A
= 25
o
C, V
GS
= 4.5V, R
θ
JA
= 50
o
C/W)
Pulsed
16
15
115
A
A
A
I
D
E
AS
Single Pulse Avalanche Energy (Note 1)
Power dissipation
265
2.5
20
mJ
W
P
D
Derate above 25
o
C
mW/
o
C
o
C
T
J
, T
STG
Operating and Storage
T
e
mperature
-55 to 150
Thermal Characteristics
R
θ
JC
R
θ
JA
R
θ
JA
Thermal Resistance, Junction to Case (Note 2)
25
50
125
o
C/W
o
C/W
o
C/W
Thermal Resistance, Junction to Ambient (Note 2a)
Thermal Resistance, Junction to Ambient (Note 2b)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
330mm
Tape Width
12mm
Quantity
2500 units
FDS8874
FDS8874
SO-8
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
1
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
VDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= 250
µ
A, V
GS
= 0V
30
–
–
–
–
–
–
–
1
250
±100
V
V
DS
= 24V
V
GS
= 0V
I
DSS
µ
A
nA
T
J
= 150
o
C
I
GSS
V
GS
= ±20V
–
On Characteristics
V
GS(TH)
Gate to Source Threshold Voltage
V
GS
= V
DS
, I
D
= 250
µ
A
I
D
= 16A, V
GS
= 10V
I
D
= 15A, V
GS
= 4.5V
1.2
–
–
–
2.5
5.5
7.0
V
4.9
5.6
r
DS(on)
Drain to Source On Resistance
m
Ω
I
D
= 16A, V
GS
= 10
V
,
–
7.8
10.2
T
J
= 150
o
C
Dynamic Characteristics
C
ISS
C
OSS
C
RSS
R
G
Input Capacitance
–
–
–
3000
600
350
1.5
56
3990
800
525
4.0
72
38
–
pF
pF
pF
Ω
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V
GS
= 0.5V, f = 1MHz
0.4
Q
g(TOT)
Q
g(5)
Q
gs
Q
gs2
Q
gd
T
o
tal Gate Charge at 10V
T
o
tal Gate Charge at 5V
Gate to Source Gate Charge
Gate Charge Threshold to Plateau
Gate to Drain “Miller” Charge
V
GS
= 0V to 10V
V
GS
= 0V to 5V
I
D
= 16A
–
–
–
–
–
nC
nC
nC
nC
nC
V
DD
= 15V
30
8.0
5.0
10
–
–
Switching Characteristics
(V
GS
= 10V)
t
ON
t
d(ON)
t
r
Turn-On Time
Turn-On Delay Time
Rise Time
–
–
–
–
–
–
–
9
45
54
20
–
81
–
–
–
–
ns
ns
ns
ns
ns
ns
V
DD
= 15V, I
D
= 16A
V
GS
= 10V, R
GS
= 4.7
Ω
t
d(OFF)
t
f
Turn-Off Delay Time
Fall Time
t
OFF
Turn-Off Time
111
Drain-Source Diode Characteristics
I
SD
= 16A
I
SD
= 2.1A
I
SD
= 16A, dI
SD
/dt = 100A/
µ
s
I
SD
= 16A, dI
SD
/dt = 100A/
µ
s
–
–
–
–
–
–
–
–
1.25
1.0
28
V
V
ns
nC
V
SD
Source to Drain Diode Voltage
t
rr
Reverse Recovery Time
Q
RR
Reverse Recovered Charge
13
Notes:
1:
Starting T
= 25°C, L = 1mH, I
= 23A, V
= 30V, V
= 10V.
J
AS
DD
GS
2:
R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
θ
JA
drain pins.
R
is guaranteed by design while R
is determined by the user’s board design.
θ
JA
θ
JC
2
a) 50°C/W when mounted on a 1in
pad of 2 oz copper.
b) 125°C/W when mounted on a minimum pad.
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
2
Typical Characteristics
T
J
= 25°C unless otherwise noted
20
15
10
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 4.5V
V
= 10V
GS
GS
5
0
o
R
=50 C/W
θ
JA
0
25
50
75
100
125
150
25
50
75
100
125
150
o
o
T
, AMBIENT TEMPERATURE (
C)
T
, AMBIENT TEMPERATURE (
C)
A
A
Figure 1.
Normalized Power Dissipation vs
Ambient Temperature
Figure 2.
Maximum Continuous Drain Current vs
Ambient Temperature
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.001
SINGLE PULSE
R
θ
JA
= 125
o
C/W
0.0001
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t, RECTANGULAR PULSE DURATION (s)
Figure 3.
Normalized Maximum Transient Thermal Impedance
3000
1000
V
GS
= 10V
SINGLE PULSE
R
θ
JA
= 125
o
C/W
T
A
= 25
o
C
100
10
1
0.5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t, PULSE WIDTH (s)
Figure 4.
Single Pulse Maximum Power Dissipation
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
3
Typical Characteristics
T
J
= 25°C unless otherwise noted
100
50
40
30
20
10
0
PULSE DURATION = 80
µ
s
If R = 0
= (L)(I
)/(1.3*RATED BV
t
AV
– V
)
DUTY CYCLE = 0.5% MAX
AS
DSS
DD
If R
≠
0
= (L/R)ln[(I
*R)/(1.3*RATED BV
V
= 15V
DD
t
– V
) +1]
DD
AV
AS
DSS
o
T
= 25
C
J
o
STARTING T
= 25
C
J
10
o
o
T
= 150
C
J
STARTING T
= 150
C
J
o
T
= -55
C
J
1
1.5
2.0
2.5
3.0
0.1
1
10
100
t
, TIME IN AVALANCHE (ms)
V
, GATE TO SOURCE VOLTAGE (V)
AV
GS
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5.
Unclamped Inductive Switching
Capability
Figure 6.
Transfer Characteristics
50
14
PULSE DURATION = 80
µ
s
V
= 4V
V
V
= 10V
GS
I =
16A
D
GS
DUTY CYCLE = 0.5% MAX
40.
30
20
10
0
12
10
8
V
= 5V
= 3V
GS
GS
V
= 2.5V
GS
o
6
T
= 25
C
A
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5% MAX
4
0
0.1
0.2
0.3
0.4
2
4
V ,
GATE TO SOURCE VOLTAGE (V)
GS
6
8
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7.
Saturation Characteristics
Figure 8.
Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.6
1.4
1.2
1.0
0.8
0.6
1.4
PULSE DURATION = 80
µ
s
V
= V
, I
= 250
µ
A
DS D
GS
DUTY CYCLE = 0.5% MAX
1.2
1.0
0.8
0.6
0.4
V
= 10V, I
= 16A
D
GS
-80
-40
0
40
80
120
o
160
-80
-40
0
40
80
120
160
o
T ,
JUNCTION TEMPERATURE (
C)
T ,
JUNCTION TEMPERATURE (
C)
J
J
Figure 9.
Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10.
Normalized Gate Threshold Voltage vs
Junction Temperature
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
4
Typical Characteristics
T
J
= 25°C unless otherwise noted
1.10
1.05
1.00
5000
I
= 250
µ
A
D
C
C
=
C +
C
GS GD
ISS
≅
C +
C
OSS
DS
GD
1000
C
=
C
GD
RSS
0.95
0.90
V
= 0
V
, f =
1
MHz
GS
100
-80
-40
0
40
80
120
160
0.1
1
10
30
o
T ,
JUNCTION TEMPERATURE (
C)
V
, DRAIN TO SOURCE VOLTAGE (V)
J
DS
Figure 11.
Normalized Drain to Source
Figure 12.
Capacitance vs Drain to Source
Voltage
Breakdown Voltage vs Junction Temperature
200
100
10
V
= 15V
DD
100us
1ms
8
6
4
2
0
10
1
10ms
THIS AREA IS
LIMITED BY r
100ms
DS(on)
1s
10s
DC
SINGLE PULSE
T
J
= MAX RATED
R
0.1
WAVEFORMS IN
θ
JA
= 125
o
C/W
DESCENDING ORDER:
I
I
= 16A
= 1A
T
A
= 25
o
C
0.1
V
DS
, DRAIN to SOURCE VOLTAGE (V)
D
D
0.01
0.01
1
10
100
0
10
20
30
40
50
60
Q ,
GATE CHARGE (nC)
g
Figure 13.
Gate Charge Waveforms for Constant
Gate Currents
Figure 14.
Forward Bias Safe Operating Area
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
5
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t
TO OBTAIN
P
+
–
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01
Ω
t
AV
Figure 15.
Unclamped Energy Test Circuit
Figure 16.
Unclamped Energy Waveforms
V
DS
V
Q
DD
g(TOT)
V
V
GS
DS
L
V
= 10V
GS
Q
g(5)
V
GS
+
–
Q
gs2
V
= 5V
GS
V
DD
DUT
V
= 1V
GS
I
g(REF)
0
Q
g(TH)
Q
Q
gs
gd
I
g(REF)
0
Figure 17.
Gate Charge Test Circuit
Figure 18.
Gate Charge Waveforms
V
DS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
R
t
t
f
L
r
V
DS
90%
90%
+
–
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19.
Switching Time Test Circuit
Figure 20.
Switching Time Waveforms
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
6
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2.
The area, in square inches is the top copper
area including the gate and source pads.
application.
Therefore the application’s ambient
temperature, T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
26
R
=
64
+
——————————-
(EQ. 2)
θ
JA
0.23 +
Area
(
T
–
T
)
JM
A
(EQ. 1)
P
=
–
—————————–
DM
R
θ
JA
The transient thermal impedance (Z
θ
JA
) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal imped-
ance. Each trace represents a copper pad area in square
inches corresponding to the descending list in the graph.
Spice and SABER thermal models are provided for each of
the listed pad areas.
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
200
5. Air flow and board orientation.
R
= 64 + 26/(0.23+Area)
θ
JA
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
Fairchild provides thermal information to assist the design-
er’s preliminary application evaluation. Figure 21 defines the
100
50
R
θ
JA
for the device as a function of the top copper (compo-
nent side) area. This is for a horizontally positioned FR-4
board with 1oz copper after 1000 seconds of steady state
power with no air flow. This graph provides the necessary in-
formation for calculation of the steady state junction temper-
ature or power dissipation. Pulse applications can be
evaluated using the Fairchild device Spice thermal model or
manually utilizing the normalized maximum transient
0.001
0.01
0.1
1
2
10
AREA, TOP COPPER AREA (in
)
Figure 21.
Thermal Resistance vs Mounting
Pad Area
150
COPPER BOARD AREA – DESCENDING ORDER
2
0.04 in
2
0.28 in
0.52 in
0.76 in
1.00 in
120
90
60
30
0
2
2
2
-1
0
1
2
3
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
Figure 22.
Thermal Impedance vs Mounting Pad Area
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
7
PSPICE Electrical Model
.SUBCKT FDS8874 2 1 3 ;
Ca 12 8 2.4e-9
rev May 2004
Cb 15 14 2.4e-9
Cin 6 8 2.6e-9
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
Ebreak 11 7 17 18 33.5
Eds 14 8 5 8 1
RSLC1
51
DBREAK
11
+
Egs 13 8 6 8 1
RSLC2
5
Esg 6 10 6 8 1
ESLC
51
–
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
+
50
–
17
DBODY
RDRAIN
6
8
18
EBREAK
MWEAK
ESG
It 8 17 1
–
EVTHRES
+
16
21
+
–
19
Lgate 1 9 4e-9
LGATE
EVTEMP
8
RGATE
GATE
1
Ldrain 2 5 1.0e-9
Lsource 3 7 1e-10
+
6
–
18
MMED
22
9
20
MSTRO
8
RLGATE
RLgate 1 9 40
RLdrain 2 5 10
RLsource 3 7 1
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
S2A
RBREAK
12
15
13
14
17
18
8
13
RVTEMP
19
S1B
S2B
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 2.35e-3
Rgate 9 20 1.9
13
CB
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
+
–
–
8
22
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50
VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=7E-12 IKF=10 N=1.01 RS=2.5e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=1.13e-9 M=0.57 TT=1e-15 XTI=1.2)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.13e-9 IS=1e-30 N=10 M=0.4)
.MODEL MmedMOD NMOS (VTO=1.8 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MstroMOD NMOS (VTO=2.2 KP=380 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.49 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=5e-3 TC2=1e-5)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.1e-3 TC2=-8e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2.0)
.ENDS
Note: For further discussion of the PSPICE model, consult
A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options
; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
8
SABER Electrical Model
REV May 2004
template FDS8874 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod =
(isl=7e-12,ikf=10,nl=1.01,rs=2.5e-3,trs1=8e-4,trs2=2e-7,cjo=1.13e-9,m=0.57,tt=1e-15,xti=1.2)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod =
(cjo=1.13e-9,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.8,kp=9,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.2,kp=380,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.49,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod =
(ron=1e-5,roff=0.1,von=-4,voff=-3)
LDRAIN
sw_vcsp..model s1bmod =
(ron=1e-5,roff=0.1,von=-3,voff=-4)
sw_vcsp..model s2amod =
(ron=1e-5,roff=0.1,von=-2.0,voff=-0.5)
sw_vcsp..model s2bmod =
(ron=1e-5,roff=0.1,von=-0.5,voff=-2.0)
c.ca n12 n8 = 2.4e-9
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
c.cb n15 n14 = 2.4e-9
RSLC2
c.cin n6 n8 = 2.6e-9
ISCL
dp.dbody n7 n5 = model=dbodymod
DBREAK
11
50
–
dp.dbreak n5 n11 = model=dbreakmod
RDRAIN
6
8
dp.dplcap n10 n5 = model=dplcapmod
ESG
DBODY
EVTHRES
+
16
21
+
spe.ebreak n11 n7 n17 n18 = 33.5
–
19
MWEAK
LGATE
EVTEMP
8
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RGATE
GATE
1
+
6
–
18
EBREAK
+
MMED
22
9
20
MSTRO
8
17
RLGATE
18
LSOURCE
CIN
–
SOURCE
3
7
i.it n8 n17 = 1
RSOURCE
RLSOURCE
S1A
S2A
l.lgate n1 n9 = 4e-9
RBREAK
12
15
13
14
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 1e-10
17
18
8
13
RVTEMP
19
S1B
S2B
13
CB
res.rlgate n1 n9 = 40
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1
CA
IT
14
–
+
+
VBAT
6
8
5
8
EGS
EDS
+
–
–
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
22
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RVTHRES
res.rbreak n17 n18
= 1, tc1=8.3e-4,tc2=-8e-7
res.rdrain n50 n16
= 2.35e-3, tc1=5e-3,tc2=1e-5
res.rgate n9 n20 = 1.9
res.rslc1 n5 n51
= 1e-6, tc1=1e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7
= 2e-3, tc1=1e-4,tc2=1e-6
res.rvthres n22 n8
= 1, tc1=-2.1e-3,tc2=-8e-6
res.rvtemp n18 n19
= 1, tc1=-1.8e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
9
SPICE Thermal Model
JUNCTION
th
REV May 2004
FDS8874T
Copper Area =1.0 in
2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
8
7
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
6
5
SABER Thermal Model
Copper Area = 1.0 in
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
4
3
2
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl
=25
}
tl
CASE
TABLE 1. THERMAL MODELS
COMPONANT
CTHERM6
CTHERM7
CTHERM8
RTHERM6
RTHERM7
RTHERM8
0.04 in
2
1.2e-1
0.5
0.28 in
2
1.5e-1
1.0
0.52 in
2
2.0e-1
1.0
0.76 in
2
2.0e-1
1.0
1.0 in
2
2.0e-1
1.0
3.0
12
1.3
2.8
3.0
3.0
26
20
15
13
39
24
21
19
18
55
38.7
31.3
29.7
25
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
10
tm
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Rev. I26
©2007 Fairchild Semiconductor Corporation
FDS8874 Rev. B
11
