onsemi-FDU5N50NZTU

Part #onsemi-FDU5N50NZTU
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onsemi-FDU5N50NZTU
FDU5N50NZTU  
Power MOSFE
T
,
N
-Channel,  
UniFET
t
II  
500
V
, 4
A
, 1.5
W
 
UniFET II MOSFET is ON Semiconductor’s high voltage MOSFET  
family based on advanced planar stripe and DMOS technology. This  
advanced MOSFET family has the smallest on
−
state resistance among  
the planar MOSFET, and also provides superior switching performance  
and higher avalanche energy strength. In addition, internal  
gate
−
source ESD diode allows UniFET II MOSFET to withstand over  
2 kV HBM surge stress. This device family is suitable for switching  
power converter applications such as power factor correction (PFC),  
flat panel display (FPD) TV power,
A
T
X and electronic lamp ballasts.  
D
G
Features  
S
•
R  
= 1.38
ꢀ
(Typ.) @ V
 
= 10
V
, I
 
= 2 A  
GS D  
DS(on)  
•
Low Gate Charge (Typ. 9 nC)  
•
Low C
 
(Typ. 4 pF)  
rss  
•
100% Avalanche Tested  
•
Improved dv/dt Capability  
•
ESD Improved Capability  
•
These Devices are Pb
−
Free and are RoHS Compliant  
Applications  
IPAK3  
CASE 369AR  
•
LCD / LED TV  
•
Lighting  
•
Charger / Adapter  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information on  
©
Semiconductor Components Industries, LLC, 2018  
1
Publication Order Number:  
May, 2019
−
Rev. 1  
FDU5N50NZTU/D  

FDU5N50NZTU  
MAXIMUM RATINGS
(T =
 
25
°
C unless otherwise noted)  
C
Symbol  
Parameter  
Value  
Unit  
V
V
DSS  
V
GSS  
Drain
−
to
−
Source Voltage  
Gate
−
to
−
Source Voltage  
Drain Current  
500  
25  
V
I
D
Continuous (T
 
= 25
°
C)  
4
A
C
Continuous (T
 
= 100
°
C)  
2.4  
C
I
I
Drain Current  
16  
A
mJ  
A
DM  
E
AS  
304  
4
AR  
E
Power Dissipation  
6.2  
mJ  
V/ns  
W
AR  
dv/dt  
10  
62  
P
T =
 
25
°
C  
C
D
Derate Above 25
°
C  
0.5  
W/
°
C  
°
C  
T , T  
Operating and Storage
T
e
mperature Range  
−
55 to +150  
300  
J
STG  
T
L
Maximum Lead
T
e
mperature for Soldering Purposes (1/8
″
from case for 5 seconds)  
°
C  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Repetitive
 
Rating: Pulse width limited by maximum junction temperature.  
2. I
 
= 4 A, V
 
= 50
V
, L =
3
8 mH, R
 
= 25
ꢀ
, starting T
 
= 25
°
C.  
AS  
DD  
G
DSS  
J
3. I
 
≤
4 A, di/dt
≤
200 A/
ꢁ
s, V
 
≤
BV  
, Starting T
 
= 25
°
C.  
SD  
DD  
J
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Value  
2.0  
Unit  
Thermal Resistance, Junction
−
to
−
Case  
Thermal Resistance, Junction
−
to
−
Ambient  
°
C/W  
R
ꢂ
JC  
JA  
R
90  
ꢂ
PACKAGE MARKING AND ORDERING INFORMATION  
Part Number  
Top Mark  
Package  
Packing Method  
Reel Size  
Tape Width  
Quantity  
FDU5N50NZTU  
FDU5N50NZ  
IPAK  
Tube  
N/A  
N/A  
75 units  
2
 

FDU5N50NZTU  
ELECTRICAL CHARACTERISTICS
(T =
 
25
°
C unless otherwise specified)  
C
Symbol  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
OFF CHARACTERISTICS  
BV  
Drain
−
to
−
Source Breakdown Voltage  
I
D
= 250
ꢁ
A, V
 
= 0
V
, T
 
=
2
5
°
C  
500  
V
DSS  
GS  
J
ꢃ
B
V
/
ꢃ
T
Breakdown Voltage
T
e
mperature  
Coefficient  
I
D
= 250
ꢁ
A, Referenced to 25
°
C  
0.5  
V/
°
C  
DSS  
J
I
Zero Gate Voltage Drain Current  
V
= 500
V
, V
 
= 0 V  
1
ꢁ
A  
ꢁ
A  
DSS  
DS  
GS  
V
DS  
= 400
V
, T
 
=
1
25
°
C  
10  
10  
C
I
Gate
−
to
−
Body Leakage Current  
V
GS  
= 25
 
V
, V
 
= 0 V  
DS  
GSS  
ON CHARACTERISTICS  
V
Gate Threshold Voltage  
V
= V
 
, I
 
= 250
ꢁ
A  
3.0  
5.0  
1.5  
V
ꢀ
S
GS(th)  
DS(on)  
GS  
DS  
D
R
Static Drain
−
to
−
Source On Resistance  
Forward Transconductance  
V
V
= 10
V
, I
 
= 2 A  
1.38  
3.54  
GS  
DS  
D
g
FS  
= 20
V
, I
 
= 2 A  
D
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
DS  
= 25
V
, V
 
= 0 V, f = 1
M
Hz  
330  
50  
4
440  
70  
6
pF  
nC  
iss  
GS  
C
Output Capacitance  
oss  
C
Reverse Transfer Capacitance  
T
o
tal Gate Charge at 10 V  
Gate
−
to
−
Source Gate Charge  
Gate
−
to
−
Drain “Miller” Charge  
rss  
Q
V
DS  
= 400
V
, I
 
= 4
A
,  
9
12  
g(tot)  
D
V
GS  
= 10 V (Note

Q
2
gs  
Q
4
gd  
SWITCHING CHARACTERISTICS  
t
Turn
−
On Delay Time  
Turn
−
On Rise Time  
Turn
−
Off Delay Time  
Turn
−
Off Fall Time  
V
= 250
V
, I
 
= 4
A
,  
12  
22  
28  
21  
35  
55  
65  
50  
ns  
d(on)  
DD  
D
V
GS  
= 10
V
, R
 
=
2
5
ꢀ

G
t
r
t
d(off)  
t
f
DRAIN
−
SOURCE DIODE CHARACTERISTICS  
I
Maximum Continuous Drain to Source Diode Forward Current  
Maximum Pulsed Drain to Source Diode Forward Current  
4
A
S
I
16  
1.4  
SM  
V
SD  
Drain to Source Diode Forward Voltage  
Reverse Recovery Time  
V
= 0
V
, I
 
= 4 A  
V
GS  
SD  
t
rr  
V
GS  
= 0
V
, I
 
= 4
A
,  
dI /dt
 
= 100 A/
ꢁ
s  
210  
1.1  
ns  
ꢁ
C  
SD  
F
Q
Reverse Recovery Charge  
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
4. Essentially
 
independent of Operating
T
e
mperature Typical Characteristics.  
3
 

FDU5N50NZTU  
TYPICAL CHARACTERISTICS  
Figure 1. On
−
Region Characteristics  
Figure 2. Transfer Characteristics  
Figure 3. On
−
Resistance Variation vs. Drain  
Figure 4. Body Diode Forward Voltage  
Current and Gate Voltage  
Variation vs. Source Current and Temperature  
Figure 5. Capacitance Characteristics  
Figure 6. Gate Charge Characteristics  
4

FDU5N50NZTU  
TYPICAL CHARACTERISTICS  
Figure 7. Breakdown Voltage Variation vs.  
Figure 8. On
−
Resistance Variation vs.  
Temperature  
Temperature  
Figure 9. Maximum Safe Operating Area vs.  
Case Temperature  
Figure 10. Maximum Drain Current  
P

DM  

t

1  

t

2  

Figure 11. Transient Thermal Response Curve  
5

FDU5N50NZTU  
Figure 12. Gate Charge Test Circuit & Waveform  
Figure 13. Resistive Switching Test Circuit & Waveforms  
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms  
6

FDU5N50NZTU  
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms  
UniFET is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.  
7

MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
DPAK3 (IPAK)  
CASE 369AR  
ISSUE O  
DATE 30 SEP 2016  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions
 
are uncontrolled
 
except when stamped
 
“CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13815G  
DPAK3 (IPAK)  
PAGE 1 OF 1  
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding  
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the  
rights of others.  
©
Semiconductor Components Industries, LLC, 2019  

ON Semiconductor and  
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.  
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coverage may be accessed at

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
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PUBLICATION ORDERING INFORMATION  
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T
:  
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−
282
−
9855
T
o
ll Free USA/Canada  
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