onsemi-FDY2001PZ

Part #onsemi-FDY2001PZ
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onsemi-FDY2001PZ
January 2006  
FDY2001PZ  
Dual P-Channel (– 2.5V) Specified PowerTrench

MOSFET  
General Description  
Features  
This Dual P-Channel MOSFET has been designed  
using Fairchild Semiconductor’s advanced Power  
Trench process to optimize the R

DS(ON)

@ V

GS

= – 2.5v.  
•
– 150 mA, – 20 V
 
R

DS(ON)

= 8
 
Ω
@ V

GS

= – 4.5 V  
R

DS(ON)

= 12
Ω
@ V

GS

= –
 
2.5 V  
Applications  
•
ESD protection diode (note 3)  
•
RoHS Compliant  
•
Li-Ion Battery Pack  
6
5
4
D

1  

6
S

1  

G

1  

D

2  

1
5
4
G

2  

S

2  

2
3
1
2
3
Absolute Maximum Ratings
 
T

A

=25

o

C unless otherwise noted  
Symbol  
V

DSS  

Parameter  
Drain-Source Voltage  
Ratings  
Units  
V
– 20  
V

GSS  

Gate-Source Voltage  
Drain Current
 
– Continuous  
– Pulsed  
V
±
8  
– 150  
I

D  

(Note 1a) 1  
mA  
– 1000  
625  
P

D  

Power Dissipation (Steady State)  
(Note 1a) 1  
(Note 1b) 1  
mW  
446  
T

J

, T

STG  

Operating and Storage Junction Temperature  
Range  
–55 to +150  
°
C  
Thermal Characteristics  
Thermal Resistance, Junction-to-Ambient
 
(Note 1a) 1  
200  
280  
R

θ
JA  

°
C/W  
Thermal Resistance, Junction-to-Ambient
 
(Note 1b) 1  
R

θ
JA  

Package Marking and Ordering Information  
Device Marking  
Device  
Reel Size  
Tape width  
Quantity  
B
FDY2001PZ  
7 ’’  
8 mm  
3000units  
2006 Fairchild Semiconductor Corporation  
FDY2001PZ Rev A  

Electrical Characteristics  
T

A

= 25°C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min Typ
 
Max Units  
Off Characteristics  
BV

DSS  

Drain–Source Breakdown  
– 20  
V
V

GS

= 0 V,  
I

D

= – 250
µ
A  
Voltage  
Breakdown Voltage Temperature  
Coefficient  
16  
∆
BV
DSS  
∆
T

J  

I

D

= – 250
µ
A, Referenced to 25
°
C  
mV/
°
C  
I

DSS  

Zero Gate Voltage Drain Current
 
V

DS

= – 16 V,
 
V

GS

= 0 V  
Gate–Body Leakage,  
– 3  
µ
A  
µ
A  
I

GSS  

V

GS

=
±
8 V,  
V

DS

= 0 V  
±
10  
On Characteristics  
(Note 2)  
V

GS(th)  

Gate Threshold Voltage  
– 0.65
 
– 1.0
 
– 1.5  
– 3  
V
V

DS

= V

GS  

I

D

= 250
µ
A, Referenced to 25
°
C  
,
I

D

= – 250
µ
A  
Gate Threshold Voltage  
Temperature Coefficient  
∆
V

GS(th)  

∆
T

J  

R

DS(on)  

mV/
°
C  
Static Drain–Source  
On–Resistance  
V

GS

= – 4.5 V,
 
I

D

= –150 mA  
V

GS

= – 2.5 V,
 
I

D

= –125 mA  
V

GS

= – 1.8 V,
 
I

D

= –100 mA  
V

GS

= – 1.5 V
 
I

D

= –
 
30 mA  
8
Ω
12  
15  
20  
12  
V

GS

= – 4.5 V,
 
I

D

= – 150 mA,  
T

J

= 125
°
C  
V

DS

= – 5 V,  
g

FS  

Forward Transconductance  
I

D

= – 150 mA  
0.7  
S
Dynamic Characteristics  
C

iss  

C

oss  

C

rss  

Input Capacitance  
100  
30  
pF  
pF  
pF  
V

DS

= – 10 V,
 
V

GS

= 0 V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
15  
Switching Characteristics
 
(Note 2)  
t

d(on)  

t

r  

t

d(off)  

t

f  

Turn–On Delay Time  
Turn–On Rise Time  
Turn–Off Delay Time  
Turn–Off Fall Time  
Total Gate Charge  
Gate–Source Charge  
Gate–Drain Charge  
6
13  
8
12  
23  
16  
2
ns  
ns  
V

DD

= – 10 V,
 
I

D

= – 150 mA,  
V

GS

= – 4.5 V,
 
R

GEN

= 6
Ω  
ns  
1
ns  
Q

g  

Q

gs  

Q

gd  

1.0  
0.2  
0.3  
1.4  
nC  
nC  
nC  
V

DS

= – 10 V,
 
I

D

= – 150 mA,  
V

GS

= – 4.5 V  
Drain–Source Diode Characteristics and Maximum Ratings  
V

SD  

Drain–Source Diode Forward  
Voltage  
V

GS

= 0 V,
 
I

S

= – 150 mA
(Note 2)  
– 0.9
 
– 1.2  
V
t

rr  

Diode Reverse Recovery Time  
I

F

= – 150 mA,  
dI

F

/dt = 100 A/µs  
11  
2
ns  
Q

rr  

Diode Reverse Recovery Charge  
nC  
Notes:  
1
. R

θ
JA

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of  
the drain pins. R

θ
JC

is guaranteed by design while R

θ
CA

is determined by the user’s board design  
a)  
200°C/W when  
b) 280°C/W when mounted on a  
minimum pad of 2 oz copper  
Scale 1 : 1 on letter size paper  
mounted on a 1in

2

pad  
of 2 oz copper  
2
.
Pulse Test: Pulse Width < 300
µ
s,  
Duty Cycle
 
< 2.0%  
3. The diode connected between the gate  
and source serves only as protection  
againts ESD.
 
No gate overvoltage  
rating is implied.  
FDY2001PZ Rev A  

Typical Characteristics  
5
4.2  
3.4  
2.6  
1.8  
1
1
V

GS

=-1.5V  
V

GS

= -4.5V  
-3.5V  
-2.5V  
0.8  
0.6  
0.4  
0.2  
0
-3.0V  
-2.0V  
-1.8V  
-2.0V  
-1.8V  
-2.5V  
0.4  
-3.0V  
0.6  
-3.5V  
-4.5V  
-1.5V  
0.2  
0
0.2  
0.8  
1
0
0.5  
1
1.5  
2
-V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
-I

D

, DRAIN CURRENT (A)  
Figure 1. On-Region Characteristics.  
Figure 2. On-Resistance Variation with  
Drain Current and Gate Voltage.  
1.6  
1.4  
1.2  
1
2.25  
I

D

= -0.15A  
V

GS

= -4.5V  
I

D

= -0.075A  
1.75  
1.25  
0.75  
0.25  
T

A

= 125

o

C  
0.8  
0.6  
T

A

= 25

o

C  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
0
2
4
6
8
10  
T

J

, JUNCTION TEMPERATURE (

o

C)  
-V

GS

, GATE TO SOURCE VOLTAGE (V)  
Figure 3. On-Resistance Variation with  
Temperature.  
Figure 4. On-Resistance Variation with  
Gate-to-Source Voltage.  
1
1
0.8  
0.6  
0.4  
0.2  
0
V

GS

= 0V  
V

DS

= -5V  
0.1  
0.01  
0.001  
T

A

= 125

o

C  
T

A

= 125

o

C  
-55

o

C  
25

o

C  
-55

o

C  
0.8  
25

o

C  
0.0001  
0.5  
1
1.5  
2
2.5  
0
0.2  
0.4  
0.6  
1
1.2  
1.4  
-V

GS

, GATE TO SOURCE VOLTAGE (V)  
-V

SD

, BODY
 
DIODE FORWARD VOLTAGE (V)  
Figure 5. Transfer Characteristics.  
Figure 6. Body Diode Forward Voltage Variation  
with Source Current and Temperature.  
FDY2001PZ Rev A  

Typical Characteristics  
10  
150  
125  
100  
75  
f = 1 MHz  

GS

= 0 V  
I

D

= –  
V
8
V

DS

= -5V  
-15V  
C

iss  

6
-10V  
4
2
0
50  
C

oss  

25  
C

rss  

0
0
0.5  
1
1.5  
2
2.5  
0
4
8
12  
16  
20  
Q

g

, GATE CHARGE (nC)  
-V

DS

, DRAIN TO SOURCE VOLTAGE (V)  
Figure 7. Gate Charge Characteristics.  
Figure 8. Capacitance Characteristics.  
10  
10  
8
SINGLE PULSE  
R

θ
JA

= 280°C/W  
T

A

= 25°C  
1ms  
10ms  
1
R

DS(ON)

LIMIT  
6
100ms  
1s  
10s  
DC  
4
0.1  
V

GS

= -4.5V  
SINGLE PULSE  
R

θ
JA

= 280

o

C/W  
2
T

A

= 25

o

C  
0.01  
0
0.01  
0.1  
1
10  
100  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
-V

DS

, DRAIN-SOURCE VOLTAGE (V)  
t

1

, TIME (sec)  
Figure 9. Maximum Safe Operating Area.  
Figure 10. Single Pulse Maximum  
Power Dissipation.  
1
D = 0.5  
R

θ
JA

(t) = r(t) * R

θ
JA  

R

θ
JA

=280 °C/W  
0.2  
P(pk)  
0.1  
0.1  
0.05  
t

1  

t

2  

0.02  
0.01  
T

J

– T

A

= P * R

θ
JA

(t)  
Duty Cycle, D = t

1

/ t

2  

SINGLE PULSE  
0.01  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
t

1

, TIME (sec)  
Figure 11. Transient Thermal Response Curve.  
Thermal characterization performed using the conditions described in Note 1b.  
Transient thermal response will change depending on the circuit board design.  
FDY2001PZ Rev A  

Dimensional Outline and Pad Layout  
1.70  
1.50  
0.50  
0.30  
0.15  
0.50  
6
1
4
3
1.70  
1.55  
1.20 BSC  
(0.20)  
1.25  
1.80  
0.30  
0.55  
0.50  
1.00  
LAND PATTERN RECOMMENDATION  
0.60  
0.56  
0.18  
0.10  
SEE DETAIL A  
0.35 BSC  
0.20 BSC  
DETAIL A  
0.10  
0.00  
SCALE 2 : 1  
NOTES: UNLESS OTHERWISE SPECIFIED  
A) THIS PACKAGE CONFORMS TO EIAJ  
SC89 PACKAGING STANDARD.  
B) ALL DIMENSIONS ARE IN MILLIMETERS.  
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,  
MOLD FLASH, AND TIE BAR EXTRUSIONS.  
FDY2001PZ Rev A  

TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
®
ACEx™  
PowerSaver™  
SuperSOT™-6  
SuperSOT™-8  
SyncFET™  
TCM™  
ISOPLANAR™  
LittleFET™  
MICROCOUPLER™  
MicroFET™  
MicroPak™  
MICROWIRE™  
MSX™  
FAST  
®
PowerTrench  
ActiveArray™  
Bottomless™  
Build it Now™  
CoolFET™  
CROSSVOLT
™  
DOME™  
EcoSPARK™  
E

2

CMOS™  
EnSigna™  
FACT™  
FASTr™  
FPS™  
FRFET™  
GlobalOptoisolator™  
GTO™  
®
QFET  
QS™  
®
QT Optoelectronics™  
Quiet Series™  
RapidConfigure™  
RapidConnect™  
μ
SerDes™  
ScalarPump™  
SILENT SWITCHER  
SMART START™  
SPM™  
Stealth™  
TinyLogic  
TINYOPTO™  
TruTranslation™  
UHC™  
HiSeC™  
I

2

C™  
MSXPro™  
OCX™  
®
UltraFET  
i-Lo
™  
ImpliedDisconnect™  
IntelliMAX™  
UniFET™  
VCX™  
Wire™  
OCXPro™  
OPTOLOGIC  
®
®
OPTOPLANAR™  
PACMAN™  
POP™  
Power247™  
PowerEdge™  
FACT Quiet Series™  
Across the board. Around the world.™  
®
The Power Franchise  
SuperFET™  
SuperSOT™-3  
Programmable Active Droop™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVE
S
T
HE RIGH
T
T
O MAKE CHANGES WITHOU
T
F
URTHER NOTIC
E
T
O
A
NY  
PRODUCTS HEREI
N
T
O IMPROVE RELIABILIT
Y
,
F
UNCTION OR DESIGN. FAIRCHILD DOES NO
T
A
SSUM
E
A
N
Y
L
IABILITY  
ARISING OU
T
O
F
T
H
E
A
PPLICATION OR USE O
F
A
N
Y
P
RODUC
T
O
R CIRCUI
T
D
ESCRIBED HEREIN; NEITHER DOES IT  
CONVE
Y
A
N
Y
L
ICENSE UNDER ITS PATEN
T
R
IGHTS, NO
R
T
HE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOU
T
T
HE EXPRESS WRITTE
N
A
PPROVA
L
O
F FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
Rev. I18