onsemi-FNB81560T3
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FNB81560T3
Motion SPM
)
8 Series
FNB81560T3 is a Motion SPM 8 module providing a
fully−featured, high−performance inverter output stage for AC
Induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features
including under−voltage lockouts, inter−lock function, over−current
shutdown, thermal monitoring of drive IC, and fault reporting. The
built−in, high−speed HVIC requires only a single supply voltage and
translates the incoming logic−level gate inputs to the high−voltage,
high−current drive signals required to properly drive the module’s
robust shortcircuit−rated IGBTs. Separate negative IGBT terminals
are available for each phase to support the widest variety of control
algorithms.
Features
•
UL Certified No. E209204 (UL1557)
•
600 V − 15 A 3−Phase IGBT Inverter Including Control IC for Gate
Drive and Protections
•
Low−Loss, Short−Circuit Rated IGBTs
•
Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
•
Active−high Interface, works with 3.3 / 5 V Logic, Schmitt−trigger
3D Package Drawing
(Click to Activate 3D Content)
Input
•
HVIC for Gate Driving, Under−
V
o
ltage and Short−Circuit Current
Protection
SPMFA−A25
CASE MODEZ
•
Fault Output for Under−
V
o
ltage and Short−Circuit Current Protection
•
Inter−Lock Function to Prevent Short−Circuit
•
Shut−Down Input
MARKING DIAGRAM
•
HVIC Temperature−Sensing Built−In for Temperature Monitoring
•
Isolation Rating: 1500 V
/ min.
rms
Applications
•
Motion Control − Home Appliance / Industrial Motor
Related Resources
ON
NB81560T3
XXX
Y
= ON Semiconductor Logo
Guide
= Specific Device Code
= Lot Number
=
Y
e
ar
•
AN−9584
*
SPM 8 Package Assembly Guidance for 25L double
DIP
WW
= Work Week
Integrated Power Functions
•
600 V − 15 A IGBT Inverter for Three Phase DC / AC Power
ORDERING INFORMATION
this data sheet.
Integrated Drive, Protection and System Control Functions
•
For Inverter High−side IGBTs: gate drive circuit, high−voltage
isolated high−speed level shifting control circuit Under−
V
o
ltage
Lock−Out (UVLO) protection (Note: Available bootstrap circuit
©
Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
August, 2019 − Rev. 3
FNB81560T3/D
FNB81560T3
•
Control Circuit Under−
V
o
ltage Lock−Out (UVLO) protection
•
For Inverter Low−side IGBTs: gate drive circuit, Over Current
Protection (OCP), Short−Circuit Protection (SCP) control supply
circuit Under−
V
o
ltage Lock−Out (UVLO) protection
•
Fault Signaling: corresponding to UVLO (low−side supply) and SC
faults
•
Input Interface: High−active interface, works with 3.3 / 5 V logic,
Schmitt trigger input
PIN CONFIGURATION
(25) VB
U
(1) P
(24) COM
(23) IN
UH
(22) IN
UL
(21) V
DD
(20) /SD
U
(2) U, VS
U
Case temperature (Tc)
Detecting point
(3) N
U
(19) VB
V
(4) V, V
S
V
(5) N
V
(18) IN
VH
(17) IN
VL
(16) V
DD
(15) /SD
V
(14) VB
W
(13) IN
WH
(12) IN
WL
(6) W, VS
W
(7) N
W
(11) V
DD
(10) Csc
(9) /FO,/S
D
W
,V
TS
(8) COM
Figure 1. Pin Configuration − Top View
Table 1. PIN DESCRIPTIONS
Pin Number
Pin Name
P
Pin Description
1
2
3
4
5
6
7
8
9
Positive DC−Link Input
U, VS
U
N
U
Output for U Phase
Negative DC−Link Input for U Phase
Output for V Phase
V,
V
S
V
N
V
Negative DC−Link Input for V Phase
Output for W Phase
W, VS
W
N
W
Negative DC−Link Input for W Phase
Common Supply Ground
COM
/FO, /SD
W
, V
TS
Fault Output, Shut−Down Input for W Phase,
T
e
mperature Output of Drive IC
10
11
12
13
C
SC
V
DD
IN
WL
IN
WH
Shut Down Input for Over Current and Short Circuit Protection
Common Bias Voltage for IC and IGB
T
s
D
riving
Signal Input for Low−Side W Phase
Signal Input for High−Side W Phase
2
FNB81560T3
Pin Number
Pin Name
VB
W
Pin Description
14
15
High−Side Bias Voltage for W−Phase IGBT Driving
Shut−Down Input for V Phase
/SD
V
16
17
18
19
20
V
DD
IN
VL
IN
VH
VB
V
/SD
U
Common Bias Voltage for IC and IGB
T
s
D
riving
Signal Input for Low−Side V Phase
Signal Input for High−Side V Phase
High−Side Bias Voltage for V−Phase IGBT Driving
Shut−Down Input for U Phase
21
22
23
24
25
V
DD
IN
UL
IN
UH
COM
VB
U
Common Bias Voltage for IC and IGB
T
s
D
riving
Signal Input for Low−Side U Phase
Signal Input for High−Side U Phase
Common Supply Ground
High−Side Bias Voltage for U−Phase IGBT Driving
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
P
VB
U
VB
HIN
LIN
HO
VS
LO
IN
UH
IN
UL
V
DD
U,VS
U
V
DD
/SD
U
/SD
U
COM
COM
N
U
VB
V
IN
VH
IN
VL
VB
HIN
LIN
HO
VS
LO
V,VS
V
V
DD
V
DD
/SD
V
COM
/SD
V
Nv
VB
W
IN
WH
IN
WL
VB
HIN
LIN
HO
VS
LO
V
DD
W,VS
W
V
DD
Csc
Csc
/FO, /SD
W
, V
TS
COM
/FO, /SD
W
, V
TS
COM
Nw
Notes:
1. Inverter high−side is composed of three IGB
T
s
, freewheeling diodes.
2. Inverter low−side is composed of three IGB
T
s
, freewheeling diodes.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
Figure 2. Internal Block Diagram
3
FNB81560T3
Table 2. ABSOLUTE MAXIMUM RATINGS
(T =
25
°
C unless otherwise specified)
J
Symbol
Parameter
Conditions
Rating
Unit
INVERTER PART
V
Supply Voltage
Applied between P − N
, N
, N
450
500
600
15
V
V
V
A
A
PN
PN(Surge)
U
V
W
V
Supply Voltage (Surge)
Applied between P − N
, N
, N
U V
W
V
CES
Collector − Emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
I
C
T
T
C
J
I
= 25
°
C, T
≤
150
°
C, Under 1 ms Pulse Width
30
CP
C
J
T
Operating Junction
T
e
mperature
−40 ~ 150
_
C
J
CONTROL PART
V
Control Supply Voltage
Applied between V
− COM
20
20
V
V
DD
DD
V
High−Side Control Bias Voltage
Applied between VB
− VS
, VB
− VS
, VB
−
BS
U
U
V
V
W
VS
W
V
IN
Input Signal Voltage
Applied between IN
, IN
, IN
, IN
, IN
IN −
COM
WL
,
−0.3 ~ V
+ 0.3
V
UH
VH
WH
UL
VL
DD
V
Function Supply Voltage
Fault Current
Applied between /FO, /SD
, V
− COM
−0.3 ~ V
+ 0.3
V
mA
V
FS
W
TS
DD
I
Sink Current at /FO, /SD
, V
pin
2
FO
W
TS
V
SC
Current Sensing Input Voltage
Applied between C
− COM
−0.3 ~ V
+ 0.3
SC
DD
TOTAL SYSTEM
V
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
V
= V
= 13.5 ~ 16.5
V
, T
=
1
50
°
C, Non−
400
V
PN(PROT)
DD
BS
J
Repetitive, < 2
m
s
T
Storage
T
e
mperature
−40 ~ 125
1600
_
C
Vrms
STG
V
Isolation Voltage
Connect Pins to Heat Sink Plate
AC 60 Hz, Sinusoidal, AC 1 Minute, Connection
Pins to Heat Sink Plate
ISO
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. These
values had been made an acquisition by the calculation considered to design factor
.
Table 3. THERMAL RESISTANCE
Symbol
Parameter
Conditions
Inverter IGBT part, (Per Module)
Inverter FWDi part, (Per Module)
Min
−
Typ
−
Max
3.40
3.86
Unit
_
C/W
_
C/W
R
th(j−c)Q
Junction−to−Case Thermal
R
−
−
th(j−c)F
C
4
FNB81560T3
Table 4. ELECTRICAL CHARACTERISTICS
(T =
25
°
C unless otherwise specified.)
J
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INVERTER PART
V
CE(SAT)
T
J
= 25
°
C
T
J
= 150
°
C
T
J
= 25
°
C
T
J
= 150
°
C
−
−
−
−
1.60
1.80
2.00
1.90
2.10
−
V
V
V
V
V
DD
= V
BS
= 15 V, V
IN
= 5
V
,
I
C
= 12 A
Collector − Emitter Saturation
Voltage
V
F
FWDi Forward Voltage
2.50
−
V
IN
= 0
V
,
I
F
= 12 A
HS
t
ON
Switching Times
0.25
0.75
1.25
m
s
V
PN
= 400
V
,
V
DD
= V
BS
= 15 V, I
C
= 15 A, T
J
= 25
°
C
V
t
C(ON)
t
OFF
−
−
−
0.20
0.55
0.10
0.50
1.05
0.40
m
s
m
s
m
s
t
C(OFF)
t
rr
−
0.25
−
0.10
0.75
0.20
−
m
s
m
s
m
s
LS
t
ON
1.25
0.50
V
PN
= 400
V
,
V
DD
= V
BS
= 15 V, I
C
= 15 A, T
J
= 25
°
C
t
C(ON)
t
OFF
−
−
−
0.55
0.10
0.10
1.05
0.40
−
m
s
m
s
m
s
t
C(OFF)
t
rr
I
CES
V
CE
= V
CES
−
−
1.00
mA
Collector − Emitter Leakage
Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. t
and t
include the propagation delay of the internal drive IC. t
and t
are the switching times of IGBT under the given
ON
OFF
C(ON)
C(OFF)
HINx
LINx
t
rr
t
off
t
on
100% I
Cx
I
Cx
90%
I
Cx
10% V
CEx
10% V
CEx
v
CEx
10% I
Cx
10% I
Cx
t
c(on)
t
c(off)
Figure 3. Switching Time
5
FNB81560T3
One−Leg Diagram of SPM 8
I
C
V
BS
P
V
C
BS
+15V
VB
LS Switching
HO
HIN
V
PN
HS Switching
U,V,W
VS
V
Inductor
400V
LIN
V
DD
LS Switching
/Fo, /SDw,
V
TS
LO
V
IN
HS Switching
5V
0V
V
DD
V
10k
W
Csc
COM
N
U,V,W
+15V
V
+5V
Figure 4. Example Circuit for Switching Test
Inductive Load,
V
P
N
= 300V, V
=15V,
T
=
25
Inductive Load,
V
P
N
= 300V, V
=15V,
T
=
150
°
C
DD J
°
C
DD
J
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
IGBT Turn−on, Eon
IGBT Turn−off, Eoff
FRD Turn−off, Erec
0.0 1.5 3.0 4.5 6.0 7.5 9.0
10.5 12.0 13.5 15.0 16.5
COLLECTOR CURRENT, I
C
[AMPERES]
0.0 1.5 3.0 4.5 6.0 7.5 9.0
10.5 12.0 13.5 15.0 16.5
COLLECTOR CURRENT, I
C
[AMPERES]
Figure 5. Switching Loss Characteristics
4.8
4.3
3.8
3.3
2.8
2.3
1.8
1.3
3.3V pull−up with 4.7kohm
5V pull−up with 10kohm
0
25
50
75
T
HVIC
[ C]
100
125
150
O
Figure 6. V−T Curve of Temperature Output of IC
6
FNB81560T3
Table 5. ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CONTROL PART
I
QDD
V
DD
− COM
V
DD
− COM
−
−
−
−
−
−
−
−
1.7
2.2
mA
mA
m
A
IN
Quiescent V
DD
Supply
Current
V
DD
= 15 V,
(UH,VH,WH,UL,VL,WL)
= 0 V
I
PDD
I
QBS
I
PBS
V
DD
= 15 V, f
PWM
= 20 kHz, duty = 50%,
applied to one PWM signal input
Operating V
DD
Supply
Current
V
BS
= 15
V
,
I
N
(UH, VH, WH)
= 0 V
V
B(U)
− V
S(U)
, V
B(V)
−
V
S(V)
, V
B(W)
− V
S(W)
100
700
Quiescent V
BS
Supply
Current
V
DD
= V
BS
= 15 V, f
PWM
= 20 kHz,
duty = 50%, applied to one PWM signal
input for high − side
V
B(U)
− V
S(U)
, V
B(V)
−
V
S(V)
, V
B(W)
− V
S(W)
m
A
Operating V
BS
Supply
Current
V
FOH
Fault Output Voltage
3.81
−
−
V
V
SC
= 0
V
,
V
F
Circuit: 10 k
W
to 5 V Pull−up
V
SC
= 1
V
,
V
F
Circuit: 10 k
W
to 5 V Pull−up
V
FOL
−
−
0.5
V
V
V
V
SC(ref)
Short−Circuit Trip Level
V
DD
= 15 V (Note 4)
0.46
10.0
0.49
11.5
0.52
13.0
UV
DDD
Detection level
Supply Circuit Under−
Voltage Protection
UV
DDR
UV
BSD
Reset level
10.5
9.5
12.0
11.0
11.5
13.5
12.5
13.0
V
V
V
Detection level
Reset level
UV
BSR
I
FO_T
10.0
V
DD
= V
BS
= 15 V, T
HVIC
= 25
°
C
V
DD
= V
BS
= 15 V, T
HVIC
= 75
°
C
−
−
−
82.5
207.5
4.18
−
−
−
m
A
m
A
V
HVIC
T
e
mperature
Sensing Current
V
FO_T
V
DD
= V
BS
= 15 V, T
HVIC
= 25
°
C, 10 k
W
to 5 V Pull−up
V
DD
= V
BS
= 15 V, T
HVIC
= 75
°
C, 10 k
W
to 5 V Pull−up
HVIC
T
e
mperature
Sensing Voltage See
Figure 7
−
2.93
−
V
t
FOD
Fault−Out Pulse Width
40
−
−
−
−
−
2.4
−
m
s
V
V
FSDR
V
FSDD
Shut−down Reset level
Applied between /FO − COM
0.8
V
Shut−down Detection
level
V
IN(ON)
ON Threshold Voltage
−
−
−
2.4
−
V
V
Applied between IN
(UH)
, IN
(VH)
, IN
(WH)
, IN
(UL)
, IN
(VL)
, IN
(WL)
− COM
V
IN(OFF)
OFF Threshold Voltage
0.8
BOOTSTRAP DIODE PART
V
DD
= 15 V, T
J
= 25
°
C
R
BS
Bootstrap Diode Resis-
tance
−
280
−
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Short−circuit
current protection function is for all six IGB
T
s
i
f the /FO, /SD
W
, V
TS
pin is connected to /SD
x
pins.
7
FNB81560T3
0.06
0.05
0.04
0.03
0.02
0.01
0.00
T
J
=25
o
C, V
D
D
=15V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
V
F
[V]
Figure 7. Built−In Bootstrap Diode Characteristics
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage
Conditions
Min
Typ
Max
Unit
V
PN
Applied between P − N
U
, N
V
, N
W
−
300
400
V
V
DD
V
BS
Control Supply Voltage
High − Side Bias Voltage
Control Supply Variation
Applied between V
DD
− COM
14.0
13.0
−1
15
15
−
16.5
18.5
1
V
V
Applied between VB
U
− VS
U
, VB
V
−VS
V
, VB
W
− VS
W
V/
m
s
dV
DD
/ dt,
dV
BS
/ dt
t
dead
For each input signal
0.5
−4
−
−
4
m
s
Blanking Time for Preventing
Arm − Short
V
SEN
V
Applied between N
U
, N
V
, N
W
− COM (Including surge
voltage)
Voltage for Current Sensing
Minimun Input Pulse Width
P
WIN(ON)
0.7
0.7
−
−
−
−
m
s
V
DD
= V
BS
= 15
V
,
I
C
≤
30 A,
Wiring Inductance
P
WIN(OFF)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. This
product might not make response if input pulse width is less than the recommended value.
Table 7. MECHANICAL CHARACTERISTICS AND RATINGS
Parameter
Device Flatness
Conditions
Min
−50
0.6
5.9
−
Typ
−
Max
10
0
0.8
7.9
−
Unit
m
m
Mounting
T
o
rque
Mounting Screw: M3
Recommended 0.7 N
•
m
Recommended 7.1 kg
•
cm
0.7
6.9
5.0
N
•
m
kg
•
cm
g
Weight
6. Do
not make over torque when mounting screws. Much mounting torque may cause package cracks, as well as bolts and Al heat−sink
destruction.
7. Avoid
one side tightening stress. Figure 9
shows the recommended torque order for mounting screws. Uneven mounting can cause the DBC
substrate of package to be damaged. The pre−screwing torque is set to 20 ~ 30% of maximum torque rating.
8
FNB81560T3
Figure 8. Flatness Measurement Position
Pre−Screwing: 1
→
2
Final Screwing: 2
→
1
2
1
Figure 9. Mounting Screws Torque Order
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Shipping
FNB81560T3
NB81560T3
SPMFA−A25
15 Units / Rail
9
FNB81560T3
TIME CHARTS OF PROTECTIVE FUNCTION
Input Signal
Protection
Circuit State
RESET
SET
RESET
UV
DDR
a1
a6
UV
DDD
a2
Control
Supply Voltage
a3
a4
a7
Output Current
a5
Fault Output Signal
a1: Control supply voltage rises: after the voltage rises UV
a2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
DDR
a3: Under−voltage detection (UV
).
DDD
a4: IGBT OFF in spite of control input condition.
a5: Fault output operation starts.
a6: Under−voltage reset (UV
).
DDR
a7: Normal operation: IGBT ON and carrying current.
Figure 10. Under−Voltage Protection (Low−Side)
Input Signal
Protection
Circuit State
RESET
SET
RESET
UV
BSR
b5
b1
UV
BSD
b2
Control
Supply Voltage
b3
b4
b6
Output Current
High−level (no fault output)
Fault Output Signal
b1: Control supply voltage rises: after the voltage reaches UV
b2: Normal operation: IGBT ON and carrying current.
, the circuits start to operate when next input is applied.
BSR
b3: Under−voltage detection (UV
).
BSD
b4: IGBT OFF in spite of control input condition, but there is no fault output signal.
b5: Under−voltage reset (UV
).
BSR
b6: Normal operation: IGBT ON and carrying current.
Figure 11. Under−Voltage Protection (High−Side)
10
FNB81560T3
Hin
Lin
Ho
Lo
d3
d4
d5
Hin : High−side Input Signal
Lin : Low−side Input Signal
Ho : High−side IGBT Gate Voltage
Lo : Low−side IGBT Gate Voltage
/Fo : Fault Output
d1
d2
/Fo
d1: High Side First − Input − First − Output Mode
d2: Low Side Noise Mode: No LO
d3: High Side Noise Mode: No HO
d4: Low Side First − Input − First − Output Mode
d5: IN − Phase Mode: No HO
Figure 12. Inter−Lock Function
HIN
LIN
HO
Smart Turn−off
Activated by next input
after fault clear
Soft Off
LO
Over−Current
Detection
CSC
No Output
/FO
HIN : High−side Input Signal
LIN :
Low−side Input Signal
HO :
High−Side Output Signal
LO :
Low−Side Output Signal
C
: Over Current Detection Input
SC
/FO : Fault Out Function
Figure 13. Fault−Out Function by Over Current Protection
11
FNB81560T3
HIN
LIN
HO
Activated by next
input after fault
clear
No Output
Smart
Turn−off
Soft Off
LO
C
SC
External
/S
D
x
shutdown input
HIN : High−side Input Signal
LIN :
Low−side Input Signal
HO :
High−Side Output Signal
LO :
Low−Side Output Signal
C
: Over Current Detection Input
SC
/SD :
Shutdown Input Function
x
Figure 14. Shutdown Input Function by External Command
INPUT/OUTPUT INTERFACE CIRCUIT
5 V Line (MCU or Control power)
R
PF
= 10k
W
SPM
IN
UH
, IN
VH
, IN
WH
IN
UL
, IN
VL
, IN
/FO, /SD
W
, V
WL
TS
MCU
COM
NOTE: RC
coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the
application and the wiring impedance of the application’s printed circuit board. The input signal section of the SPM 8
product integrates 5 k
W
(typ.) pull−down resistor. Therefore, when using an external filtering resistor, please pay
attention to the signal voltage drop at input terminal.
Figure 15. Recommended MCU I/O Interface Circuit
12
FNB81560T3
P
U,VS
U
Nu
15V
VB
U
VB
HO
VS
LO
C
BS
C
BSC
R
S
R
S
IN
UH
IN
UL
HIN
LIN
Gating UH
Gating UL
V
DD
C
PS
C
PS
V
DD
/SD
U
COM
/SD
U
COM
VB
V
HO
VS
LO
VB
M
C
U
C
BS
C
BSC
V,VS
V
R
S
R
S
IN
VH
IN
VL
M
Gating VH
Gating VL
HIN
LIN
C
DCS
V
DC
V
DD
C
PS
C
PS
V
DD
/SD
V
/SD
V
COM
5V
Nv
VB
W
VB
HO
VS
LO
C
BS
C
BSC
R
S
R
S
IN
WH
IN
WL
HIN
LIN
Gating WH
Gating WL
W,VS
W
V
DD
V
DD
Fault
/Fo, /SDw, V
TS
Csc
A
/Fo, /SDw, V
TS
Csc
COM
R
SU
E
COM
Nw
R
F
D
C
PS
C
PS
C
PF
C
SP15
C
SPC15
C
SC
R
SV
R
SW
Power
GND Line
B
C
Control
W−Phase Current
GND Line
Input Signal for
V−Phase Current
U−Phase Current
Short−Circuit Protection
Figure 16. Typical Application Circuit
NOTES:
8.
T
o
a
void malfunction, the wiring of each input should be as short as possible (Less than 2 ~ 3 cm).
9. /FO
is open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor that makes
I
FO
10
.
C
of around seven times larger than bootstrap capacitor C
is recommended.
SP15
BS
11. Input signal is active−HIGH type. There is a 5 k
W
resistor inside the IC to pull down each input signal line to GND. RC coupling circuits are
recommended for the prevention of input signal oscillation. R
C time
constant should be selected in the range 50 ~ 150 ns (Recommended
S
PS
R
= 100
W
, C
= 1 nF).
S
PS
12
.
E
ach wiring pattern inductance of A point should be minimized (Recommend less than 10nH). Use the shunt resistor R
of surface
S(U/V/W)
mounted (SMD) type to reduce wiring inductance.
T
o
p
revent malfunction, wiring of point E should be connected to the terminal of the shunt
resistor R
as close as possible.
S(U/V/W)
13
.
T
o
p
revent errors of the protection function, the wiring of B, C, and D point should be as short as possible.
14
.
I
n the short−circuit current protection circuit, please select the R
C time
constant in the range 1.5 ~ 2
m
s. Do enough evaluation on the
F
SC
real system because short−circuit protection time may vary wiring pattern layout and value of the R
and C
time constant.
F
SC
15
.
T
he connection between control GND line and power GND line which includes the N
, N
, N
must be connected to only one point. Please
U
V
W
do not connect the control GND to the power GND by the broad pattern. Also, the wiring distance between control GND and power GND
should be as short as possible.
16
.
E
ach capacitor should be mounted as close to the pins of the Motion SPM 8 product as possible.
17
.
T
o
p
revent surge destruction, the wiring between the smoothing capacitor and the P and GND pins should be as short as possible. The use
of a high frequency non−inductive capacitor of around 0.1 ~ 0.22
m
F between the P and GND pins is recommended.
18
.
R
elays are used in almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance
between the CPU and the relays.
19
.
T
he zener diode or transient voltage suppressor should be adapted for the protection of ICs from the surge destruction between each pair
of control supply terminals (Recommended zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15
W
).
20
.
P
lease choose the electrolytic capacitor with good temperature characteristic in C
. Also, choose 0.1 ~ 0.2
m
F R−category ceramic
BS
capacitors with good temperature and frequency characteristics in C
21
.
F
or the detailed information, please refer to the application notes.
22
.
/
FO and /SD must be connected as short as possible.
.
BSC
SPM is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
13
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMFA−A25 / 25LD, FULL PACK, DIP TYPE, SPM8 SERIES
CASE MODEZ
ISSUE O
DATE 31 JAN 2017
98AON13572G
ON SEMICONDUCTOR STANDARD
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STATUS:
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accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
DESCRIPTION: SPMFA−A25
/ 25LD, FULL PACK, DIP TYPE, SPM8 SERIES
PAGE 1 O
F
2
DOCUMENT NUMBER:
98AON13572G
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Case Outline Number:
January, 2017 − Rev. O
MODEZ
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