onsemi-FQD17N08LTF
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December 2000
TM
QFET
FQD17N08L / FQU17N08L
80V LOGIC N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
•
•
•
•
•
•
•
12.9A, 80V, R
= 0.1
Ω
@V =
10 V
DS(on) GS
Low gate charge ( typical 8.8 nC)
Low Crss ( typical
29 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
This advanced technology is especially tailored to minimize
on-state
resistance,
provide
superior
switching
performance, and withstand a high energy pulse in the
avalanche and commutation modes. These devices are
well suited for low voltage applications such as automotive,
high efficiency switching for DC/DC converters, and DC
motor control.
Low level gate drive requirements allowing
direct operation from logic drives
D
!
D
“
! ”
“
!
G
“
I-PAK
FQU Series
D-PAK
FQD Series
G
S
G
D
!
S
S
Absolute Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
Parameter
FQD17N08L / FQU17N08L
Units
V
V
I
Drain-Source Voltage
80
12.9
8.2
DSS
– Continuous (T
= 25°C)
Drain Current
A
D
C
– Continuous (T
= 100°C)
A
C
I
(Note 1)
Drain Current
– Pulsed
51.6
±
20
100
A
DM
V
E
I
Gate-Source Voltage
V
GSS
AS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Single Pulsed Avalanche Energy
Avalanche Current
mJ
A
12.9
4.0
AR
E
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
mJ
V/ns
W
AR
dv/dt
6.5
Power Dissipation (T
= 25°C) *
2.5
P
A
D
Power Dissipation (T
= 25°C)
40
W
C
– Derate above 25°C
Operating and Storage
T
e
mperature Range
0.32
-55 to +150
W/°C
°C
T , T
J
STG
Maximum lead temperature for soldering purposes,
1/8
”
from case for 5 seconds
T
300
°C
L
Thermal Characteristics
Symbol
Parameter
Typ
—
Max
3.13
50
Units
°C
/
W
°C
/
W
°C
/
W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
θ
JC
θ
JA
θ
JA
—
—
110
* When mounted on the minimum pad size recommended (PCB Mount)
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Electrical Characteristics
T =
25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
T
y
p
Max
Units
Off Characteristics
BV
V
= 0
V
, I
=
2
50
µ
A
GS D
Drain-Source Breakdown Voltage
80
—
—
—
—
V
DSS
∆
BV
Breakdown Voltage
T
e
mperature
Coefficient
DSS
J
I
= 250
µ
A, Referenced to 25°C
0.08
V/°C
D
/
I
∆
T
V
V
V
V
= 80
V
, V
= 0 V
—
—
—
—
—
—
—
—
1
µ
A
µ
A
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 64
V
, T
=
1
25°C
10
DS
GS
GS
C
I
I
= 20
V
, V
= 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
100
-100
GSSF
DS
= -20
V
, V
= 0 V
GSSR
DS
On Characteristics
V
V
V
V
V
= V
, I
= 250
µ
A
Gate Threshold Voltage
1.0
—
—
2.0
V
Ω
S
GS(th)
DS
GS
D
= 10
V
, I
=
6
.45 A
R
Static Drain-Source
On-Resistance
0.076 0.100
0.090 0.115
GS
GS
D
DS(on)
= 5
V
, I
=
6
.45 A
D
(Note 4)
g
= 25
V
, I
=
6
.45 A
Forward Transconductance
—
11.7
—
FS
DS
D
Dynamic Characteristics
C
C
C
Input Capacitance
—
—
—
400
120
29
520
155
37
pF
pF
pF
iss
V
= 25
V
, V
= 0 V,
GS
DS
Output Capacitance
oss
rss
f = 1.0 MHz
Reverse Transfer Capacitance
Switching Characteristics
t
t
t
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
—
—
—
—
—
—
—
7
25
590
50
ns
ns
d(on)
V
= 40
V
, I
=
1
6.5 A,
DD
D
290
20
r
R
= 25
Ω
G
ns
d(off)
f
(Note 4, 5)
(Note 4, 5)
75
160
11.5
—
ns
Q
Q
Q
8.8
2.0
5.4
nC
nC
nC
g
V
V
= 64
V
, I
=
1
6.5 A,
DS
D
= 5 V
gs
gd
GS
—
Drain-Source Diode Characteristics and Maximum Ratings
I
Maximum Continuous Drain-Source Diode Forward Current
—
—
—
—
—
—
—
12.9
51.6
1.5
—
A
A
S
I
Maximum Pulsed Drain-Source Diode Forward Current
SM
V
t
V
V
= 0
V
, I
=
1
2.9 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
—
V
SD
GS
S
= 0
V
, I
=
1
6.5 A,
55
85
ns
nC
rr
GS
S
(Note 4)
dI /
dt = 100 A/
µ
s
Q
Reverse Recovery Charge
—
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.83mH, I
= 12.9A, V
= 25V, R
= 25
Ω,
Starting T =
25°C
AS
DD
G
J
3. I
≤
16.5A, di/dt
≤
300A/
µ
s, V
≤
BV
Starting T =
25°C
SD
DD
DSS,
J
4. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
5. Essentially independent of operating temperature
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Typical Characteristics
V
GS
Top :
10.0 V
8.0 V
6.0 V
5.0 V
4.5 V
4.0 V
3.5 V
10
1
10
1
Bottom :
3.0 V
℃
150
10
0
℃
25
℃
-55
※
Notes :
※
Notes :
μ
10
0
1. V
D
S
= 25V
1. 250
s Pulse Test
2. T
C
= 25
μ
2. 250
s Pulse Test
℃
-1
10
10
-1
10
0
10
1
0
2
4
6
8
10
V
GS
, Gate-Source Voltage
[V]
V
DS
, Drain-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.4
0.3
0.2
0.1
0.0
10
1
V
G
S
= 5V
V
G
S
= 10V
10
0
※
Notes :
℃
150
℃
25
1. V
G
S
= 0V
※
℃
Note : T = 25
μ
2. 250
s Pulse Test
J
-1
10
0
10
20
30
40
50
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
I
D
, Drain Current
[A]
V
S
D
, Source-Drain Voltage
[V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperature
1100
1000
900
800
700
600
500
400
300
200
100
0
12
10
8
C
iss
= C
gs
+
C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
rss
= C
C
gd
V
DS
= 40V
V
DS
= 64V
※
Notes :
C
iss
1. V
GS
= 0 V
2. f = 1 MHz
6
C
oss
4
C
rss
2
※
Note : I
D
= 16.5A
14
0
-1
10
10
0
10
1
0
2
4
6
8
10
12
16
Q
G
, Total Gate Charge [nC]
V
DS
, Drain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Typical Characteristics
(Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※
N
otes :
1. V
G
S
= 0 V
2. I
D
=
2
50
μ
A
0.9
※
Notes :
1. V
G
S
= 10 V
2. I
D
= 6.45 A
0.8
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
o
C
]
T
J
, Junction Temperature [
o
C
]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
15
12
9
Operation in This Area
is Limited by R
DS(on)
10
2
10
1
10
0
100
µ
s
1
m
s
10 ms
DC
6
※
Notes :
1. T
C
= 25
o
2. T
J
= 150
o
3
C
C
3. Single Pulse
-1
0
25
10
10
0
10
1
10
2
50
75
100
125
150
℃
T
C
, Case Temperature [
]
V
DS
,
D
rain-Source Voltage [V]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0
.
5
1 0
0
※
N o
t
e s
1 .
Z
θ
J
C
(
t)
2 .
D u
t
y
F a c to r,
D = t
1
/
t
2
:
0
.
2
℃
/W M
a x .
=
3
.
1 3
0
.
1
3 .
T
J M
–
T
C
=
P
D
* Z
θ
J
C
(
t)
M
0
.
0 5
P
DM
0
.
0 2
1
0
–
1
0
.
0 1
t
1
s in g le
p u ls e
t
2
1 0
–
5
1
0
–
4
1 0
–
3
1 0
–
2
1 0
–
1
1 0
0
1 0
1
t
1
, S
q u a
r
e
W a
v e
P u ls e
D u ra tio n
[s e c ]
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Gate Charge Test Circuit & Waveform
V
GS
Same Type
50K
Ω
as DUT
Q
g
12V
200nF
5V
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
5V
t
d(on)
t
r
t
d(off)
t
f
t
on
t
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
DSS
——————–
BV
DSS
– V
DD
L
1
2
2
—-
E
AS
=
L
I
AS
V
DS
I
D
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
DD
V
DS
(t)
DUT
10V
t
p
t
p
Time
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
————————–
V
GS
D =
Gate Pulse Period
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Package Dimensions
DPAK
6.60
±
0.20
5.34
±
0.30
2.30
±
0.10
0.50
±
0.10
(0.50)
(4.34)
(0.50)
MAX0.96
0.76
±
0.10
0.50
±
0.10
1.02
±
0.20
2.30
±
0.20
2.30TYP
2.30TYP
[2.30
±
0.20]
[2.30
±
0.20]
6.60
±
0.20
(5.34)
(5.04)
(1.50)
(2XR0.25)
0.76
±
0.10
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
Package Dimensions
(Continued)
IPAK
2.30
±
0.20
0.50
±
0.10
6.60
±
0.20
5.34
±
0.20
(0.50)
(4.34)
(0.50)
MAX0.96
0.76
±
0.10
0.50
±
0.10
2.30TYP
2.30TYP
[2.30
±
0.20]
[2.30
±
0.20]
©2000 Fairchild Semiconductor International
Rev. A2, December 2000
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
VCX™
ACEx™
FASTr™
QFET™
Bottomless™
CoolFET™
CROSSVOLT™
DOME™
GlobalOptoisolator™
GTO™
HiSeC™
QS™
QT Optoelectronics™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
ISOPLANAR™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
POP™
E
2
CMOS™
EnSigna™
FACT™
FACT Quiet Series™
FAST
®
PowerTrench
®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
INTERNATIONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2000 Fairchild Semiconductor International
Rev. F1
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Contents
General description
|
Features
|
Product
status/pricing/packaging
Support
General description
representatives
These N-Channel enhancement mode power
field effect transistors are produced using
Fairchild’s proprietary, planar stripe, DMOS
technology.
Quality and reliability
Print version
Design tools
This advanced technology is especially tailored
to minimize on-state resistance, provide
superior switching performance, and withstand
a high energy pulse in the avalanche and
commutation modes. These devices are well
suited for low voltage applications such as
automotive, high efficiency switching for
DC/DC converters, and DC motor control.
back to top
Features
●
12.9A, 80V, R
10V
= 0.1
Ω
@V
=
DS(on)
GS
●
●
●
●
●
●
Low gate charge (typical 8.8nC)
Low Crss (typical 29pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
175°C maximum junction temperature
rating
●
Low level gate drive requirments
allowing direct operation from logic
drives
back to top
Product status/pricing/packaging
Product
FQD17N08LTF
FQD17N08LTM
Product status
Pricing*
Package type
Leads Packing
method
Full Production
Full Production
$0.437 TO-252(DPAK)
$0.437 TO-252(DPAK)
2
2
TAPE REEL
TAPE REEL
* 1,000 piece Budgetary Pricing
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