onsemi-FQD6N50CTF
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®
QFET
FQD6N50C / FQU6N50C
500V N-Channel MOSFET
General Description
Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe,
DMOS technology.
•
•
•
•
•
•
4.5A, 500V, R
= 1.2
Ω
@V =
10 V
DS(on) GS
Low gate charge (typical 19nC)
Low Crss (typical 15pF)
Fast switching
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switched mode power supplies,
active power factor correction, electronic lamp ballasts
based on half bridge topology.
100% avalanche tested
Improved dv/dt capability
D
!
D
●
◀
▲
●
●
!
G
I-PAK
FQU Series
D-PAK
FQD Series
G
S
G D S
!
S
Absolute Maximum Ratings
T =
25°C unless otherwise noted
C
Symbol
Parameter
FQD6N50C / FQU6N50C
Units
V
A
V
I
Drain-Source Voltage
Drain Current
500
4.5
DSS
– Continuous (T
= 25°C)
D
C
– Continuous (T
= 100°C)
2.7
A
C
I
(Note 1)
Drain Current
– Pulsed
18
A
DM
V
E
I
E
dv/dt
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
±
30
300
4.5
6.1
4.5
V
mJ
A
mJ
V/ns
W
GSS
AS
(Note 2)
(Note 1)
(Note 1)
(Note 3)
AR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
AR
Power Dissipation (T
= 25°C)*
2.5
61
A
P
Power Dissipation (T
= 25°C)
W
D
C
– Derate above 25°C
Operating and Storage
T
e
mperature Range
0.49
-55 to +150
W/°C
°C
T , T
J
STG
Maximum lead temperature for soldering purposes,
1/8
”
from case for 5 seconds
T
300
°C
L
Thermal Characteristics
Symbol
Parameter
Typ
Max
2.05
50
Units
°C
/
W
°C
/
W
°C
/
W
R
R
R
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
–
–
–
θ
JC
θ
JA
θ
JA
110
* When mounted on the minimum pad size recommended (PCB Mount)
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Electrical Characteristics
T =
25°C unless otherwise noted
C
Symbol
Parameter
Test Conditions
Min
T
y
p
Max
Units
Off Characteristics
BV
∆
BV
/
V
I
= 0 V, I
=
2
50
µ
A
GS D
Drain-Source Breakdown Voltage
Breakdown Voltage
T
e
mperature
Coefficient
500
—
—
—
—
V
DSS
DSS
∆
T
= 250
µ
A, Referenced to 25°C
0.8
V/°C
D
J
I
V
V
V
V
= 500
V
, V
= 0 V
—
—
—
—
—
—
—
—
1
10
100
-100
µ
A
µ
A
nA
nA
DSS
DS
GS
Zero Gate Voltage Drain Current
= 400
V
, T
=
1
25°C
DS
GS
GS
C
I
= 30
V
, V
= 0 V
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
GSSF
GSSR
DS
I
= -30
V
, V
= 0 V
DS
On Characteristics
V
R
V
V
V
= V
, I
= 250
µ
A
Gate Threshold Voltage
Static Drain-Source
On-Resistance
2.0
—
—
4.0
1.2
—
V
Ω
S
GS(th)
DS
GS
DS
GS
D
DS(on)
= 10
V
, I
=
2
.25A
1.0
4.5
D
g
= 40
V
, I
=
2
.25A
(Note 4)
Forward Transconductance
—
FS
D
Dynamic Characteristics
C
C
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
—
—
—
540
80
15
700
105
20
pF
pF
pF
iss
V
= 25
V
, V
= 0 V,
GS
DS
oss
rss
f = 1.0 MHz
Switching Characteristics
t
t
t
t
Q
Q
Q
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
T
o
tal Gate Charge
Gate-Source Charge
Gate-Drain Charge
—
—
—
—
—
—
—
10
35
55
45
19
2.8
8.8
30
80
120
100
25
—
ns
ns
ns
d(on)
V
R
= 250
V
, I
=
4
.5A,
= 25
Ω
DD
D
r
G
d(off)
f
(Note 4, 5)
(Note 4, 5)
ns
nC
nC
nC
g
V
V
= 400
V
, I
=
4
.5A,
DS
GS
D
= 10 V
gs
gd
—
Drain-Source Diode Characteristics and Maximum Ratings
I
I
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
—
—
—
—
—
—
—
—
260
1.6
4.5
18
1.4
—
A
A
V
ns
µ
C
S
SM
V
t
V
V
= 0 V, I
=
4.5 A
Drain-Source Diode Forward Voltage
Reverse Recovery Time
SD
GS
S
= 0 V, I
=
4
.5
A,
rr
GS
S
dI /
dt = 100 A/
µ
s
(Note 4)
Q
Reverse Recovery Charge
—
F
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L =
26.6 mH, I
= 4.5A, V
= 50V, R
= 25
Ω,
Starting T =
25°C
AS
DD
G
DSS,
J
3. I
≤
4.5A, di/dt
≤
200A/
µ
s, V
≤
BV
Starting T =
25°C
J
SD
DD
4. Pulse Test : Pulse width
≤
300
µ
s, Duty cycle
≤
2%
5. Essentially independent of operating temperature
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Typical Characteristics
V
G
S
Top :
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
10
1
10
0
10
1
10
0
150
o
C
Botto
m
:
5
.0
V
25
o
C
-55
o
C
-1
10
※
Notes :
1. 250µ s Pulse Test
2. T
C
= 25
※
Notes :
1. V
D
S
= 40V
℃
2. 250µ s Pulse Test
-1
10
-1
10
10
0
10
1
2
4
6
8
10
V
D
S
,
D
rain-Source Voltage [V]
V
G
S
,
G
ate-Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
3.5
10
1
10
0
3.0
2.5
2.0
1.5
1.0
0.5
V
G
S
=
1
0V
V
GS
=
2
0V
150
℃
25
℃
※
Notes :
1. V
G
S
= 0V
2. 250µ s Pulse Test
※
Not
e
: T =
2
5
℃
J
-1
10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
5
10
15
V
S
D
, Source-Drain voltage [V]
I
D
,
D
rain Current [A]
Figure 4. Body Diode Forward Voltage
Variation with Source Current
and Temperature
Figure 3. On-Resistance Variation
vs
Drain Current and Gate Voltage
12
10
8
1200
1000
800
600
400
200
0
C
iss
=
C
g
s
+
C
g
d
(
C
d
s
=
s
horted)
C
oss
= C
+ C
gd
C
rss
= C
d
s
gd
V
DS
= 100V
V
DS
= 250V
C
iss
V
DS
= 400V
C
oss
6
4
※
Note ;
C
1. V
G
S
= 0 V
2. f
=
1
M
Hz
rss
2
※
Not
e
:
I
D
= 4.5A
0
10
0
10
1
-1
0
5
10
15
20
10
Q
G
,
T
otal Gate Charge [nC]
V
D
S
,
D
rain-Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Typical Characteristics
(Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
※
Notes :
0.9
0.8
1. V
= 0 V
2. I
D
G
=
S
2
50 µ A
※
Notes :
1. V
= 10 V
2. I
D
G
=
S
2
.25 A
-100
-50
0
50
100
150
200
-100
-50
0
50
100
150
200
T,
J
unction Temperature [
o
C
]
T,
J
unction Temperature [
o
C
]
J
J
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
5
4
3
2
1
0
10
2
Operation in This Area
is Limited by R
D
S(on)
10
1
10
0
100
1
m
s
10 ms
100 ms
µ
s
DC
-1
10
※
Notes :
1. T
C
= 25
o
C
2. T
= 150
o
C
J
3. Single Pulse
-2
10
10
0
10
1
10
2
10
3
25
50
75
100
125
150
V
D
S
,
D
rain-Source Voltage [V]
T
C
,
C
ase Temperature [
℃
]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
10
0
10
-1
10
-2
D
=
0.5
0.2
※
No
t
es :
0.1
1. Z
(t) = 2.05
℃
/W Max.
2.
D
θ
u
J
t
C
y
F
actor, D=t
1
/t
2
3. T
J
M
–
T
C
=
P
D M
*
Z
θ
J
C
(t)
0.05
0.02
0.01
single pulse
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
,
S
quare W
ave Pulse Duration [sec]
Figure 11. Transient Thermal Response Curve
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Gate Charge Test Circuit & Waveform
V
GS
Same Type
50K
Ω
as DUT
10V
Q
g
12V
200nF
300nF
V
DS
V
GS
Q
gs
Q
gd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
R
L
V
DS
90%
V
DS
V
DD
V
GS
R
G
10%
V
GS
DUT
10V
t
d
(
o
n)
t
r
t
d(off)
t
f
t
on
t
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
DSS
L
1
2
—-
——————–
BV
DSS
– V
DD
E
AS
=
L
I
AS
V
DS
I
D
2
BV
DSS
I
AS
R
G
V
DD
I
D
(t)
V
DD
V
DS
(t)
DUT
10V
t
p
t
p
Time
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
V
DS
_
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
• dv/dt controlled by
R
G
• I
SD
controlled by pulse period
Gate Pulse Width
V
GS
————————–
Gate Pulse Period
D =
10V
( Driver )
I
FM
, Body Diode Forward Current
I
SD
di/dt
( DUT )
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
SD
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Package Dimensions
D-PAK
6.60
±
0.20
5.34
±
0.30
2.30
±
0.10
0.50
±
0.10
(0.50)
(4.34)
(0.50)
MAX0.96
0.76
±
0.10
0.50
±
0.10
1.02
±
0.20
2.30
±
0.20
2.30TYP
2.30TYP
[2.30
±
0.20]
[2.30
±
0.20]
6.60
±
0.20
(5.34)
(5.04)
(1.50)
(2XR0.25)
0.76
±
0.10
Dimensions in Millimeters
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
Package Dimensions
(Continued)
I-PAK
2.30
±
0.20
0.50
±
0.10
6.60
±
0.20
5.34
±
0.20
(0.50)
(4.34)
(0.50)
MAX0.96
0.76
±
0.10
0.50
±
0.10
2.30TYP
2.30TYP
[2.30
±
0.20]
[2.30
±
0.20]
Dimensions in Millimeters
©2004 Fairchild Semiconductor Corporation
Rev. B, June 2004
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The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
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PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
©2004 Fairchild Semiconductor Corporation
Rev. I11
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500V N-Channel Advance Q-FET C-Series
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Contents
•
General description
•
Features
•
Qualification Support
Product Change Notices
(PCNs)
Datasheet
•
Product status/pricing/packaging
•
Order Samples
Download this
datasheet
Support
Sales support
Quality and reliability
Design center
General description
These N-Channel enhancement mode power field effect ransistors are
produced using Fairchild.s proprietary, planar stripe, DMOS technology.
e-mail this datasheet
This advanced technology has been especially tailored to minimize on-state
resistance, provide superior switching performance, and withstand high
energy pulse in the avalanche and commutation mode. These devices are
well suited for high efficiency switched mode power supplies, active power
factor correction, electronic lamp ballasts based on half bridge topology.
This page
Print version
back to top
Features
z
4.5A, 500V, R
= 1.2
Ω
@V =
10V
DS(on) GS
z
z
z
z
z
Low gate charge (typical 19nC)
Low Crss (typical 15pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
back to top
Product status/pricing/packaging
Product
Product status
Pb-free Status
Pricing*
Package type
Leads Packing
method
Package Marking Convention**
FQD6N50CTF
FQD6N50CTM
Full Production
Full Production
$0.90
TO-252(DPAK)
$0.90
TO-252(DPAK)
2
2
TAPE REEL
TAPE REEL
Line 1: &
(3-Digit Date Code)
3
Line 1:
(Fairchild logo)
$Y
&
Z
(Asm. Plant Code)
&E& (3-Digit
Date Code)
3
Line 2: FQD Line 3: 6N50C
* Fairchild 1,000 piece Budgetary Pricing
** A sample button will appear if the part is available through Fairchild’s on-line samples program. If there is no sample button, please
contact a
to obtain samples
Indicates product with Pb-free second-level interconnect. For more information
click here.
Package marking information for product FQD6N50C is available.
Click here for more information
.
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Qualification Support
Click on a product for detailed qualification data
Product
FQD6N50CTF
FQD6N50CTM
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